JPH09266130A - Multilayer capacitor - Google Patents

Multilayer capacitor

Info

Publication number
JPH09266130A
JPH09266130A JP8072875A JP7287596A JPH09266130A JP H09266130 A JPH09266130 A JP H09266130A JP 8072875 A JP8072875 A JP 8072875A JP 7287596 A JP7287596 A JP 7287596A JP H09266130 A JPH09266130 A JP H09266130A
Authority
JP
Japan
Prior art keywords
internal
electrode
multilayer capacitor
electrodes
internal electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8072875A
Other languages
Japanese (ja)
Inventor
Yoshio Akimoto
Hideki Kabasawa
Kiwa Okino
英樹 樺澤
喜和 沖野
欣男 秋本
Original Assignee
Taiyo Yuden Co Ltd
太陽誘電株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd, 太陽誘電株式会社 filed Critical Taiyo Yuden Co Ltd
Priority to JP8072875A priority Critical patent/JPH09266130A/en
Publication of JPH09266130A publication Critical patent/JPH09266130A/en
Granted legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer capacitor which is free of any internal structural defect. SOLUTION: In the multilayer capacitor 20, a plurality of internal electrodes 22 are laminated and connected through dielectric layers 21 to a common external electrode 24. The internal electrodes 22 are set to have different lengths. The tip ends of the internal electrodes 22 are set not to be present at identical vertical positions. The numbers of the internal electrodes 22 and dielectric layers 21 are made uniform in a vertical direction of the stack. Accordingly, a structural defect resulting from an internal stress, which occurred at the time of manufacturing a prior art, can be suppressed and, even at the time of forming a small-size multilayer capacitor, its yield can be improved.

Description

【発明の詳細な説明】 Detailed Description of the Invention

【0001】 [0001]

【発明が属する技術分野】本発明は、積層コンデンサに関し、特に静電容量の小さな小型の積層コンデンサに関するものである。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor, and more particularly to a small multilayer capacitor having a small capacitance.

【0002】 [0002]

【従来の技術】図2乃至図4に従来例の積層コンデンサ
を示す。図2は分解斜視図、図3は平面図、図4は図3
のA−A線矢視方向断面図である。
2. Description of the Related Art FIGS. 2 to 4 show a conventional multilayer capacitor. 2 is an exploded perspective view, FIG. 3 is a plan view, and FIG.
3 is a sectional view taken along line AA of FIG.

【0003】図において、10は積層コンデンサで、誘
電体層11と内部電極12とを交互に積層してなる素体
13と、素体13の両端部において内部電極を交互に並
列に接続している一対の外部電極14とから構成されて
いる。
[0003] In the drawing, reference numeral 10 denotes a multilayer capacitor in which a dielectric body 13 formed by alternately laminating dielectric layers 11 and internal electrodes 12 and internal electrodes are alternately connected in parallel at both ends of the dielectric body 13. And a pair of external electrodes 14.

【0004】内部電極12は、誘電体層11の中央領域
付近に設けられた内部電極片12aと、外部電極14に
沿って外部電極14に接続した状態で設けられた内部電
極引出部12bとから成り、内部電極片12aは内部電
極引出部12bを介して外部電極14に接続されてい
る。
The internal electrode 12 is composed of an internal electrode piece 12a provided near the central region of the dielectric layer 11 and an internal electrode lead portion 12b provided along the external electrode 14 and connected to the external electrode 14. The internal electrode piece 12a is connected to the external electrode 14 via the internal electrode lead-out portion 12b.

【0005】誘電体層11は矩形のシート上のセラミッ
ク焼結体からなり、セラミック焼結体は、例えばチタン
酸バリウム等を主成分とする誘電体磁器材料から形成さ
れている。内部電極12は金属ペーストを焼結させた金
属薄膜からなり、金属ペーストとしては、例えばPdや
Ag−Pdのような貴金属材料を主成分とするものが使
用されている。外部電極14も内部電極12と同様の材
料により形成され、表面には半田濡れ性をよくするため
に半田メッキが施されている。
[0005] The dielectric layer 11 is formed of a ceramic sintered body on a rectangular sheet, and the ceramic sintered body is formed of a dielectric ceramic material containing, for example, barium titanate as a main component. The internal electrode 12 is formed of a metal thin film obtained by sintering a metal paste. As the metal paste, for example, an electrode mainly containing a noble metal material such as Pd or Ag-Pd is used. The external electrode 14 is also formed of the same material as the internal electrode 12, and the surface is plated with solder to improve solder wettability.

【0006】 [0006]

【発明が解決しようとする課題】ところで、近年、移動通信機器等に使用される通信用の周波数が高周波帯(G
Hz帯)へ移行してきており、これに伴って移動通信機器等に使用される積層コンデンサも小型化への対応を余儀なくされている。
In recent years, communication frequencies used in mobile communication devices and the like have been changed to high frequency bands (G-bands).
(Hz band), and along with this, the multilayer capacitors used in mobile communication devices and the like have been forced to respond to miniaturization.

【0007】しかしながら、積層コンデンサを形成する
場合、内部電極層と誘電体層を交互に積層しているた
め、内部電極が形成されている部分と内部電極が形成さ
れていない部分とでは積層数が異なるので、加圧の際に
応力が生じて構造欠陥(デラミネーション、クラック
等)の発生率が大きくなってしまう。これは、小型の積
層コンデンサを製造する際に顕著に現れ、歩留まりの低
下を招いていた。
However, in the case of forming a multilayer capacitor, since the internal electrode layers and the dielectric layers are alternately laminated, the number of laminated layers is different between the portion where the internal electrodes are formed and the portion where the internal electrodes are not formed. Since they are different, stress is generated at the time of pressurization and the occurrence rate of structural defects (delamination, cracks, etc.) increases. This appears remarkably when manufacturing a small multilayer capacitor, leading to a decrease in yield.

【0008】本発明の目的は上記の問題点に鑑み、内部構造欠陥のない積層コンデンサを提供することにある。 In view of the above problems, it is an object of the present invention to provide a multilayer capacitor having no internal structural defect.

【0009】 [0009]

【課題を解決するための手段】本発明は上記の目的を達
成するために請求項1では、誘電体層と内部電極層とを
交互に積層してなる直方体形状の素体と、該素体の両端
部において該内部電極層に形成された内部電極を交互に
並列に接続している一対の外部電極とからなる積層コン
デンサであって、同一の外部電極に接続された内部電極
はそれぞれ異なる長さ又は幅に設定されている積層コン
デンサを提案する。
In order to achieve the above object, the present invention provides a rectangular parallelepiped shaped element body in which dielectric layers and internal electrode layers are alternately laminated, and the element body. Is a multilayer capacitor composed of a pair of external electrodes in which the internal electrodes formed on the internal electrode layers are alternately connected in parallel at both ends of the internal electrode layer, and the internal electrodes connected to the same external electrode have different lengths. We propose a multilayer capacitor that is set to the width or width.

【0010】該積層コンデンサによれば、同一の外部電
極に接続された内部電極の長さ又は幅はそれぞれ異なる
長さに設定されているため、それぞれの内部電極の先端
或いは側端は上下方向同一位置に存在しないので、上下
層方向における積層数をほぼ均一化することができ、内
部応力の発生が低減される。
According to the multilayer capacitor, since the lengths or widths of the internal electrodes connected to the same external electrode are set to different lengths, the tips or side ends of the internal electrodes are vertically identical. Since it does not exist at the position, the number of stacked layers in the upper and lower layers can be made substantially uniform, and the generation of internal stress can be reduced.

【0011】また、請求項2では、請求項1記載の積層
コンデンサにおいて、一方の外部電極に接続された最外
層の内部電極は、該内部電極の先端部が、前記素体の上
下面に形成された他方の外部電極に対向しない長さに設
定されている積層コンデンサを提案する。
According to a second aspect of the present invention, in the multilayer capacitor according to the first aspect, the innermost electrode of the outermost layer connected to one outer electrode is formed such that the tip of the inner electrode is formed on the upper and lower surfaces of the element body. We propose a multilayer capacitor that is set to a length that does not face the other external electrode.

【0012】該積層コンデンサによれば、一方の外部電極に接続された最外層の内部電極と他方の外部電極とが対向しないので、これらの間に浮遊容量が発生しない。 According to the multilayer capacitor, the inner electrode of the outermost layer connected to one outer electrode and the other outer electrode do not face each other, so that no stray capacitance is generated between them.

【0013】 [0013]

【発明の実施の形態】以下、図面に基づいて本発明の一
実施形態を説明する。図1は一実施形態における一実施
例の積層コンデンサを示す分解斜視図、図5は側面断面
図である。図において、20は積層コンデンサで、誘電
体層21と内部電極22とを交互に積層してなる素体2
3と、素体23の両端部において内部電極22を交互に並列に接続している一対の外部電極24とから構成されている。 It is composed of 3 and a pair of external electrodes 24 in which internal electrodes 22 are alternately connected in parallel at both ends of the element body 23. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an exploded perspective view showing a multilayer capacitor of an example of an embodiment, and FIG. 5 is a side sectional view. In the figure, reference numeral 20 designates a multilayer capacitor, which is an element body 2 in which dielectric layers 21 and internal electrodes 22 are alternately laminated. TFTP OF THE confirming An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an excited perspective view showing a multilayer capacitor of an example of an embodiment, and FIG. 5 is a side sectional view In the figure, reference nucleus 20 designates a multilayer capacitor, which is an element body 2 in which dielectric layers 21 and internal electrodes 22 are particularly laminated.
3 and a pair of external electrodes 24 in which the internal electrodes 22 are alternately connected in parallel at both ends of the element body 23. 3 and a pair of external electrodes 24 in which the internal electrodes 22 are appropriately connected in parallel at both ends of the element body 23.

【0014】誘電体層21は、矩形のシート状のセラミック焼結体からなり、焼結体は例えばチタン酸バリウムを主成分とするグリーンシートを焼成して形成した誘電体磁器材料からなる。 The dielectric layer 21 is made of a rectangular sheet-shaped ceramic sintered body, and the sintered body is made of a dielectric ceramic material formed by firing a green sheet containing barium titanate as a main component, for example.

【0015】誘電体層21を介して隣り合う一対の内部電極22のそれぞれは、外部電極24に沿って設けられた内部電極引出部22aと、この内部電極引出部22a
に基端部が接続された内部電極片22bとから構成されている。 It is composed of an internal electrode piece 22b to which a base end portion is connected to. この内部電極片22bは矩形になっており、内部電極片22bの長辺は外部電極24に対して略直角になっている。 The internal electrode piece 22b has a rectangular shape, and the long side of the internal electrode piece 22b is substantially perpendicular to the external electrode 24. Each of the pair of internal electrodes 22 adjacent to each other through the dielectric layer 21 has an internal electrode lead-out portion 22a provided along the external electrode 24 and the internal electrode lead-out portion 22a. Each of the pair of internal electrodes 22 adjacent to each other through the dielectric layer 21 has an internal electrode lead-out portion 22a provided along the external electrode 24 and the internal electrode lead-out portion 22a.
And an internal electrode piece 22b to which the base end is connected. The internal electrode piece 22b has a rectangular shape, and the long side of the internal electrode piece 22b is substantially perpendicular to the external electrode 24. And an internal electrode piece 22b to which the base end is connected. The internal electrode piece 22b has a rectangular shape, and the long side of the internal electrode piece 22b is substantially perpendicular to the external electrode 24.

【0016】また、各内部電極22における内部電極片22bの幅は各々等しく形成されている。 The widths of the internal electrode pieces 22b in the internal electrodes 22 are equal to each other.

【0017】一方、同一の外部電極24に接続された複数の内部電極22は、それぞれ異なる長さに設定され、
それぞれの先端が上下方向同一位置に重ならないようになっている。
On the other hand, the plurality of internal electrodes 22 connected to the same external electrode 24 are set to have different lengths,
The tips of each do not overlap in the same position in the vertical direction.

【0018】これらの内部電極22は導電性ペーストの
薄膜を焼結させた金属薄膜からなり、導電性ペーストと
しては、例えばパラジウム粉末を主成分とするものが使
用されている。外部電極24も内部電極22と同様の材
料により形成され、表面には半田濡れ性をよくするため
に半田メッキが施されている。
These internal electrodes 22 are made of a metal thin film obtained by sintering a thin film of a conductive paste, and as the conductive paste, for example, one containing palladium powder as a main component is used. The external electrode 24 is also formed of the same material as the internal electrode 22, and its surface is plated with solder to improve solder wettability.

【0019】この積層コンデンサは次のようにして製造
した。まず、誘電体の原料粉末に有機バインダーを15
重量%添加し、さらに水を50重量%加え、これらをボ
ールミルに入れて十分に混合し、誘電体磁器原料のスラ
リーを作成した。
This multilayer capacitor was manufactured as follows. First, an organic binder was added to the dielectric raw material powder.
% By weight, and further 50% by weight of water, and these were put into a ball mill and mixed well to prepare a slurry of a dielectric ceramic raw material.

【0020】次に、このスラリーを真空脱泡器に入れて
脱泡した後、リバースロールコーターに入れ、ポリエス
テルフィルム上にこのスラリーからなる薄膜を形成し、
この薄膜をポリエステルフィルム上で100℃に加熱し
て乾燥させ、これを打ち抜いて、10cm角、厚さ約2
0μmのグリーンシートを得た。
Next, after putting this slurry in a vacuum defoamer to defoam it, put it in a reverse roll coater to form a thin film of this slurry on a polyester film,
This thin film is dried by heating to 100 ° C. on a polyester film, punched out, and 10 cm square, about 2 mm thick.
A green sheet of 0 μm was obtained.

【0021】一方、平均粒径が1.5μmのパラジウム粉末10gと、エチルセルロース0.9gをブチルカルビトール9.1gに溶解させたものとを攪拌器に入れ、
10時間攪拌することにより内部電極用の導電性ペーストを得た。
On the other hand, 10 g of palladium powder having an average particle size of 1.5 μm and 0.9 g of ethyl cellulose dissolved in 9.1 g of butyl carbitol were placed in a stirrer.
By stirring for 10 hours, a conductive paste for an internal electrode was obtained.

【0022】この後、上述した内部電極のパターンを5
0個有する各スクリーンを用いて、上記グリーンシートの片面にこの導電性ペーストからなる内部電極のパターンを各々印刷し、これを乾燥させた。 Using each screen having 0 screens, a pattern of an internal electrode made of this conductive paste was printed on one side of the green sheet, and this was dried. After that, the above-mentioned internal electrode pattern is applied to 5 After that, the above-mentioned internal electrode pattern is applied to 5
Using each of the screens having zero, a pattern of the internal electrode made of the conductive paste was printed on one surface of the green sheet, and dried. Using each of the screens having zero, a pattern of the internal electrode made of the conductive paste was printed on one surface of the green sheet, and dried.

【0023】次に、上記印刷面を上にしてグリーンシートを複数枚積層し、さらにこの積層物の上下両面に印刷の施されていないグリーンシートを積層した。次いで、
この積層物を約50℃の温度で厚さ方向に約40トンの圧力を加えて圧着させた。 This laminate was pressure-bonded at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. この後、この積層物を格子状に裁断し、約50個の積層チップを得た。 After that, the laminate was cut in a grid pattern to obtain about 50 laminated chips. Next, a plurality of green sheets were laminated with the printed surface facing upward, and further, unprinted green sheets were laminated on the upper and lower surfaces of this laminate. Then Next, a plurality of green sheets were laminated with the printed surface facing upward, and further, unprinted green sheets were laminated on the upper and lower surfaces of this laminate. Then
This laminate was pressed at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. Thereafter, the laminate was cut into a lattice to obtain about 50 laminated chips. This laminate was pressed at a temperature of about 50 ° C. by applying a pressure of about 40 tons in the thickness direction. Laminated was cut into a lattice to obtain about 50 laminated chips.

【0024】次に、この積層チップを雰囲気焼成可能な
炉に入れ、大気中で600℃まで加熱して、有機バイン
ダーを焼成させ、その後、炉の雰囲気を大気中雰囲気と
し、積層体チップの加熱温度を600℃から焼成温度の
1150℃(最高温度)を3時間保持した。この後、1
00℃/hrの速度で600℃まで降温し、室温まで冷
却して、焼結体チップを得た。
Next, this laminated chip is placed in a furnace capable of firing in an atmosphere and heated to 600 ° C. in the atmosphere to burn the organic binder, and thereafter, the atmosphere of the furnace is set in the atmosphere to heat the laminated chip. The temperature was maintained at 600 ° C. to 1150 ° C. (maximum temperature), which is the firing temperature, for 3 hours. After this, 1
The temperature was lowered to 600 ° C. at a rate of 00 ° C./hr and cooled to room temperature to obtain a sintered body chip. The temperature was lowered to 600 ° C. at a rate of 00 ° C./hr and cooled to room temperature to obtain a sintered body chip.

【0025】次いで、内部電極が露出する焼結体チップの側面に銀とガラスフリットとビヒクルからなる導電性ペーストを塗布して乾燥させ、これを大気中で800℃
の温度で15分間焼き付け、銀電極層を形成し、さらにこの上に銅を無電解メッキで被着させ、この上に電気メッキ法でPb−Sn半田層を設けて、一対の外部電極を形成した。これによって積層コンデンサが得られた。
Next, a conductive paste made of silver, glass frit and vehicle is applied to the side surface of the sintered body chip where the internal electrodes are exposed and dried, and this is dried at 800 ° C. in the atmosphere.

Baking at a temperature of 15 minutes to form a silver electrode layer, further depositing copper thereon by electroless plating, and providing a Pb-Sn solder layer thereon by electroplating to form a pair of external electrodes did. As a result, a multilayer capacitor was obtained. Baking at a temperature of 15 minutes to form a silver electrode layer, further depositing copper ceramics by electroless plating, and providing a Pb-Sn solder layer optically by electroplating to form a pair of external electrodes did. As a result, a multilayer capacitor was obtained.

【0026】前述の構成よりなる積層コンデンサによれば、一対の外部電極24に接続されたそれぞれの内部電極22はそれぞれ異なる長さに設定されているため、それぞれの内部電極の先端は上下方向同一位置に存在しない。 According to the multilayer capacitor having the above-described structure, since the internal electrodes 22 connected to the pair of external electrodes 24 are set to have different lengths, the tips of the internal electrodes are the same in the vertical direction. Does not exist in position.

【0027】従って、上下層方向における積層数をほぼ
均一化することができ、内部応力の発生を低減すること
ができるので、従来製造時に発生していた内部応力に起
因する構造欠陥を低減することができると共に、小型の
積層コンデンサを形成した場合にも歩留まりの向上を図
ることができる。
Therefore, since the number of stacked layers in the upper and lower layers can be made substantially uniform and the generation of internal stress can be reduced, the structural defects caused by the internal stress which have been conventionally produced can be reduced. In addition, the yield can be improved even when a small-sized multilayer capacitor is formed.

【0028】次に、本発明の第2の実施形態を説明す
る。図6は、第2の実施形態の積層コンデンサを示す側
面断面図である。図において、前述した第1の実施形態
と同一構成部分は同一符号をもって表しその説明を省略
する。また、第1の実施形態と第2の実施形態との相違
点は、同一外部電極24に接続された最外層の内部電極
22、即ち最上層と最下層の内部電極22の先端部が、
素体23の上下面に形成された他方の外部電極24に対向しないように、その長さを設定したことにある。 The length is set so as not to face the other external electrode 24 formed on the upper and lower surfaces of the element body 23. Next, a second embodiment of the present invention will be described. FIG. 6 is a side sectional view showing the multilayer capacitor of the second embodiment. In the figure, the same components as those in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted. Further, the difference between the first embodiment and the second embodiment is that the innermost electrode 22 of the outermost layer connected to the same outer electrode 24, that is, the tips of the innermost electrode 22 of the uppermost layer and the lowermost layer, Next, a second embodiment of the present invention will be described. FIG. 6 is a side sectional view showing the multilayer capacitor of the second embodiment. In the figure, the same components as those in the first embodiment described above are transfected by the same Reference numerals, and description thereof will be omitted. Further, the difference between the first embodiment and the second embodiment is that the innermost electrode 22 of the outermost layer connected to the same outer electrode 24, that is, the tips of the innermost electrode 22 of the uppermost layer and the lowermost layer,
The length is set so as not to face the other external electrode 24 formed on the upper and lower surfaces of the element body 23. The length is set so as not to face the other external electrode 24 formed on the upper and lower surfaces of the element body 23.

【0029】前述の構成よりなる積層コンデンサ20に
よれば、一方の外部電極24に接続された最外層の内部
電極22と他方の外部電極24とが対向しないため、こ
れらの間に浮遊容量が発生しないので、誤差を低減し、
ほぼ設計値の静電容量を得ることができる。
According to the multilayer capacitor 20 having the above-described structure, the inner electrode 22 of the outermost layer connected to the one outer electrode 24 and the other outer electrode 24 do not face each other, so that stray capacitance is generated between them. Since it does not, reduce the error,
It is possible to obtain an approximately designed capacitance.

【0030】尚、これらの実施形態は一例であり本発明がこれに限定されることはない。 These embodiments are merely examples, and the present invention is not limited to these.

【0031】また、前述した実施形態においては内部電極の長さをそれぞれ異なるように設定したが、図7に示す第3の実施形態のように、内部電極の幅をそれぞれ異なるように設定しても同様の効果を得ることができる。 Further, although the lengths of the internal electrodes are set to be different in the above-described embodiment, the widths of the internal electrodes are set to be different as in the third embodiment shown in FIG. Can also obtain the same effect.

【0032】[0032]

【発明の効果】以上説明したように本発明の請求項1に
よれば、同一の外部電極に接続された内部電極の長さ又
は幅はそれぞれ異なる長さに設定されているため、それ
ぞれの内部電極の先端或いは側端は上下方向同一位置に
存在せず、上下層方向における積層数をほぼ均一化する
ことができ、内部応力の発生を低減することができるの
で、従来製造時に発生していた内部応力に起因する構造
欠陥を低減することができると共に、小型の積層コンデ
ンサを形成した場合にも歩留まりの向上を図ることがで
きる。
As described above, according to claim 1 of the present invention, the lengths or widths of the internal electrodes connected to the same external electrode are set to different lengths. The tips or side edges of the electrodes do not exist at the same position in the vertical direction, the number of layers stacked in the vertical direction can be made substantially uniform, and the generation of internal stress can be reduced. It is possible to reduce structural defects caused by internal stress and improve the yield even when a small multilayer capacitor is formed.

【0033】また、請求項2によれば、上記の効果に加えて、一方の外部電極に接続された最外層の内部電極と他方の外部電極とが対向しないため、これらの間に浮遊容量が発生しないので、誤差を低減し、ほぼ設計値の静電容量を得ることができる。 According to the second aspect, in addition to the above effect, since the innermost electrode of the outermost layer connected to one outer electrode and the other outer electrode do not face each other, stray capacitance is present between them. Since it does not occur, it is possible to reduce the error and obtain a capacitance of approximately the design value.

【図面の簡単な説明】 [Brief description of drawings]

【図1】本発明の第1の実施形態の積層コンデンサを示す分解斜視図FIG. 1 is an exploded perspective view showing a multilayer capacitor according to a first embodiment of the present invention.

【図2】従来例の積層コンデンサを示す分解斜視図FIG. 2 is an exploded perspective view showing a conventional multilayer capacitor.

【図3】従来例の積層コンデンサを示す平断面図FIG. 3 is a cross-sectional plan view showing a conventional multilayer capacitor.

【図4】図3のA−A線矢視方向断面図FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図5】本発明の第1の実施例の積層コンデンサを示す側面断面図FIG. 5 is a side sectional view showing the multilayer capacitor of the first embodiment of the present invention.

【図6】本発明の第2の実施形態の積層コンデンサを示す側面断面図FIG. 6 is a side sectional view showing a multilayer capacitor according to a second embodiment of the present invention.

【図7】本発明の第3の実施形態の積層コンデンサを示す側面断面図FIG. 7 is a side sectional view showing a multilayer capacitor of a third embodiment of the present invention.

【符号の説明】 [Explanation of symbols]

20…積層コンデンサ、21…誘電体層、22…内部電極、22a…内部電極引出部、22b…内部電極片、2
3…素体、24…外部電極。
20 ... Multilayer capacitor, 21 ... Dielectric layer, 22 ... Internal electrode, 22a ... Internal electrode lead-out part, 22b ... Internal electrode piece, 2
3 ... Element body, 24 ... External electrodes.

Claims (2)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 誘電体層と内部電極層とを交互に積層し
    てなる直方体形状の素体と、該素体の両端部において該
    内部電極層に形成された内部電極を交互に並列に接続し
    ている一対の外部電極とからなる積層コンデンサであっ
    て、 同一の外部電極に接続された内部電極はそれぞれ異なる
    長さ又は幅に設定されていることを特徴とする積層コン
    デンサ。
    1. A rectangular parallelepiped element body in which dielectric layers and internal electrode layers are alternately laminated, and internal electrodes formed on the internal electrode layers at both ends of the element body are alternately connected in parallel. A multilayer capacitor comprising a pair of external electrodes, wherein the internal electrodes connected to the same external electrode are set to have different lengths or widths.
  2. 【請求項2】 一方の外部電極に接続された最外層の内
    部電極は、該内部電極の先端部が、前記素体の上下面に
    形成された他方の外部電極に対向しない長さに設定され
    ていることを特徴とする請求項1記載の積層コンデン
    サ。
    2. The innermost electrode of the outermost layer connected to one of the outer electrodes is set to a length such that the tip of the inner electrode does not face the other outer electrode formed on the upper and lower surfaces of the element body. The multilayer capacitor according to claim 1, wherein
JP8072875A 1996-03-27 1996-03-27 Multilayer capacitor Granted JPH09266130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8072875A JPH09266130A (en) 1996-03-27 1996-03-27 Multilayer capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8072875A JPH09266130A (en) 1996-03-27 1996-03-27 Multilayer capacitor

Publications (1)

Publication Number Publication Date
JPH09266130A true JPH09266130A (en) 1997-10-07

Family

ID=13501954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8072875A Granted JPH09266130A (en) 1996-03-27 1996-03-27 Multilayer capacitor

Country Status (1)

Country Link
JP (1) JPH09266130A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001110673A (en) * 1999-10-14 2001-04-20 Taiyo Yuden Co Ltd Lamianted ceramic capacitor and method of manufacturing the same
JP2004509451A (en) * 2000-04-28 2004-03-25 エクストゥーワイ、アテニュエイタズ、エル、エル、シー A predetermined symmetrically balanced mixture having a complementary pair of parts with a shielding electrode and a shielded electrode and a symmetrically balanced complementary energy part other predetermined element parts for conditioning;
JP2008205073A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Ceramic capacitor
US7715171B2 (en) 2005-08-19 2010-05-11 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
US8026777B2 (en) * 2006-03-07 2011-09-27 X2Y Attenuators, Llc Energy conditioner structures
JP2013161931A (en) * 2012-02-03 2013-08-19 Taiyo Yuden Co Ltd Porous capacitor, and method of manufacturing the same
CN103903854A (en) * 2012-12-27 2014-07-02 三星电机株式会社 Multilayer ceramic capacitor and board for mounting the same
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
CN104620341A (en) * 2012-06-19 2015-05-13 太阳诱电株式会社 Laminated ceramic capacitor
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225507A (en) * 1983-06-06 1984-12-18 Tohoku Metal Ind Ltd Laminated porcelain capacitor
JPS61162037U (en) * 1985-03-28 1986-10-07
JPH0669062A (en) * 1992-08-12 1994-03-11 Murata Mfg Co Ltd Laminated capacitor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59225507A (en) * 1983-06-06 1984-12-18 Tohoku Metal Ind Ltd Laminated porcelain capacitor
JPS61162037U (en) * 1985-03-28 1986-10-07
JPH0669062A (en) * 1992-08-12 1994-03-11 Murata Mfg Co Ltd Laminated capacitor

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373592B2 (en) 1997-04-08 2016-06-21 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
JP2001110673A (en) * 1999-10-14 2001-04-20 Taiyo Yuden Co Ltd Lamianted ceramic capacitor and method of manufacturing the same
JP2004509451A (en) * 2000-04-28 2004-03-25 エクストゥーワイ、アテニュエイタズ、エル、エル、シー A predetermined symmetrically balanced mixture having a complementary pair of parts with a shielding electrode and a shielded electrode and a symmetrically balanced complementary energy part other predetermined element parts for conditioning;
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
US7715171B2 (en) 2005-08-19 2010-05-11 Murata Manufacturing Co., Ltd. Multilayer ceramic capacitor
US8026777B2 (en) * 2006-03-07 2011-09-27 X2Y Attenuators, Llc Energy conditioner structures
JP2008205073A (en) * 2007-02-19 2008-09-04 Matsushita Electric Ind Co Ltd Ceramic capacitor
US9082548B2 (en) * 2012-02-03 2015-07-14 Taiyo Yuden Co., Ltd. Porous capacitors and method for manufacturing the same
JP2013161931A (en) * 2012-02-03 2013-08-19 Taiyo Yuden Co Ltd Porous capacitor, and method of manufacturing the same
CN104620341A (en) * 2012-06-19 2015-05-13 太阳诱电株式会社 Laminated ceramic capacitor
CN103903854A (en) * 2012-12-27 2014-07-02 三星电机株式会社 Multilayer ceramic capacitor and board for mounting the same
US20140185186A1 (en) * 2012-12-27 2014-07-03 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board for mounting the same
US9208950B2 (en) * 2012-12-27 2015-12-08 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and board for mounting the same

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