JP2005108890A - Laminated ceramic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor which is made uniform enough in inner density and capable of effectively restraining voids from occurring at thermocompression bonding or delamination from occurring after a baking process is carried out. <P>SOLUTION: The laminated ceramic capacitor 10 has a configuration wherein a dielectric layer is located between a first internal electrode layer 2 and a second internal electrode layer 3, and buffer conductor layers 4 and 5 which are held coming into no contact with at least either of the internal electrode layers are provided closer to the external electrodes 8 and 9 than the opposed regions each located between the internal electrodes 2 and 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer ceramic capacitor.

  As shown in FIG. 3, a conventional multilayer ceramic capacitor 10 has a plurality of rectangular dielectric layers on which conductive internal electrode layers 2 and 3 are formed so that the internal electrode layers 2 and 3 take out portions are opposed to each other. The internal electrode layers 2 and 3 facing each other are provided with external electrode terminals 8 and 9 on the laminated ceramic element laminated and integrated with each other.

  However, this conventional multilayer ceramic capacitor 10 includes a region in which the internal electrode layers 2 and 3 face each other over all layers in a thickness in the lamination direction before thermocompression bonding, and a region from the facing region to the external electrode terminals 8 and 9. Since the number of existing internal electrode layers 2 and 3 is different, it is difficult to avoid density unevenness in the stacking direction when the laminated body is thermocompression-bonded, and to prevent delamination after firing.

In this regard, a rectangular dielectric layer having conductive internal electrode layers 2 and 3 formed thereon is formed on a capacitor forming portion 12 formed by alternately laminating a plurality of internal electrode layers 2 and 3 so that the extraction portions face each other. On the other hand, in a multilayer ceramic capacitor 10 in which rectangular dielectric layers having nothing deposited on both main surfaces thereof are laminated and integrated as margin portions 11 and 13, dielectrics constituting the margin portions 11 and 13 are integrated. Disclosed is a technique for disposing the buffer conductor layers 4 and 5 extending from the end portion where the external electrode terminals 8 and 9 are formed between the body layers to the central portion so that the density inside the capacitor is substantially uniform as a whole. Yes. (See Patent Document 1)
JP-A-5-234805

  However, in the multilayer ceramic capacitor 10 described in Patent Document 1, although the internal density can be made substantially uniform as a whole capacitor, the density unevenness still occurs in the unit of the pair of internal electrode layers 2 and 3 forming the capacitance. In addition, after the margin portions 11 and 13 having the laminated cushioning materials 4 and 5 disposed on the upper and lower main surfaces of the capacity forming portion 12 are stacked, holes are formed between the two when thermocompression bonding is performed. Therefore, there has been a problem that delamination and cracks still occur after the laminate is fired.

  The present invention has been devised in view of the problems as described above, and its purpose is to make the internal density of the capacitor sufficiently uniform and to effectively generate voids during thermocompression bonding and delamination after firing. It is an object of the present invention to provide a monolithic ceramic capacitor that can be suppressed.

The multilayer ceramic capacitor of the present invention is formed by laminating a large number of rectangular dielectric layers to form a multilayer body, and between the first and second internal electrode layers and the second dielectric layer adjacent to each other vertically inside the multilayer body. The internal electrode layers are alternately arranged in the laminating direction of the dielectric layers so that both internal electrode layers are partially opposed to each other, and one end surface of the laminated body is connected to the first internal electrode layer. A first external electrode terminal is formed on the other end surface of the laminate, and a second external electrode terminal connected to the second internal electrode layer is formed, and between the first internal electrode layer and the second internal electrode layer Inside the dielectric layer located at
A buffer conductor layer held in a non-contact manner with at least one of the internal electrode layers is disposed closer to the external electrode terminal than the opposing region of both internal electrode layers.

  In the multilayer ceramic capacitor of the present invention, the buffer conductor layer disposed in the region between the facing region and the second external electrode terminal is not in contact with the first internal electrode layer, and the facing region and the first external electrode terminal are not in contact with each other. The buffer conductor layer disposed in the region between the two is maintained in a non-contact manner with the second internal electrode layer.

  Furthermore, the multilayer ceramic capacitor of the present invention is characterized in that the thickness of the buffer conductor layer is substantially the same as that of the internal electrode layer.

  According to the present invention, a multilayer body is formed by laminating a large number of rectangular dielectric layers, and the first internal electrode layer and the second internal electrode are disposed between the dielectric layers adjacent to each other vertically in the multilayer body. The first external electrode connected to the first internal electrode layer on one end surface of the multilayer body, and alternately arranged in the stacking direction of the dielectric layers so that both internal electrode layers are partially opposed to each other The electrode terminal is formed between the first internal electrode layer and the second internal electrode layer, and the second external electrode terminal connected to the second internal electrode layer is formed on the other end surface of the laminate. A multilayer ceramic capacitor is configured by disposing a buffer conductor layer held in non-contact with at least one of the internal electrode layers inside the dielectric layer, on the external electrode terminal side of the opposing region of both internal electrode layers As a result, the capacitance is not limited to the entire multilayer ceramic capacitor. Since it is possible to suppress the occurrence of density unevenness even in the unit of the pair of internal electrode layers to be formed, it is possible to prevent the generation of vacancies between the dielectric layers during thermocompression bonding and reduce the occurrence of delamination after firing. It becomes possible.

  According to the invention, the buffer conductor layer disposed in the region between the counter region and the second external electrode terminal is in non-contact with the first internal electrode layer, and between the counter region and the first external electrode terminal. Since the buffer conductor layer disposed in the region is configured to be kept out of contact with the second internal electrode layer, the internal electrode layer and the buffer conductor layer are not short-circuited, and the capacitance of the multilayer ceramic capacitor can be stabilized. It is possible to maintain the above-mentioned effects more effectively.

  Furthermore, according to the present invention, since the buffer conductor layer is configured to have substantially the same thickness as the internal electrode layer, the density inside the capacitor is substantially uniform. It is possible to prevent the generation of pores and more effectively prevent the occurrence of delamination after firing.

  Hereinafter, the multilayer ceramic capacitor of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor of the present invention, and FIG. 2 is an exploded perspective view of the capacitor body of the multilayer ceramic capacitor of the present invention. In addition, the same part as a prior art attaches | subjects and demonstrates the same code | symbol.

  As shown in FIG. 1, the multilayer ceramic capacitor 10 of the present invention is configured by forming a first external electrode terminal 8 and a second external electrode terminal 9 at both ends in the longitudinal direction of the capacitor body 1.

  The capacitor body 1 includes an upper margin portion 11, a capacitance forming portion 12, and a lower margin portion 13. The upper margin portion 11 includes dielectric layers 11a to 11n, and the lower margin portion 13 includes dielectric layers. It is comprised from the body layers 13a-13n.

  Here, it is desirable to use the same dielectric material for each dielectric layer so that the sintering behavior is the same, for example, a dielectric having a perovskite crystal structure containing barium titanate, strontium titanate, and lead. Consists of body materials.

  Further, the first internal electrode layers 2 and the second internal electrode layers 3 are alternately arranged between the dielectric layers 11n, 12a, 12b,. For example, the rectangular first internal electrode layer 2 is disposed on the rectangular dielectric layers 12b, 12d..., And the second internal electrode layer 3 is disposed on the rectangular dielectric layers 12a, 12c. ing. On the dielectric layer 12b, a first end margin portion 2E is formed as a region up to one end face of the capacitor body 1 on the tip end side of the first internal electrode layer 2, and similarly, on the dielectric layer 12a. A second end margin portion 3E is formed on the tip end side of the second internal electrode layer 3 as a region up to the other end surface of the capacitor body 1. Here, the 1st internal electrode layer 2 and the 2nd internal electrode layer 3 are comprised from the metal conductor film which has Pd, Cu, Ni etc. as a main component, for example.

  In the capacitance forming portion 12, dielectric layers 14a, 14b,... 14n are further arranged between a pair of adjacent first internal electrode layers 2 and second internal electrode layers 3, and these dielectric layers 14a. Buffer conductor layers 4 and 5 are disposed at positions corresponding to the first end margin portion 2E and the second end margin portion 3E at both ends of each element region between ˜14n, respectively. It is formed in a non-contact state with the layer 3. As a result, the occurrence of density unevenness can be reduced not only in the multilayer ceramic capacitor 10 as a whole but also in the unit of the pair of internal electrode layers forming the capacitance, so that voids are generated between the dielectric layers during thermocompression bonding. And the occurrence of delamination after firing can be reduced.

  The material of the buffer conductor layers 4 and 5 may be any material as long as it is conductive. From the viewpoint of making the internal density of the capacitor uniform, it is preferable to use the same material as that of the internal electrode layers 2 and 3 described above.

  The thickness of the buffer conductor layers 4 and 5 is preferably substantially the same as that of the internal electrode layers 2 and 3, specifically within a range of ± 15% with respect to the thickness of the internal electrode layers 2 and 3. . As a result, the density inside the multilayer ceramic capacitor 10 becomes substantially uniform, so that voids are prevented from being generated between the dielectric layers during thermocompression bonding, and delamination is more effectively prevented after firing. It becomes possible.

  A first external electrode terminal 8 and a second external electrode terminal 9 are attached and formed on a pair of end portions in the longitudinal direction of the capacitor body 1. The first external electrode terminal 8 and the second external electrode terminal 9 are composed of a thick film base conductor containing a metal mainly composed of Ag or Cu, and a surface plating layer such as a Ni plating layer or a solder plating layer. Are formed over both end portions, that is, the end surface of the end portion, the upper and lower surfaces, and both side surfaces.

  The first internal electrode layer 2 described above extends to one end face (left side in the drawing) in the longitudinal direction of the dielectric layers 12 a, 12 c..., Thereby being connected to the first external electrode terminal 8. Yes. In addition, the second internal electrode layer 3 extends to the end face in the other longitudinal direction (right side in the drawing) of the dielectric layers 12b, 12d, etc., and is thereby connected to the second external electrode terminal 9. Yes. Therefore, on the dielectric layer 12a, the first end margin portion 2E is formed on the tip end side of the first internal electrode layer 2 so as not to be short-circuited to the second external electrode terminal 9, and similarly, the dielectric layer A second end margin portion 3E is formed on the front end portion of the second internal electrode layer 3 so as not to be short-circuited to the first external electrode terminal 8 on 12b.

  Next, a method for manufacturing the multilayer ceramic capacitor of the present invention will be described. The buffer conductor layers 4 and 5 will be described using a multilayer ceramic capacitor 10 shown in FIG. 1 formed of the same material as the internal electrode layers 2 and 3.

  First, the dielectric green sheet used as the dielectric layers 11a-14n which can extract a some element is produced.

  Next, the upper margin portion 11 of each element is formed by a plurality of dielectric green sheets that do not form internal electrode layers that become the dielectric layers 11a to 11n.

  Further, among the dielectric green sheets constituting the capacitance forming portion 12 of each element, the first internal electrode layer is located near one end of each element region of the dielectric green sheet to be the dielectric layers 12a, 12c. 2 is formed by printing Pd-based (Pd alone or Pd alloy such as Ag—Pd) or Ni-based conductive paste. Similarly, a conductor film to be the second internal electrode layer 3 is formed near the other end of each element region of the dielectric green sheet to be the dielectric layers 12b, 12d.

  .. Corresponding to the first end margin portion 2E and the second end margin portion 3E at both end portions of each element region of the dielectric green sheet constituting the dielectric layers 14a, 14c... Constituting the capacitance forming portion 12. At the position, a conductor film to be the buffer conductor layers 4 and 5 is formed by printing Pd-based (Pd alone or Pd alloy such as Ag—Pd) or Ni-based conductive paste.

  Next, the lower margin portion 13 of each element is composed of a plurality of dielectric green sheets that do not form internal electrode layers that become the dielectric layers 13a to 13n.

  Thereafter, the above-mentioned dielectric green sheets to be the dielectric layers 11a to 14n are sequentially laminated, and thermocompression bonding is performed by applying a predetermined pressure. The laminated dielectric green sheets are cut according to the shape of each element and fired in a predetermined atmosphere. As a result, the capacitor body 1 including the upper margin portion 11, the capacitance forming portion 12, and the lower margin portion 13 is formed.

  When the characteristics of the capacitor body 1 of the present invention formed as described above were examined, the configuration of each material, thickness, total number, and the like was the same, and the arrangement positions of the buffer conductor layers 4 and 5 are as shown in FIG. In the capacitor made by changing to the capacitor body 1 of the present invention, the voids generated at a probability of 20% at the time of thermocompression bonding and the delamination between the respective layers generated by 0.4% after the sintering are completely generated. I found that there was no. In addition, in the capacitor body 1 of the present invention, the occurrence of density unevenness can be suppressed not only in the capacitor body 1 as a whole but also in the units of the pair of internal electrode layers 2 and 3 that form a capacitance. There was no short circuit failure caused by stretching and thinning locally.

  Next, the end including the pair of longitudinal end faces of the sintered capacitor body 1 is made of a metal containing Ag and Cu, a paste containing glass frit as a solid component, a metal containing Ag and Cu, and a resin containing a resin component. The thick conductor film is formed by dipping in the paste and baking or thermosetting the attached conductor film. Then, a surface plating layer such as Ni plating or solder plating is formed on the thick base conductor film.

  In the above-described multilayer ceramic capacitor 10, as shown in FIG. 2, the dielectric layers 14a to 14n of the capacitance forming portion 12 have the buffer conductor layer 4 at a position corresponding to the first end margin portion 2E on the other end side. The buffer conductor layer 5 is present at a position corresponding to the second end margin portion 3E on the one end side.

  Accordingly, in the step of thermocompression bonding the dielectric green sheet, a uniform pressure is applied to the entire capacitor body 1, and uneven density of the capacitor body 1 can be effectively prevented. Thereby, peeling or the like hardly occurs between the dielectric layers 11a to 14n at the time of cutting or firing.

  Here, the number of the buffer conductor layers 4 disposed at the other end of the dielectric layers 14a to 14n is substantially equal to the number of the first end margin portions 2E of the first internal electrode layer 2 and at one end. The density distribution in the laminating process can be made constant by matching the number of arranged buffer conductor layers 5 to the number of second end margin portions 3E of the second internal electrode layer 3 substantially.

  The present invention is not limited to the above-described embodiment. For example, in the above-described embodiment, a dielectric layer is further provided between a pair of adjacent first internal electrode layer 2 and second internal electrode layer 3. 14a to 14n are arranged, and buffer conductor layers 4 and 5 are formed at both ends of each element region between the dielectric layers 14a to 14n. Instead, the dielectric layers 14a to 14n are arranged. Without directly stacking the buffer conductor layer 5 at a position corresponding to the second end margin portion 3E of the rectangular first internal electrode layer 2 disposed on the rectangular dielectric layers 12b, 12d. The buffer conductor layer 4 is formed at a position corresponding to the first end margin portion 2E on the rectangular dielectric layers 12a, 12c... And the second internal electrode layer 3 is formed directly on the buffer conductor layer 4. It is good also as composition to do. Even in this case, the same effect as that of the above-described embodiment can be obtained, and at the same time, since the dielectric layers 14a to 14n are not provided, the capacitor 1 can be formed relatively thin.

It is sectional drawing of the multilayer ceramic capacitor of this invention. It is a disassembled perspective view of the capacitor | condenser main body of the multilayer ceramic capacitor of this invention. It is sectional drawing of the conventional multilayer ceramic capacitor. It is sectional drawing of the conventional multilayer ceramic capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Capacitor body 2 ... 1st internal electrode layer 3 ... 2nd internal electrode layer 2E ... 1st end margin part 3E ... 2nd end margin part 4, 5 ... Buffer conductor layer 10 ... Multilayer ceramic capacitor 11 ... Upper margin part 12 ... Capacitance forming part 13 ... Lower margin part

Claims (3)

A large number of rectangular dielectric layers are stacked to form a stacked body, and the first internal electrode layer and the second internal electrode layer are connected to the internal electrodes between the adjacent dielectric layers inside the stacked body. The first external electrode terminals connected to the first internal electrode layer on one end face of the multilayer body are alternately arranged in the stacking direction of the dielectric layers so that the layers partially face each other. In a multilayer ceramic capacitor formed by forming a second external electrode terminal connected to the second internal electrode layer on the other end surface of the body,
In the dielectric layer located between the first internal electrode layer and the second internal electrode layer, at least one internal electrode layer is not in contact with the external electrode terminal side of the opposing region of the internal electrode layers A multilayer ceramic capacitor, characterized in that a buffer conductor layer held on the substrate is disposed. The buffer conductor layer disposed in the region between the opposing region and the second external electrode terminal is in contact with the first internal electrode layer, and the buffer conductor disposed in the region between the counter region and the first external electrode terminal. The multilayer ceramic capacitor according to claim 1, wherein the layer is kept out of contact with the second internal electrode layer. 3. The multilayer ceramic capacitor according to claim 1, wherein a thickness of the buffer conductor layer is substantially the same as that of the internal electrode layer. 4.

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