JP2013183028A - Electronic component built-in wiring board, chip capacitor, and manufacturing method of electronic component built-in wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit cracks in an electronic component incorporated in an electronic component built-in wiring board.SOLUTION: An electronic component built-in wiring board includes: a substrate 100; a conductor layer 302 and an insulation layer 102 that are formed on a second surface F12 of the substrate 100; an electronic component 200a disposed in an opening R100 that opens on the second surface F12; and a via conductor 322b connected with an electrode 220 of the electronic component 200a. An opening is formed on a third surface or a fourth surface of the body 201 and at least a part of the electrode 220 of the electronic component 200a is formed in the opening formed on the third surface or the fourth surface.

Description

  The present invention relates to an electronic component built-in wiring board, a chip capacitor, and a method for manufacturing an electronic component built-in wiring board.

  Patent Document 1 discloses a wiring board with a built-in capacitor.

JP 2001-345560 A

  In the electronic component built-in wiring board described in Patent Document 1, an electronic component (capacitor) is accommodated in an opening (accommodating portion) formed in the substrate. The main surface of the main part of the electronic component is flat on both surfaces (front and back surfaces), and a plurality of external electrodes are formed on the flat main surface. For this reason, a step is formed at the boundary between the main body portion of the electronic component and the external electrode formed on the main body portion. When there is such a step, for example, when the electronic component is accommodated in the opening of the substrate or an insulating layer is formed on both sides of the electronic component, the electronic component is likely to crack from the stepped portion. Become. Such cracks are more likely to occur as the electronic component becomes thinner.

  The present invention has been made in view of such circumstances, and an object thereof is to suppress cracks in an electronic component built in an electronic component built-in wiring board. Another object of the present invention is to make the wiring board thinner (thinner) while maintaining high reliability of the electrical characteristics of the electronic components incorporated in the wiring board.

The electronic component built-in wiring board according to the present invention,
A substrate having a first surface and a second surface opposite to the first surface, and an opening opening at least in the second surface;
A main body having a third surface and a fourth surface opposite to the third surface, and an external electrode formed on the main body, so that the third surface is in the same direction as the first surface, An electronic component disposed in the opening formed in the substrate;
An insulating layer formed on the second surface of the substrate and on the electronic component;
A via conductor formed in the insulating layer and connected to the external electrode;
An electronic component built-in wiring board having
An opening is formed in the third surface or the fourth surface of the main body,
At least a part of the external electrode is formed in the opening formed in the third surface or the fourth surface.

  It is preferable that the depth of the opening formed in the third surface or the fourth surface is substantially the same as the thickness of at least a part of the external electrode formed in the opening.

  The difference between the depth of the opening formed in the third surface or the fourth surface and the thickness of at least a part of the external electrode formed in the opening is preferably 5 μm or less.

  It is preferable that the depth of the opening formed in the third surface or the fourth surface is larger than the thickness of at least a part of the external electrode formed in the opening.

  It is preferable that the opening formed in the third surface or the fourth surface forms a step in the third surface or the fourth surface of the main body.

  It is preferable that the depth of the opening formed in the third surface or the fourth surface is substantially constant.

  It is preferable that the opening formed in the third surface or the fourth surface is formed only in a portion where the external electrode is formed.

  A first opening is formed in the third surface of the main body, a second opening is formed in the fourth surface of the main body, and the first opening and the second opening are formed. Preferably, each of the external electrode portions is formed.

  The main body has a first side and a second side opposite to the first side, and the electronic component is integrated with the first opening, on the first side of the main body, and over the second opening. It is preferable to have the 1st external electrode formed in this.

  The first opening and the third opening are formed on the third surface of the main body, and the second opening and the fourth opening are formed on the fourth surface of the main body. It is preferable that the electronic component has a second external electrode integrally formed over the third opening, the second side surface of the main body, and the fourth opening. .

  It is preferable that a first via conductor connected to the first external electrode and a second via conductor connected to the second external electrode are formed in the insulating layer.

  An insulating layer formed on the first surface of the substrate and on the electronic component; and the opening formed in the substrate penetrates from the first surface to the second surface. preferable.

  The insulating layer is preferably made of a resin containing a core material.

  The electronic component is preferably a multilayer ceramic capacitor.

  It is preferable that a semiconductor element mounting pad is formed on the insulating layer located at the outermost layer, and the via conductor is electrically connected to the semiconductor element mounting pad.

The chip capacitor according to the present invention is
A chip capacitor having a main body having a first main surface and a second main surface opposite to the first main surface, and an external electrode formed on the main body,
An opening is formed in the first main surface or the second main surface of the main body,
At least a part of the external electrode is formed in the opening formed in the first main surface or the second main surface.

  A first opening is formed in the first main surface of the main body, a second opening is formed in the second main surface of the main body, and the main body includes the first side surface and the first side surface. It is preferable to have a second side surface on the opposite side, and to have a first external electrode integrally formed over the first opening, the first side surface of the main body, and the second opening.

  The first opening and the third opening are formed on the first main surface of the main body, and the second opening and the fourth opening are formed on the second main surface of the main body. It is preferable that the first external electrode is formed integrally with the third opening, the second side surface of the main body, and the fourth opening.

The manufacturing method of the electronic component built-in wiring board according to the present invention,
Providing a substrate having a first side and a second side opposite thereto;
Forming an opening in the substrate at least in the second surface;
Providing an electronic component having a main body portion having a third surface and a fourth surface on the opposite side, and an external electrode formed on the main body portion;
Disposing the electronic component in the opening formed in the substrate so that the third surface is in the same direction as the first surface;
Forming an insulating layer on the second surface of the substrate and on the electronic component;
Forming a via conductor connected to the external electrode in the insulating layer;
A method of manufacturing an electronic component built-in wiring board including:
In the preparation of the electronic component, an opening is formed in the third surface or the fourth surface of the main body, and at least a part of the external electrode is formed on the third surface or the fourth surface. Form in the opening.

  Forming an insulating layer on the first surface of the substrate and on the electronic component, wherein the opening formed in the substrate penetrates from the first surface to the second surface; preferable.

  Prior to the placement of the electronic component, the opening on the second surface side of the opening formed in the substrate is closed with a support material, and in the placement of the electronic component, the opening formed in the substrate From the opening on the first surface side of the part, the electronic component is placed on the support material in the opening, the electronic component is placed in the opening and the support material is removed, and then the substrate It is preferable that the insulating layer is formed on the second surface and the electronic component.

  In the formation of the insulating layer, it is preferable that the insulating layer is bonded onto the second surface of the substrate and the electronic component by pressing an insulating layer made of a resin including a core material.

  In the preparation of the electronic component, the main body portion has a first side surface and a second side surface opposite to the first side surface, and a first opening portion and a third opening portion are formed on the third surface of the main body portion. A second opening and a fourth opening are formed on the fourth surface of the main body, and the first opening, the first side surface of the main body, and the second opening are formed. A first external electrode integrally formed over a portion, and a second external electrode integrally formed over the third opening, the second side surface of the main body, and the fourth opening. It is preferable to prepare an electronic component having the same.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to suppress the crack of the electronic component incorporated in the electronic component built-in wiring board. Further, according to the present invention, in addition to or instead of this effect, the wiring board is made thin (thinned) while maintaining high reliability with respect to the electrical characteristics of the electronic components incorporated in the wiring board. May be effective.

It is sectional drawing of the electronic component built-in wiring board which concerns on embodiment of this invention. It is the elements on larger scale of FIG. It is a figure which shows the 1st cross-sectional shape of the chip capacitor incorporated in the wiring board with a built-in electronic component which concerns on embodiment of this invention. It is a figure which shows the 2nd cross-sectional shape of the chip capacitor incorporated in the electronic component built-in wiring board which concerns on embodiment of this invention. It is the elements on larger scale of FIG. 3A. It is a top view of the main-body part of the chip capacitor built in the electronic component built-in wiring board concerning the embodiment of the present invention. It is sectional drawing of the main-body part of the chip capacitor incorporated in the wiring board with a built-in electronic component which concerns on embodiment of this invention. It is a top view of the chip capacitor built in the electronic component built-in wiring board concerning the embodiment of the present invention. It is a figure which shows the electrode formed in each side surface of the chip capacitor incorporated in the electronic component built-in wiring board which concerns on embodiment of this invention. It is a top view which shows the state by which the electronic component is arrange | positioned at the cavity. It is a figure which shows a mode that a crack arises in the electronic component by which the opening part is not formed in the main-body part. It is a flowchart which shows the manufacturing method of the chip capacitor which concerns on embodiment of this invention. FIG. 10 is a diagram for explaining a step of laminating a dielectric layer and a conductor layer in the manufacturing method shown in FIG. 9. It is a figure which shows the relationship between the dielectric layer laminated | stacked by the process of FIG. 10, and the conductor pattern of a 1st conductor layer. It is a figure which shows the relationship between the dielectric layer laminated | stacked at the process of FIG. 10, and the conductor pattern of a 2nd conductor layer. It is a figure which shows the dielectric layer which has a groove | channel laminated | stacked outermost at the process of FIG. It is a figure for demonstrating the process of pressing the dielectric layer and conductor layer which were laminated | stacked at the process of FIG. It is a top view for demonstrating the process of cutting the dielectric layer and conductor layer which were pressed by the process of FIG. It is sectional drawing for demonstrating the process of cutting the dielectric layer and conductor layer which were pressed by the process of FIG. In the manufacturing method shown in FIG. 9, it is a figure for demonstrating the process of forming a 1st electrode layer by plating in the main-body part of the chip capacitor cut out by the process of FIG.15 and FIG.16. It is a figure which shows the main-body part of the chip capacitor in which the 1st electrode layer was formed by the process of FIG. 17A. It is a figure for demonstrating the process of forming a 2nd electrode layer by the electroplating which uses the 1st electrode layer formed at the process of FIG. 17A as a seed layer in the manufacturing method shown in FIG. It is a figure which shows the main-body part of the chip capacitor by which the 2nd electrode layer was formed on the 1st electrode layer by the process of FIG. 18A. It is a flowchart which shows the manufacturing method of the electronic component built-in wiring board which concerns on embodiment of this invention. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 1st process of forming a conductor layer on a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 2nd process of forming a conductor layer on a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 3rd process of forming a conductor layer on a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 4th process of forming a conductor layer on a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the process of roughening the conductor layer on a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 1st method for forming an opening part in a board | substrate. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 2nd method for forming an opening part in a board | substrate. FIG. 20 is a diagram showing openings formed in a substrate in the manufacturing method shown in FIG. 19. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the process of attaching the board | substrate with which the opening part (cavity) was formed to a carrier. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the process of arrange | positioning an electronic component in a cavity. In the manufacturing method shown in FIG. 19, it is a figure which shows the state by which the electronic component was arrange | positioned in the cavity. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 1st process of filling the clearance gap between the board | substrate and electronic component in a cavity. It is a figure for demonstrating the 2nd process after the process of FIG. It is a figure for demonstrating the 3rd process after the process of FIG. It is a figure for demonstrating the process of removing a carrier from a board | substrate in the manufacturing method shown in FIG. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the 1st process of forming a lower layer buildup part. FIG. 32 is a diagram for explaining a second step after the step of FIG. 31. It is a figure for demonstrating the 3rd process after the process of FIG. It is a figure for demonstrating the 4th process after the process of FIG. In the manufacturing method shown in FIG. 19, it is a figure for demonstrating the process of forming an upper layer buildup part. In other embodiment of this invention, it is a figure which shows the example whose depth of the opening part formed in the main surface of an electronic component is larger than the thickness of the electrode formed in the opening part. In other embodiment of this invention, it is a figure which shows the example whose depth of the opening part formed in the main surface of an electronic component is smaller than the thickness of the electrode formed in the opening part. In other embodiment of this invention, it is a figure which shows the example from which the depth of the opening part formed in the main surface of an electronic component changes stepwise. In other embodiment of this invention, it is a figure which shows the example from which the depth of the opening part formed in the main surface of an electronic component changes continuously. In other embodiment of this invention, it is a figure which shows the example by which the opening part is formed in the part in which the electrode is not formed in the main surface of the main-body part of an electronic component. In other embodiment of this invention, it is a figure which shows the 1st example by which the opening part is formed only in one main surface of the main-body part of an electronic component. In other embodiment of this invention, it is a figure which shows the 2nd example by which the opening part is formed only in one main surface of the main-body part of an electronic component. In other embodiment of this invention, it is a figure which shows the electronic component built-in wiring board by which the electronic component is arrange | positioned at the non-penetrating opening part. In other embodiment of this invention, it is a figure which shows the example which arrange | positions one electronic component per one cavity (opening part). In other embodiment of this invention, it is a figure which shows the example in which the insulating layer which comprises a lower layer buildup part contains a core material, and the insulating layer which comprises an upper layer buildup part does not contain a core material. In other embodiment of this invention, it is a figure which shows the electronic component built-in wiring board which has a double-sided via structure. In other embodiment of this invention, it is a figure which shows the electronic component built-in wiring board which has a board | substrate which incorporates a metal plate. It is a figure for demonstrating the 1st process of manufacturing the board | substrate used for the electronic component built-in wiring board shown in FIG. It is a figure for demonstrating the 2nd process after the process of FIG. 45A.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the wiring boards (or the thickness direction of the wiring boards) corresponding to the normal direction of the main surface (front and back surfaces) of the wiring boards. On the other hand, arrows X1 and X2 and Y1 and Y2 respectively indicate directions orthogonal to the stacking direction (or sides of each layer). The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane. In the stacking direction, the side closer to the core is called the lower layer, and the side far from the core is called the upper layer.

  The conductor layer is a layer composed of one or more conductor patterns. The conductor layer may include a conductor pattern that constitutes an electric circuit, for example, a wiring (including a ground), a pad, a land, or the like, or a planar conductor pattern that does not constitute an electric circuit.

  The openings include notches and cuts in addition to holes and grooves. The hole is not limited to a through hole, and includes a non-through hole. The holes include via holes and through holes. Hereinafter, a conductor formed in the via hole (wall surface or bottom surface) is referred to as a via conductor, and a conductor formed in the through hole (wall surface) is referred to as a through hole conductor.

  Preparation includes purchasing and using finished products in addition to purchasing materials and parts and making them themselves.

  In order for a component (or electrode, etc.) to be “arranged (or formed) in the opening”, the entire component is completely accommodated in the opening, and only a part of the component is opened. It is also included to be arranged in the section.

  In addition to wet plating such as electrolytic plating, plating includes dry plating such as PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described in detail with reference to the drawings.

  As shown in FIGS. 1 and 2 (partially enlarged view of FIG. 1), the wiring board 10 (electronic component built-in wiring board) according to the present embodiment is insulated from the substrate 100 (insulating substrate), the through-hole conductor 300b, and the insulating material. Layers 101, 102, 103, 104 (interlayer insulating layers), conductor layers 301, 302, 110, 120, 130, 140, electronic components 200a and 200b, via conductors 313b, 321b, 322b, 323b, 333b, 343b and solder resists 11 and 12. In addition, the wiring board 10 of this embodiment is a rigid wiring board of a rectangular plate shape, for example. However, the present invention is not limited to this, and the wiring board 10 may have a shape other than a rectangular plate shape, or may be a flexible wiring board.

  In the wiring board 10 of the present embodiment, the substrate 100, the through-hole conductor 300b, the conductor layers 301 and 302, and the electronic components 200a and 200b correspond to the core portion. Hereinafter, one of the front and back surfaces (two main surfaces) of the substrate 100 is referred to as a first surface F11, and the other is referred to as a second surface F12. Of the front and back surfaces (two main surfaces) of the electronic components 200a and 200b, a surface facing the same direction as the first surface F11 is referred to as a first main surface F3, and the other is referred to as a second main surface F4.

  In the present embodiment, the substrate 100 is a core substrate of the wiring board 10. An opening R100 (FIG. 2) is formed in the substrate 100. The opening R100 opens in the first surface F11 and the second surface F12, respectively. Each of the electronic components 200a and 200b is housed in the opening R100, and is built in the core portion of the wiring board 10.

  The conductor layer, the interlayer insulating layer, and the via conductor laminated on the core part correspond to the build-up part. Hereinafter, the buildup part located in the lowest layer is referred to as a lower layer buildup part, and the buildup part higher than the lower layer buildup part is referred to as an upper layer buildup part. In the present embodiment, the lower layer build-up portion includes insulating layers 101 and 102, conductor layers 110 and 120, and via conductors 313b, 321b, 322b, and 323b. In addition, the upper layer buildup portion includes insulating layers 103 and 104, conductor layers 130 and 140, and via conductors 333b and 343b.

  Through hole 300a is formed in substrate 100 (core substrate), and through hole conductor 300b is formed by filling conductor (for example, copper plating) in through hole 300a. The shape of the through-hole conductor 300b is, for example, an hourglass shape (a drum shape). That is, the through-hole conductor 300b has a constricted portion 300c, and the width of the through-hole conductor 300b gradually decreases from the first surface F11 toward the constricted portion 300c, and approaches the constricted portion 300c from the second surface F12. It gradually becomes smaller as it goes. However, the shape is not limited to this, and the shape of the through-hole conductor 300b is arbitrary, and may be, for example, a substantially cylindrical shape.

  A conductor layer 301 is formed on the first surface F11 of the substrate 100, and a conductor layer 302 is formed on the second surface F12 of the substrate 100. Each of the conductor layers 301 and 302 includes a land of the through-hole conductor 300b. The conductor layer 301 and the conductor layer 302 are electrically connected to each other through the through-hole conductor 300b. Each of the conductor layers 301 and 302 is electrically connected to a power source or a ground, for example.

  The substrate 100 has an opening R100 (for example, a hole) penetrating from the first surface F11 to the second surface F12 of the substrate 100. By forming the opening R100 in the substrate 100, the core portion of the wiring board 10 extends from the upper surface of the conductor layer 301 formed on one side of the substrate 100 to the upper surface of the conductor layer 302 formed on the other side. A cavity R10 (accommodating portion) having a thickness is formed. In the present embodiment, the cavity R <b> 10 is configured from a hole that penetrates the substrate 100. Each of the conductor layers 301 and 302 has, for example, a planar conductor pattern around the cavity R10. The planar shape (including dimensions) of the cavity R10 is the same as that of the opening R100.

  In the present embodiment, the entire electronic components 200a and 200b are accommodated in the cavity R10. However, the present invention is not limited to this, and only a part of each of the electronic components 200a and 200b may be disposed in the cavity R10. Each of the electronic components 200a and 200b is disposed in the cavity R10, thereby being positioned on the side of the substrate 100 (X direction or Y direction). In the present embodiment, two electronic components (electronic components 200a and 200b) are arranged in one opening (cavity R10).

  The insulating layer 101 is formed on the first surface F11 of the substrate 100, the conductor layer 301, and the first main surface F3 of the electronic components 200a and 200b. The insulating layer 102 is formed on the second surface F12 of the substrate 100, the conductor layer 302, and the second main surface F4 of the electronic components 200a and 200b. The insulating layer 101 closes an opening on one side (first surface F11 side) of the cavity R10, and the insulating layer 102 closes an opening on the other side (second surface F12 side) of the cavity R10.

  The conductor layer 110 is formed on the insulating layer 101, and the conductor layer 120 is formed on the insulating layer 102.

  An insulator 101a is filled between the electronic components 200a and 200b and the substrate 100 and the insulating layers 101 and 102 in the cavity R10 and between the electronic components 200a and 200b. In the present embodiment, the insulator 101a is made of an insulating material (for example, resin) constituting the insulating layer 101 or the like (for example, a resin insulating layer). In the present embodiment, the insulator 101a has a larger thermal expansion coefficient than any of the substrate 100 and the electronic components 200a and 200b.

  An insulating layer 103 is formed on the insulating layer 101 and the conductor layer 110, and an insulating layer 104 is formed on the insulating layer 102 and the conductor layer 120. A conductor layer 130 is formed on the insulating layer 103, and a conductor layer 140 is formed on the insulating layer 104. In the present embodiment, the conductor layers 130 and 140 are the outermost layers. However, the present invention is not limited to this, and more interlayer insulating layers and conductor layers may be stacked.

  Holes 313a (via holes) are formed in the insulating layer 101, and holes 321a, 322a, and 323a (respectively via holes) are formed in the insulating layer 102. A hole 333 a (via hole) is formed in the insulating layer 103, and a hole 343 a (via hole) is formed in the insulating layer 104. By filling the holes 313a, 321a, 322a, 323a, 333a, 343a with conductors (for example, copper plating), the conductors in the holes become via conductors 313b, 321b, 322b, 323b, 333b, 343b, respectively. (Each filled conductor).

  The via conductor 321b is connected to the electrode 210 of the electronic component 200a or 200b, and the via conductor 322b is connected to the electrode 220 of the electronic component 200a or 200b. Both via conductors 321 b and 322 b are formed in the insulating layer 102. Thus, in this embodiment, the electronic components 200a and 200b are connected to the via conductor only on one side. Hereinafter, this structure is referred to as a single-sided via structure.

  Due to the single-sided via structure, the electrode 210 of the electronic component 200a or 200b and the conductor layer 120 on the insulating layer 102 are electrically connected to each other via the via conductor 321b and insulated from the electrode 220 of the electronic component 200a or 200b. The conductor layer 120 on the layer 102 is electrically connected to each other through the via conductor 322b. Such a structure is advantageous for miniaturization because an electrical connection is formed in the inner layer.

  The via conductors 313b, 323b, 333b, and 343b are respectively disposed immediately above the through-hole conductor 300b (Z direction), and adjacent conductors are in contact with each other. Accordingly, the through-hole conductor and the via conductor, or the via conductors are electrically connected to each other. In the present embodiment, the via conductors 313b, 323b, 333b, 343b and the through-hole conductor 300b are all filled conductors, and these are stacked in the Z direction. Such a stack structure is advantageous for miniaturization.

  The conductor layer 301 and the conductor layer 110 are electrically connected to each other via the via conductor 313b, and the conductor layer 302 and the conductor layer 120 are electrically connected to each other via the via conductor 323b. The conductor layer 110 and the conductor layer 130 are electrically connected to each other via the via conductor 333b, and the conductor layer 120 and the conductor layer 140 are electrically connected to each other via the via conductor 343b. .

  Solder resists 11 and 12 are respectively formed on the conductor layers 130 and 140 (each outermost conductor layer). However, openings 11a and 12a are formed in the solder resists 11 and 12, respectively. For this reason, the predetermined part (part located in the opening part 11a) of the conductor layer 130 is exposed without being covered with the solder resist 11, and becomes the pad P11. In addition, a predetermined part of the conductor layer 140 (part located in the opening 12a) is a pad P12. The pad P11 becomes an external connection terminal for electrical connection with, for example, another wiring board, and the pad P12 becomes an external connection terminal for mounting an electronic component, for example. However, the application of the pads P11 and P12 is not limited to this and is arbitrary.

  The wiring board 10 of this embodiment has pads P11 and P12 (external connection terminals) immediately above the electronic component 200a or 200b (Z direction). Among these, the pad P12 corresponds to, for example, a semiconductor element mounting pad. Each of the via conductors 321b and 322b is electrically connected to one of the pads P12 (each of which is a semiconductor element mounting pad). The wiring board 10 also has pads P11 and P12 (external connection terminals) also directly above the substrate 100 (Z direction).

  Each of the pads P11 and P12 is formed on an insulating layer (insulating layer 103 or 104) located in the outermost layer. The pads P11 and P12 have a corrosion resistant layer made of, for example, a Ni / Au film on the surface thereof. The corrosion resistant layer can be formed by electrolytic plating or sputtering. Moreover, you may form the corrosion-resistant layer which consists of an organic protective film by performing OSP process. The corrosion resistant layer is not an essential component and may be omitted if not necessary.

  In the present embodiment, the electronic components 200a and 200b are composed of the same type of electronic components. Specifically, each of the electronic components 200a and 200b includes a chip capacitor having the structure shown in FIGS. 3A to 6B. Even if the electronic component (chip capacitor) constituting the electronic component 200a and the electronic component (chip capacitor) constituting the electronic component 200b are interchanged, each electronic component operates. In this embodiment, since all the electronic components (electronic components 200a and 200b) arranged in the cavity R10 are composed of the same type of electronic components, it is sufficient to prepare only one type of electronic component. In addition, since the operation for placing the electronic component in the cavity R10 is simplified, the manufacturing is facilitated.

  Hereinafter, the structure of the electronic components 200a and 200b (chip capacitors) incorporated in the wiring board 10 according to the present embodiment will be described with reference to FIGS. 3A to 6B. FIG. 3A is a diagram illustrating a first cross-sectional shape (XZ cross-section) of the electronic components 200a and 200b. FIG. 3B is a diagram illustrating a second cross-sectional shape (YZ cross-section) of the electronic components 200a and 200b. FIG. 4 is a partially enlarged view of FIG. 3A. FIG. 5A is a diagram illustrating a planar shape (XY plane) of the main body 201 of the electronic components 200a and 200b. FIG. 5B is a diagram illustrating a cross-sectional shape (XZ cross section) of the main body 201 of the electronic components 200a and 200b. FIG. 6A is a plan view of the electronic components 200a and 200b. FIG. 6B is a diagram illustrating electrodes formed on each side surface of the main body 201 of the electronic components 200a and 200b.

  Each of the electronic components 200a and 200b includes a main body 201, an electrode 210 (first external electrode), and an electrode 220 (second external electrode) as shown in FIGS. 3A to 6B, for example. Each of the electronic components 200a and 200b is a chip-type MLCC (multilayer ceramic capacitor). The electric capacity of the capacitor is, for example, 0.22 μF.

  As shown in FIGS. 5A and 5B, the main body 201 is configured by alternately laminating a plurality of dielectric layers 231 to 239 and a plurality of conductor layers 211 to 214 and 221 to 224 (respective internal electrodes). Each of the dielectric layers 231 to 239 is made of, for example, ceramic. The main body 201 has a first main surface F31 (third surface) and a second main surface F32 (fourth surface) on the opposite side along the Z direction, and a first side surface F33 along the X direction. And a second side surface F34 on the opposite side, and a third side surface F35 and a fourth side surface F36 on the opposite side along the Y direction. Each of the first to fourth side surfaces F33 to F36 connects the first main surface F31 and the second main surface F32.

  An opening R111 (first opening) and an opening R121 (third opening) are formed in the first main surface F31 of the main body 201, and an opening R112 is formed in the second main surface F32 of the main body 201. (Second opening) and opening R122 (fourth opening) are formed. By forming the openings R111, R112, R121, and R122, both ends of the main body 201 are thinned.

  In the present embodiment, the opening R111 forms a step P111 on the first main surface F31 of the main body 201, and the opening R121 forms a step P121 on the first main surface F31 of the main body 201. In addition, the opening R112 forms a step P112 on the second main surface F32 of the main body 201, and the opening R122 forms a step P122 on the second main surface F32 of the main body 201. Hereinafter, in the first main surface F31, a surface (top surface) positioned on the upper level of the steps P111 and P121 is referred to as an upper surface F310, and a surface (bottom surface) positioned on the lower level of the steps P111 and P121 is referred to as the lower surface F311. It is called F321. Further, in the second main surface F32, the surface (top surface) located on the upper level of the steps P112 and P122 is referred to as an upper surface F320, and the surface (bottom surface) located on the lower level of the steps P112 and P122 is defined as the lower surface F312. It is called F322.

  The first main surface F31 of the main body 201 is composed of an upper step surface F310 and lower step surfaces F311 and F321, and the second main surface F32 of the main body portion 201 is an upper step surface F320, lower step surfaces F312 and F322, Consists of

  Each of the electrodes 210 and 220 (electrode pair) has a U-shaped cross section (XZ cross section) as shown in FIGS. 3A and 4. In this embodiment, as shown in FIGS. 3A, 3B, and 6B, the electrodes 210 are on the first main surface F31, the second main surface F32, the first side surface F33, and the third surface of the main body 201. It is formed on the side surface F35 and the fourth side surface F36. The electrode 220 is formed on the first main surface F31, the second main surface F32, the second side surface F34, the third side surface F35, and the fourth side surface F36 of the main body 201.

  In the present embodiment, as shown in FIGS. 3A and 4, the electrode 210 is integrally formed on the opening R111, the first side surface F33, and over the opening R112. Further, the electrode 220 is integrally formed over the opening R121, the second side face F34, and the opening R122. The openings R111 and R112 are each formed corresponding to the outer shape of the electrode 210, and the openings R121 and R122 are formed corresponding to the outer shape of the electrode 220, respectively. Specifically, the openings R111 and R121 are each formed only in the portion where the electrode 210 or 220 is formed on the first main surface F31, and the openings R112 and R122 are respectively formed on the second main surface F32 where the electrode 210 or 220 is formed. It is formed only in the part to be formed. In such a configuration, it is easy to increase the thickness of the main body portion 201 other than the electrode forming portion, so that it is easy to ensure the necessary strength or electric capacity. Hereinafter, the detailed structure of the electrodes 210 and 220 will be described.

  The electrode 210 includes a plurality of portions covering each part of the main body 201, specifically, an upper portion 210a covering the entire lower step surface F311 of the first main surface F31, a first side portion 210b covering the entire first side surface F33, and a third portion. A third side portion 210d covering a part of the side surface F35, a fourth side portion 210e covering a part of the fourth side surface F36, and a lower portion 210c covering the entire lower step surface F312 of the second main surface F32 are configured. .

  The electrode 220 includes a plurality of portions covering each part of the main body 201, specifically, an upper portion 220a covering the entire lower step surface F321 of the first main surface F31, a second side portion 220b covering the entire second side surface F34, and a third portion. A third side portion 220d that covers a part of the side surface F35, a fourth side portion 220e that covers a portion of the fourth side surface F36, and a lower portion 220c that covers the entire lower step surface F322 of the second main surface F32 are configured. .

  Hereinafter, the upper surface of the upper portion 210a of the electrode 210 is referred to as a first electrode surface F411, the upper surface of the upper portion 220a of the electrode 220 is referred to as a first electrode surface F421, and the upper surface of the lower portion 210c of the electrode 210 is referred to as a second electrode surface F412. The upper surface of the lower part 220c of the electrode 220 is referred to as a second electrode surface F422. As shown in FIG. 3A, the first main surface F3 of the electronic components 200a and 200b includes a first electrode surface F411, an upper step surface F310, and a first electrode surface F421. The second main surface F4 of the electronic components 200a and 200b includes a second electrode surface F412, an upper step surface F320, and a second electrode surface F422.

  In the present embodiment, the upper part 210a, the first side part 210b, the third side part 210d, the fourth side part 210e, and the lower part 210c of the electrode 210 are integrally formed, and the upper part 220a and the second side part 220b of the electrode 220 are formed. The third side portion 220d, the fourth side portion 220e, and the lower portion 220c are integrally formed. The conductor layers 211 to 214 (respective internal electrodes) are respectively connected to the first side part 210b (part of the electrode 210), and the conductive layers 221 to 224 (respective internal electrodes) are respectively connected to the second side part 220b (the electrode 220). A part of).

  As shown in FIG. 4, the electrode 210 includes a first electrode layer 1001 and a second electrode layer 1002. The first electrode layer 1001 is formed on the lower step surface F311 of the first main surface F31, the first side surface F33, and the lower step surface F312 of the second main surface F32. Although not shown in FIG. 4, the first electrode layer 1001 is also formed on the third side surface F35 and the fourth side surface F36 (see FIG. 6B). The second electrode layer 1002 is formed on the first electrode layer 1001. The first electrode layer 1001 and the second electrode layer 1002 are made of different materials. The first electrode layer 1001 is made of nickel, for example. The second electrode layer 1002 is made of, for example, copper plating. The first electrode layer 1001 functions as a seed layer for forming (electroplating) the second electrode layer 1002, for example. However, the present invention is not limited to this, and the first electrode layer 1001 may be formed between the main body 201 and the second electrode layer 1002 in order to ensure adhesion with the main body 201.

  In the present embodiment, the first electrode layer 1001 is formed on the bottom surface and the wall surface of the openings R111, R121, R112, and R122. However, the present invention is not limited to this. For example, the first electrode layer 1001 may not be formed on the wall surfaces of the openings R111, R121, R112, and R122.

  The electrode 220 has a structure similar to that of the electrode 210, for example. Moreover, the electronic component 200b has the same structure as the electronic component 200a, for example. However, the present invention is not limited to this, and the electrode 210 and the electrode 220 may have different structures.

  The electrodes 210 and 220 are located at both ends of the electronic component 200a or 200b. As shown in FIG. 3A, the central portion of the main body 201 located between the electrodes 210 and 220 is not covered with the electrodes 210 and 220, and the upper surface F310 and the upper surface F320 of the main body 201 (in detail) , The dielectric layers 231 and 239) are exposed.

  In the present embodiment, the upper part 210a of the electrode 210 is formed in the opening R111, and the upper part 220a of the electrode 220 is formed in the opening R121. The thickness of the upper part 210a of the electrode 210 and the depth of the opening R111 are substantially the same, and the thickness of the upper part 220a of the electrode 220 and the depth of the opening R121 are substantially the same. That is, the difference between the depth of the opening R111 and the thickness of the upper portion 210a, and the difference between the depth of the opening R121 and the thickness of the upper portion 220a are each about 0 μm. In the present embodiment, since the openings R111 and R121 are completely filled with the upper part 210a of the electrode 210 or the upper part 220a of the electrode 220, respectively, based on the step P111 or P121 formed on the first main surface F31 of the main body part 201. The step is not formed on the first main surface F3 of the electronic components 200a and 200b. In the present embodiment, the boundary between the upper surface F310 of the main body 201 and the first electrode surfaces F411 and F421, and thus the first main surface F3 of the electronic components 200a and 200b becomes substantially flat.

  In the present embodiment, the lower part 210c of the electrode 210 is formed in the opening R112, and the lower part 220c of the electrode 220 is formed in the opening R122. Further, the thickness of the lower part 210c of the electrode 210 and the depth of the opening R112 are substantially the same, and the thickness of the lower part 220c of the electrode 220 and the depth of the opening R122 are substantially the same. That is, the difference between the depth of the opening R112 and the thickness of the lower portion 210c, and the difference between the depth of the opening R122 and the thickness of the lower portion 220c are each about 0 μm. For this reason, like the first main surface F3, the boundary between the upper surface F320 of the main body 201 and the second electrode surfaces F412 and F422, and thus the second main surface F4 of the electronic components 200a and 200b becomes substantially flat.

  In the present embodiment, the bottom surfaces of the openings R111, R112, R121, and R122 are flat, and the depths of the openings R111, R112, R121, and R122 are substantially constant. Thereby, it becomes easy to form an electrode having a uniform thickness in each opening. However, the present invention is not limited to this, and the depths of the openings R111, R112, R121, and R122 may not be substantially constant.

  In the present embodiment, the depths of the openings R111, R112, R121, R122 are, for example, the same. However, it is not limited to this, and they may be different from each other. For example, the openings (for example, the opening R111 and the opening R121) formed on the same main surface have the same thickness, and the openings (for example, the opening R111 and the opening R112) formed on different main surfaces are formed. Different thicknesses may be used.

  FIG. 7 shows a state in which the electronic components 200a and 200b are accommodated in the cavity R10 of the core part.

  As shown in FIG. 7, in the wiring board 10 of the present embodiment, the opening shapes at both ends (the first surface F11 side and the second surface F12 side) of the cavity R10 are respectively rectangular. In the cavity R10, the electronic components 200a and 200b are arranged along one direction (for example, the X direction). Each of the electronic components 200a and 200b has a pair of side electrodes (a first side portion 210b and a second side portion 220b) arranged along the direction in which the electronic components 200a and 200b are arranged (for example, the X direction).

  In the present embodiment, the longitudinal direction of the electronic components 200a and 200b and the direction in which the electrodes 210 and 220 are arranged are both in the X direction and coincide with each other. However, the present invention is not limited to this, and the electrodes 210 and 220 may be arranged along the short direction of the electronic components 200a and 200b.

  In this embodiment, the electrode 210 is a positive electrode (+) and the electrode 220 is a negative electrode (−). In the present embodiment, the electrode 210 (particularly, the first side portion 210b) of the electronic component 200a and the electrode 210 (particularly, the first side portion 210b) of the electronic component 200b face each other, and the opposing electrode 210, 210 are electrically connected to each other via wiring or in contact with each other. The electrode 210 of the electronic component 200a and the electrode 210 of the electronic component 200b are electrically connected to a power source via, for example, Die. The electrode 220 of the electronic component 200a and the electrode 220 of the electronic component 200b are electrically connected to, for example, a common or separate ground. In the present embodiment, the electrode 210 of the electronic component 200a and the electrode 210 of the electronic component 200b have the same polarity (positive electrode) and have substantially the same potential. In addition, the electrode 220 of the electronic component 200a and the electrode 220 of the electronic component 200b have the same polarity (negative electrode) and substantially the same potential.

  In the electronic components 200a and 200b of the present embodiment, as shown in FIGS. 3A to 6B, one end side (for example, the electrode 210 side) and the other end side (for example, the electrode 220 side) in the X direction have a symmetrical structure. Therefore, even if the polarities of the electrode 210 and the electrode 220 are reversed, the electronic components 200a and 200b operate. For this reason, in the wiring board 10 of this embodiment, when arrange | positioning an electronic component in cavity R10, it is not necessary to care about the direction of an electronic component.

  Hereinafter, preferable examples of the material according to the wiring board 10 of the present embodiment will be shown.

  The substrate 100 is made of, for example, a glass cloth (core material) impregnated with an epoxy resin (hereinafter referred to as glass epoxy). The core material is a material having a smaller coefficient of thermal expansion than the main material (in the present embodiment, epoxy resin). As a core material, it is thought that inorganic materials, such as glass fiber (for example, glass cloth or glass nonwoven fabric), an aramid fiber (for example, aramid nonwoven fabric), or a silica filler, are preferable, for example. However, the material of the substrate 100 is basically arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like may be used. The substrate 100 may be composed of a plurality of layers made of different materials.

  In the present embodiment, each of the insulating layers 101, 102, 103, and 104 is formed by impregnating a core material with resin. Specifically, each of the insulating layers 101, 102, 103, and 104 is made of glass epoxy, for example.

  In the present embodiment, the insulating layers 101 and 102 are each made of a resin containing a core material. Thereby, it becomes difficult to form a depression in the insulating layers 101 and 102, and disconnection of the conductor pattern formed on the insulating layers 101 and 102 is suppressed. Moreover, the movement of the electronic components 200a and 200b in the Z direction is suppressed, and the electronic components 200a and 200b are less likely to be displaced in the Z direction. However, there is a concern that the impact on the core portion is increased during the pressing process (see FIG. 28).

  As the core material included in the insulating layers 101, 102, 103, and 104, for example, an inorganic material such as glass fiber (for example, glass cloth or glass nonwoven fabric), aramid fiber (for example, aramid nonwoven fabric), or silica filler is considered preferable. However, the present invention is not limited to this, and other core materials may be used. The material of the insulating layers 101, 102, 103, and 104 is basically arbitrary. For example, instead of an epoxy resin, a polyester resin, a bismaleimide triazine resin (BT resin), an imide resin (polyimide), a phenol resin, an allylated phenylene ether resin (A-PPE resin), or the like may be used. Each insulating layer may be composed of a plurality of layers made of different materials. The insulating layers 101, 102, 103, and 104 may be made of a resin that does not contain a core material.

  In the present embodiment, each of the via conductors 313b, 321b, 322b, 323b, 333b, 343b is made of, for example, copper plating. The shape of each via conductor is, for example, a tapered cylinder (conical frustum) tapered so as to increase in diameter from the core portion toward the upper layer. However, it is not limited to this, and the shape of the via conductor is arbitrary.

  Each of the conductor layers 301, 302, 110, 120, 130, and 140 includes, for example, a copper foil (lower layer) and a copper plating (upper layer). Each of the conductor layers 110, 120, 130, and 140 has, for example, a wiring or land that constitutes an electric circuit, or a planar conductor pattern for increasing the strength of the wiring board 10.

  The material of each conductor layer and each via conductor is arbitrary as long as it is a conductor, and may be metal or nonmetal. Each conductor layer and each via conductor may be composed of a plurality of layers made of different materials.

  Hereinafter, preferable examples of dimensions according to the wiring board 10 of the present embodiment will be shown.

  In FIG. 6A, the width D21 in the longitudinal direction (X direction) of the electronic component 200a is, for example, about 1000 μm, and the width D22 in the short direction (Y direction) of the electronic component 200a is, for example, about 500 μm. The width D23 of the upper part 210a or the lower part 210c of the electrode 210 is, for example, about 230 μm.

The area of the upper part 210a and the lower part 210c (external electrodes on the first main surface F31 and the second main surface F32) of the electrode 210 is, for example, about 0.115 mm ² (= 230 μm × 500 μm). The areas of the upper part 210a and the lower part 210c (external electrodes on the first main surface F31 and the second main surface F32) of the electrode 210 are each preferably 0.2 mm ² or less.

  In addition, the dimension of the electrode 220 is the same as that of the electrode 210, for example. Moreover, the dimension of the electronic component 200b is the same as that of the electronic component 200a, for example. However, the present invention is not limited to this, and the electrode 210 and the electrode 220 may have different dimensions. Moreover, the wiring board which incorporates the some electronic component which has a different dimension may be sufficient.

  In FIG. 6A, the pitch D24 between the via conductor 321b and the via conductor 322b is, for example, about 770 μm.

  In FIG. 7, the width D1 of the cavity R10 in the longitudinal direction (X direction) is, for example, about 2160 μm, and the width D2 of the cavity R10 in the short direction (Y direction) is, for example, about 580 μm.

  The clearance between the electronic component 200a or 200b and the cavity R10 is, for example, about 160 μm (= about 2160 μm−about 1000 μm × 2) in the longitudinal direction (X direction), and is, for example, about 80 μm (= about) in the short direction (Y direction). 580 μm—about 500 μm).

  In FIG. 7, the distance D10 between the adjacent electronic components 200a and 200b, that is, the minimum distance between the opposing first side portions 210b (see FIG. 4B) is, for example, 150 μm or less. However, it is not restricted to this, The 1st side parts 210b which oppose may be contacting.

  The thickness of the substrate 100 is preferably 60 μm or less, and more preferably in the range of 40 to 60 μm. The thickness of the insulating layer 101 and the thickness of the insulating layer 102 are each about 25 μm, for example. The thickness of the insulating layer 101 and the thickness of the insulating layer 102 are the same, for example. However, it is not limited to this, and they may be different from each other.

  The thickness of the insulating layer 103 and the thickness of the insulating layer 104 are each about 25 μm, for example. The thickness of the insulating layer 103 and the thickness of the insulating layer 104 are, for example, the same. However, it is not limited to this, and they may be different from each other.

  In addition, the thickness of each said insulating layer makes the reference | standard (zero) the upper surface of the lower insulating layer (in the case of a lower layer buildup part) the upper surface. That is, for example, the thickness of the insulating layer 101 and the thickness of the insulating layer 102 each correspond to a thickness including the insulator 101a.

  The thickness of the conductor layer 301 and the thickness of the conductor layer 302 are each about 15 μm, for example. The thickness of the conductor layer 301 and the thickness of the conductor layer 302 are, for example, the same. However, it is not limited to this, and they may be different from each other.

  The thickness of the conductor layer 110, the thickness of the conductor layer 120, the thickness of the conductor layer 130, and the thickness of the conductor layer 140 are each about 15 μm, for example. For example, the thickness of the conductor layer 110, the thickness of the conductor layer 120, the thickness of the conductor layer 130, and the thickness of the conductor layer 140 are the same. However, it is not limited to this, and they may be different from each other.

  In FIG. 4, the thickness D20 of the portion of the main body 201 where the opening is not formed is, for example, about 140 μm. In the present embodiment, the upper surface (upper surface F310, F320) of the main body 201 and the upper surfaces (first electrode surfaces F411, F421 and second electrode surfaces F412, F422) of the electrodes 210 and 220 are substantially flush with each other. The thickness D20 of the main body 201 corresponds to the total thickness of each of the electronic components 200a and 200b.

  In the wiring board 10 of the present embodiment, the thickness of the electronic components 200a and 200b is smaller than the thickness of the cavity R10. For this reason, the entire electronic components 200a and 200b are accommodated in the cavity R10. Thereby, it becomes difficult to apply an impact to the electronic components 200a and 200b.

  In the main body 201 (see FIGS. 5A and 5B), the thicknesses of the dielectric layers 232 to 238 are each about 1 μm, for example. The thicknesses of the dielectric layers 231 and 239 (portions where there are no openings) are each about 48 μm, for example. Each of the conductor layers 211 to 214 has a thickness of about 1 μm, for example. Each of the conductor layers 221 to 224 has a thickness of about 1 μm, for example. In the present embodiment, the dielectric layers 232 to 238 have the same thickness, the dielectric layers 231 and 239 have the same thickness, the conductor layers 211 to 214 have the same thickness, and the conductor layer 221. ˜224 have the same thickness. However, it is not limited to this, and they may be different from each other.

  In FIG. 4, the depths of the openings R111, R112, R121, and R122 (in FIG. 4, only the depth D201 of the opening R111 and the depth D202 of the opening R112 are shown) are each about 18 μm, for example. . In the present embodiment, the depths of the openings R111, R121, R112, and R122 and the thicknesses of the electrodes (the upper portions 210a and 220a and the lower portions 210c and 220c) formed therein are substantially the same. However, the present invention is not limited to this, and the depth of each opening and the thickness of the electrode formed there may be different from each other.

  In the present embodiment, the height of the portion of the first main surface F31 of the main body 201 where the opening is not formed (upper surface F310) and the external electrodes (upper portions 210a and 220a) formed in the openings R111 and R121. The heights of the upper surfaces (first electrode surfaces F411 and F421) are substantially the same. In addition, the height of the portion of the second main surface F32 of the main body 201 where the opening is not formed (upper surface F320) and the upper surface of the external electrodes (lower portions 210c and 220c) formed in the openings R112 and R122 ( The heights of the second electrode surfaces F412 and F422) are substantially the same.

  In the present embodiment, an opening R111 (first opening) and an opening R121 (third opening) are formed on the first main surface F31 of the main body 201, and the second main surface F32 of the main body 201 is An opening R112 (second opening) and an opening R122 (fourth opening) are formed. An upper part 210a of the electrode 210 is formed in the opening R111, an upper part 220a of the electrode 220 is formed in the opening R121, and a lower part 210c of the electrode 210 is formed in the opening R112. A lower part 220c is formed in the opening R122. Thus, by forming the electrode in the opening formed in the main body of the electronic component, it is possible to reduce the protrusion of the electrode from the main body. For this reason, it is possible to reduce the thickness of the entire electronic component (thickness including the electrodes). As a result, the wiring board can be made thin (thinned).

  When the protrusion of the electrode from the main body is reduced, the flatness of the main surface of the electronic component is increased. For this reason, when an insulating layer is laminated on the main surface of an electronic component, the surface of the insulating layer can be easily flattened. Further, when a wiring is formed on the insulating layer, disconnection of the wiring is suppressed. It becomes possible.

  Furthermore, when the flatness of the main surface of an electronic component increases, it is thought that the crack of an electronic component is suppressed. This will be described below.

  For example, as shown in FIG. 8, when the opening part is not formed in the main body part 201 of the electronic component and the electrodes 210 and 220 are formed on the main body part 201, the main body part 201 (electrode non-forming part) and the electrode A step P100 is formed at the boundary between 210 and 220 (electrode forming portion). For this reason, when a force is applied to the electronic component, for example, when the electronic component is accommodated in the opening of the substrate or when an insulating layer is formed on both surfaces of the electronic component, the main body 201 is Cracks (for example, crack CK as shown in FIG. 8) are likely to occur.

  In this regard, in the present embodiment, as shown in FIG. 3A, the first main surface F3 and the second main surface F4 of the electronic components 200a and 200b have high flatness. For this reason, no step is formed on the main surfaces of the electronic components 200a and 200b. As a result, the electronic components 200a and 200b are less likely to crack.

  In the wiring board 10 of the present embodiment, the upper surface of the conductor layer 301 and the upper surface of the conductor layer 302 are roughened, respectively, while the first electrode surface F411 and the second electrode surface F412 of the electrode 210 and the first electrode surface of the electrode 220 are roughened. The first electrode surface F421 and the second electrode surface F422 are not roughened (see FIG. 2). Depending on the presence or absence of such roughening treatment, the ten-point average roughness (Rzjis) of the first electrode surfaces F411 and F421 and the second electrode surfaces F412 and F422 is any of the upper surface of the conductor layer 301 and the upper surface of the conductor layer 302, respectively. It is smaller than the point average roughness (Rzjis).

  In the wiring board 10 of the present embodiment, the upper surfaces of the conductor layer 301 and the conductor layer 302 are each roughened to become a rough surface having a large ten-point average roughness. High adhesion can be easily obtained between the conductive layer 302 and the insulating layer 102. In the present embodiment, the upper surfaces of the conductor layers 110, 120, 130, and 140 have the same degree of roughness as the upper surfaces of the conductor layers 301 and 302. Thereby, the adhesiveness between these upper surfaces and the insulating layer or the like formed thereon is improved.

  As described above, according to the wiring board 10 of the present embodiment, the wiring board 10 is made thin (thinned) while maintaining high reliability with respect to the electrical characteristics of the electronic components 200a and 200b incorporated in the wiring board 10. It becomes possible to do. Moreover, it becomes possible to suppress the cracks of the electronic components 200a and 200b.

  Hereinafter, the manufacturing method of the wiring board 10 which concerns on this embodiment is demonstrated.

  First, electronic components 200a and 200b (respective capacitors) are prepared. FIG. 9 is a flowchart showing a schematic content and procedure of the capacitor manufacturing method according to the present embodiment. In the present embodiment, in order to increase manufacturing efficiency, a plurality of capacitors are simultaneously manufactured on one panel, and then each of the capacitors is cut out from the panel. However, the present invention is not limited to this. For example, capacitors may be manufactured one by one.

  In step S11 of FIG. 9, as shown in FIG. 10, the dielectric layer 231, the conductor layer 221, the dielectric layer 232, the conductor layer 211, the dielectric layer 233, the conductor layer 222, the dielectric layer 234, and the conductor A layer 212, a dielectric layer 235, a conductor layer 223, a dielectric layer 236, a conductor layer 213, a dielectric layer 237, a conductor layer 224, a dielectric layer 238, a conductor layer 214, and a dielectric layer 239; Laminate in this order.

  FIG. 11 shows the relationship between the dielectric layers 231 to 239 and the conductor patterns of the conductor layers 211, 212, 213, and 214. FIG. 12 shows the relationship between the dielectric layers 231 to 239 and the conductor patterns of the conductor layers 221, 222, 223, and 224.

  In the present embodiment, at this stage (before cutting), the dielectric layers 231 to 239 have substantially the same outer shape (XY plane). The dielectric layers 231 to 239 and the conductor layers 211 to 214 and 221 to 224 are arranged such that the dielectric layers and the conductor layers are alternately stacked in the manner shown in FIG. 5B. Specifically, the dielectric layers 231 to 239 and the conductor layers 211 to 214 and 221 to 224 are arranged as shown in FIGS. 11 and 12, and a part of the conductor layers 211 to 214 and a part of the conductor layers 221 to 224 are arranged. Are stacked so as to overlap in the Z direction. The conductor patterns of the conductor layers 211 to 214 and the conductor patterns of the conductor layers 221 to 224 are aligned along the X direction, for example, as shown in FIGS. In the present embodiment, the conductor layers are arranged so that these rows overlap when the conductor pattern of each conductor layer is projected onto the XY plane (see FIG. 15 described later). The dielectric layer and the conductor layer can be positioned with a positioning pin, for example.

  Each of the dielectric layers 231 and 239 is formed with a plurality of parallel grooves T10 (for example, grooves in the Y direction) as shown in FIG. The groove T10 can be formed by, for example, mold processing. The dielectric layer and the conductor layer are laminated so that the groove T10 of the dielectric layer 231 and the groove T10 of the dielectric layer 239 overlap in the Z direction. The width and depth of the groove T10 are substantially constant. The width of the groove T10 is, for example, 560 μm, and the depth of the groove T10 is, for example, 18 μm. Note that the groove T10 may be formed before or after cutting after pressing. However, it is considered that the groove T10 having a substantially constant depth is easier to form if the groove T10 is formed before lamination.

  Subsequently, in step S12 of FIG. 9, the laminated dielectric layer and conductor layer are pressed as shown in FIG. Thereby, the dielectric layer and the conductor layer are integrated.

  Subsequently, in step S13 of FIG. 9, the integrated dielectric layer and conductor layer are cut by, for example, dicing. Specifically, for example, as indicated by a line L1 in FIGS. 15 and 16, the center of each of the grooves T10 formed in each of the dielectric layers 231 and 239 is cut along the groove T10 (for example, the Y direction). . Further, for example, as shown by a line L2 in FIG. 15, both sides of the conductor pattern of each conductor layer are cut along a row (for example, the X direction) of the conductor pattern. As a result, a plurality of rectangular plate-like main body portions 201 as shown in FIGS. 5A and 5B are completed. The groove T10 becomes an opening R111, R121, R112, R122 by being cut. The conductor layers 211 to 214 and 221 to 224 are exposed on the cut surface (side surface of the main body 201).

  Subsequently, in step S14 of FIG. 9, plating for forming the electrodes 210 and 220 is performed.

  Specifically, as shown in FIG. 17A, for example, nickel electroless plating films are formed only on both ends of the main body 201 by, for example, immersion plating. Accordingly, as shown in FIG. 17B, the lower surface F311 and F321 of the first main surface F31 of the main body 201, the first side surface F33, the second side surface F34, and the lower surface F312 of the second main surface F32 and A first electrode layer 1001 made of nickel, for example, is formed on the F322. Although not shown in FIG. 17B, the first electrode layer 1001 is also formed on the third side surface F35 and the fourth side surface F36 (see FIG. 6B). In the present embodiment, the first electrode layer 1001 is formed on the bottom surface and the wall surface of the openings R111, R121, R112, and R122.

  Subsequently, as shown in FIG. 18A, an electrolytic plating film of, for example, copper is formed using the first electrode layer 1001 as a seed layer by, for example, barrel plating. Specifically, a desired number of main body parts 201 are put in the plating tank 1000, and electrolytic plating is performed on each of the main body parts 201 while rotating the plating tank 1000. Thereafter, if necessary, the electrolytic plating may be thinned or the plating on the upper surfaces F310 and F320 may be removed by mechanical polishing or etching, for example.

  As a result, as shown in FIG. 18B, a second electrode layer 1002 made of, for example, copper electrolytic plating is formed on the first electrode layer 1001. The first electrode layer 1001 and the second electrode layer 1002 constitute the electrodes 210 and 220.

  Subsequently, in step S15 in FIG. 9, the main body 201 on which the electrodes 210 and 220 are formed is baked at 1200 ° C., for example. Thereby, the electronic components 200a and 200b (each chip capacitor) are completed.

  The wiring board 10 according to the present embodiment is manufactured using the prepared electronic components 200a and 200b. FIG. 19 is a flowchart showing a schematic content and procedure of the method for manufacturing the wiring board 10 according to the present embodiment.

  In step S21 of FIG. 19, a core substrate of the wiring board 10 is prepared, and conductor layers are formed on both surfaces thereof.

  Specifically, as shown in FIG. 20A, a double-sided copper-clad laminate 2000 is prepared as a starting material. Double-sided copper-clad laminate 2000 was formed on substrate 100 (core substrate), metal foil 2001 (for example, copper foil) formed on first surface F11 of substrate 100, and second surface F12 of substrate 100. Metal foil 2002 (for example, copper foil). In the present embodiment, at this stage, the substrate 100 is made of a glass epoxy in a completely cured state (C stage).

Subsequently, as shown in FIG. 20B, using a CO ₂ laser, for example, a hole 2003a is formed by irradiating the double-sided copper-clad laminate 2000 with the laser from the first surface F11 side, and the laser from the second surface F12 side. Is formed on the double-sided copper-clad laminate 2000 to form a hole 2003b. The hole 2003a and the hole 2003b are formed at substantially the same position in the XY plane and are finally connected to form a through hole 300a penetrating the double-sided copper-clad laminate 2000. The shape of the through hole 300a is, for example, an hourglass shape (a drum shape). The boundary between the hole 2003a and the hole 2003b corresponds to the constricted portion 300c (FIG. 1). The laser irradiation on the first surface F11 and the laser irradiation on the second surface F12 may be performed simultaneously or one surface at a time. After the through hole 300a is formed, it is preferable to perform desmearing on the through hole 300a. Undesirable conduction (short circuit) is suppressed by desmear. Further, in order to increase the absorption efficiency of laser light, the surfaces of the metal foils 2001 and 2002 may be blackened prior to laser irradiation. The through hole 300a may be formed by a method other than laser, such as drilling or etching. However, fine processing is easy with laser processing.

  Subsequently, as shown in FIG. 20C, for example, copper plating 2004 is formed on the metal foils 2001 and 2002 and in the through holes 300a by panel plating, for example. Specifically, first, an electroless plating film of copper is formed by, for example, a chemical plating method, and subsequently, using a plating solution, electrolytic plating is performed using the electroless plating film as a seed layer. Form. As a result, the through-hole 300a is filled with the plating 2004, and the through-hole conductor 300b is formed.

  Subsequently, the conductive layers formed on the first surface F11 and the second surface F12 of the substrate 100 are patterned using, for example, an etching resist and an etching solution. Specifically, each conductor layer is covered with an etching resist having a pattern corresponding to the conductor layers 301 and 302, and a portion of each conductor layer that is not covered with the etching resist (part exposed at the opening of the etching resist) Remove by etching. Thus, as shown in FIG. 20D, a conductor layer 301 (first conductor layer) is formed on the first surface F11 of the substrate 100, and a conductor layer 302 (second conductor layer) is formed on the second surface F12 of the substrate 100. Is formed. Note that the etching is not limited to wet, and may be dry.

  In the present embodiment, the conductor layers 301 and 302 each have a three-layer structure of, for example, a copper foil (lower layer), an electroless copper plating (intermediate layer), and an electrolytic copper plating (upper layer). In the present embodiment, the conductor layers 301 and 302 include power supply wiring. However, the pattern of the conductor layers 301 and 302 is not limited to this, and is arbitrary. For example, an alignment mark used in a subsequent process (such as a process of arranging the electronic components 200a and 200b) may be formed on the conductor layer 301 or 302. Moreover, you may remove the conductor of the part corresponding to the shape of opening R100 in the conductor layers 301 and 302 (refer FIG. 22A and FIG. 22B mentioned later).

  Subsequently, in step S22 of FIG. 19, the upper surfaces of the conductor layers 301 and 302 are roughened by chemical etching, for example, as shown in FIG. However, the method for the roughening treatment is not limited to this and is arbitrary. For example, the etching may be wet or dry.

  Subsequently, in step S23 of FIG. 19, for example, the substrate 100 is irradiated with laser light from the first surface F11 side to form an opening R100 (see FIG. 23 described later). Specifically, for example, as shown in FIG. 22A, the region corresponding to the opening R100 in the substrate 100 is surrounded by irradiating a laser beam so as to draw the shape of the opening R100 (see FIG. 7). Cut from the part. The laser irradiation angle is set to be substantially perpendicular to the first surface F11 of the substrate 100, for example.

  Prior to the laser light irradiation, for example, as shown in FIG. 22A, the conductor layer 301 on the substrate 100 is removed (and the conductor layer 302 on the opposite side thereof is also removed) corresponding to the shape of the opening R100. It is preferable to keep it. Further, as shown in FIG. 22B, the conductor layer 301 on the substrate 100 (and the conductor layer 302 on the opposite side thereof as necessary) may be removed along the laser irradiation path. By processing the conductor layer 301 in the form as shown in FIG. 22A or 22B, the position and shape of the opening R100 are clarified, so that alignment of laser irradiation is facilitated. Also, laser processing is facilitated by removing the conductor in the processed portion.

  When the substrate 100 is irradiated with laser light from the first surface F11 side, the amount of laser processing decreases toward the second surface F12 side, and the cut surface of the substrate 100 tends to be a tapered surface. However, when the substrate 100 is thinned, a cut surface that is substantially perpendicular to the main surface (the first surface F11 or the second surface F12) of the substrate 100 is easily obtained. In the present embodiment, the thickness of the substrate 100 is about 60 μm or less. For this reason, as shown in FIG. 23, the wall surface F <b> 10 of the substrate 100 facing the opening R <b> 100 tends to be substantially perpendicular to the main surface of the substrate 100.

  Note that the method of forming the opening R100 is not limited to the laser, and may be any method. For example, the opening R100 may be formed using a mold.

  As a result, as shown in FIG. 23, the substrate 100 having the first surface F11 and the second surface F12 on the opposite side, and the opening R100 penetrating from the first surface F11 to the second surface F12 is formed. The In the present embodiment, the opening R <b> 100 is a hole that penetrates the substrate 100. Further, the opening R100 constitutes a housing space for the electronic components 200a and 200b. Hereinafter, a portion having a thickness from the upper surface of the conductor layer 301 to the upper surface of the conductor layer 302 (accommodating space for the electronic components 200a and 200b) is referred to as a cavity R10.

  Subsequently, in step S24 of FIG. 19, the electronic components 200a and 200b (each chip capacitor) manufactured by the method of FIG. 9 are accommodated in the cavity R10 of the substrate 100. Each of the electronic components 200a and 200b has a structure as shown in FIGS. 3A to 6B.

  Specifically, as shown in FIG. 24, a carrier 2005 made of, for example, PET (polyethylene terephthalate) is provided on one side (for example, the second surface F12) of the substrate 100. As a result, one opening of the cavity R10 (hole) is closed by the carrier 2005. In this embodiment, the carrier 2005 is made of an adhesive sheet (for example, a tape) and has adhesiveness on the substrate 100 side. The carrier 2005 is bonded to the substrate 100 (specifically, the conductor layer 302) by lamination, for example.

  Subsequently, as shown in FIG. 25, electronic components 200a and 200b are inserted into the cavity R10 from the side opposite to the opening where the cavity R10 (hole) is blocked (Z1 side).

  Each of the electronic components 200a and 200b is placed in the cavity R10 by, for example, a component mounter. For example, each of the electronic components 200a and 200b is held by a vacuum chuck or the like, conveyed to the upper side (Z1 side) of the cavity R10, and then descends from there along the vertical direction, and is put into the cavity R10. Thereby, as shown in FIG. 26, the electronic components 200a and 200b have the cavity R10 (opening portion R100) such that the first main surface F3 (and the first main surface F31) is in the same direction as the first surface F11. Housed inside. Electronic components 200a and 200b are arranged adjacent to each other on carrier 2005 (adhesive sheet).

  In the present embodiment, the thickness of the cavity R10 is equal to or greater than the thickness of each of the electronic components 200a and 200b (thickness including the electrodes). For this reason, the entire electronic components 200a and 200b are accommodated in the cavity R10 formed in the core portion.

  Subsequently, in step S25 of FIG. 19, as shown in FIG. 27, the insulating layer 101 and the metal foil 2006 (for example, copper foil with resin) are formed on the conductor layer 301 in a semi-cured state (B stage). . The insulating layer 101 is made of, for example, a glass epoxy prepreg having thermosetting properties. Subsequently, as shown in FIG. 28, by pressing the insulating layer 101 in a semi-cured state, the resin flows out from the insulating layer 101 and flows into the cavity R10. Thus, as shown in FIG. 29, the insulator 101a (insulating layer 101 is formed between the electronic components 200a and 200b and the substrate 100 in the cavity R10, and between the electronic components 200a and 200b, respectively. Resin).

  After the cavity 101 is filled with the insulator 101a, the insulator 101a and the electronic components 200a and 200b are temporarily welded. Specifically, the insulator 101a is heated to develop a holding force that can support the electronic components 200a and 200b. As a result, the electronic components 200a and 200b supported by the carrier 2005 are supported by the insulator 101a. Thereafter, as shown in FIG. 30, the carrier 2005 is removed.

  At this stage, the insulator 101a (filling resin) and the insulating layer 101 are only semi-cured and are not completely cured. However, the invention is not limited to this. For example, the insulator 101a and the insulating layer 101 may be completely cured at this stage.

  As described above, in this embodiment, prior to the arrangement of the electronic components 200a and 200b, the opening on the second surface F12 side of the opening R100 formed in the substrate 100 is closed with the carrier 2005 (support material) (FIG. 24). reference). Then, electronic components 200a and 200b are placed on the carrier 2005 in the opening R100 from the opening on the first surface F12 side of the opening R100 (see FIGS. 25 and 26). Thereafter, the carrier 2005 is removed (see FIG. 30). According to such a method, it becomes easy to arrange the electronic components 200a and 200b in the cavity R10 of the core portion.

  Subsequently, in step S26 of FIG. 19, a lower layer buildup portion is formed.

  Specifically, as shown in FIG. 31, the insulating layer 102 and the metal foil 2007 (for example, a copper foil with resin) are formed on the conductor layer 302 and the second main surface F4 of the electronic components 200a and 200b. The insulating layer 102 is made of, for example, a glass epoxy prepreg having thermosetting properties. Subsequently, the insulating layer 102 is bonded to the conductor layer 302 and the electrodes 210 and 220 in a semi-cured state (B stage) by pressing, for example, and then heated to cure each of the insulating layers 101 and 102.

  Thereby, the first insulating layer (the insulating layer 101 and the insulator 101a) is formed on the first surface F11 of the substrate 100, the conductor layer 301, and the first main surface F3 of the electronic components 200a and 200b. A second insulating layer (insulating layer 102 and insulator 101a) is formed on the second surface F12 of 100, the conductor layer 302, and the second main surface F4 of the electronic components 200a and 200b (see FIG. 32). .

  As described above, in this embodiment, by pressing an insulating layer (insulating layers 101, 102 and insulator 101a) made of a resin containing a core material, the first surface F11, the second surface F12, The insulating layers (the insulating layers 101 and 102 and the insulator 101a) are bonded onto the electronic components 200a and 200b.

  In this embodiment, the insulating layers 101 and 102 are cured simultaneously. By simultaneously curing the insulating layers 101 and 102 formed on both surfaces of the substrate 100, warpage of the substrate 100 is suppressed. As a result, the substrate 100 can be easily thinned.

  Note that the resin may flow out of the insulating layer 102 by the press, and the resin that flows out of the insulating layer 102 may form the insulator 101 a together with the resin that flows out of the insulating layer 101.

  Moreover, you may perform the said press and heat processing in multiple times. Further, the heat treatment and pressing may be performed separately or simultaneously.

  In the present embodiment, the entire electronic components 200a and 200b are accommodated in the cavity R10. For this reason, at the time of the said press, it is hard to apply an impact to the electronic components 200a and 200b in the cavity R10.

  Subsequently, as shown in FIG. 32, holes 313a (via holes) are formed in the insulating layer 101 and the metal foil 2006, for example, by laser, and holes 321a to 323a (respectively, via holes) are formed in the insulating layer 102 and the metal foil 2007. . The hole 313a penetrates the metal foil 2006 and the insulating layer 101, and each of the holes 321a to 323a penetrates the metal foil 2007 and the insulating layer 102. The holes 321a reach the electrodes 210 of the electronic components 200a and 200b, and the holes 322a reach the electrodes 220 of the electronic components 200a and 200b. Each of the holes 313a and 323a reaches the conductor layers 301 and 302 immediately above the through-hole conductor 300b. Then, desmear is performed as needed.

  In this embodiment, since the upper surfaces of the electrodes 210 and 220 are not roughened, the high reflectance of the upper surfaces of the electrodes 210 and 220 is maintained. For this reason, in the formation of the via hole, it is considered that damage to the electrodes 210 and 220 by the laser is suppressed.

  Subsequently, for example, copper electroless plating films 2008 and 2009 are formed on the metal foils 2006 and 2007 and in the holes 313a and 321a to 323a by, for example, chemical plating (see FIG. 33). Prior to electroless plating, a catalyst made of palladium or the like may be adsorbed on the surfaces of the insulating layers 101 and 102, for example, by dipping.

  Subsequently, a plating resist 2010 having an opening 2010a is formed on the main surface (on the electroless plating film 2008) on the first surface F11 side by a lithography technique or printing, and the main surface (nothing on the second surface F12 side). A plating resist 2011 having an opening 2011a is formed on the electrolytic plating film 2009) (see FIG. 33). The openings 2010a and 2011a have patterns corresponding to the conductor layers 110 and 120 (FIG. 34), respectively.

  Subsequently, as shown in FIG. 33, for example, copper electrolytic plating 2012 and 2013 are formed in the openings 2010a and 2011a of the plating resists 2010 and 2011, respectively, by pattern plating, for example. Specifically, copper, which is a material to be plated, is connected to the anode, and electroless plating films 2008, 2009, which are materials to be plated, are connected to the cathode, and immersed in a plating solution. Then, a direct current voltage is applied between the two electrodes to pass a current, and copper is deposited on the surfaces of the electroless plating films 2008 and 2009. Thereby, the holes 313a and 321a to 323a are filled with the electroless plating films 2008 and 2009 and the electrolytic plating 2012 and 2013, respectively, and via conductors 313b and 321b to 323b made of, for example, copper plating are formed. The via conductor 321b (first via conductor) is formed in the insulating layer 102 and connected to the electrode 210 (first external electrode). The via conductor 322b (second via conductor) is formed in the insulating layer 102 and connected to the electrode 220 (second external electrode).

  Thereafter, the plating resists 2010 and 2011 are removed with, for example, a predetermined stripping solution, and then the unnecessary electroless plating films 2008 and 2009 and the metal foils 2006 and 2007 are removed, as shown in FIG. 110 and the conductor layer 120 are formed. The upper surfaces of the conductor layers 110 and 120 are each roughened by, for example, chemical etching. In the present embodiment, the conductor layers 110 and 120 each have a three-layer structure of, for example, a copper foil (lower layer), an electroless copper plating (intermediate layer), and an electrolytic copper plating (upper layer). Thereby, a lower layer buildup part is completed.

  Note that the seed layer for electrolytic plating is not limited to the electroless plating film, and a sputtered film or the like may be used as the seed layer instead of the electroless plating films 2008 and 2009.

  Subsequently, in step S27 of FIG. 19, for example, as shown in FIG. 35, an upper layer buildup portion is formed. For example, the upper layer build-up portion is the same as the lower layer build-up portion, that is, lamination of an insulating layer and a metal foil (for example, copper foil with resin), pressing, resin curing, formation of a via conductor, and formation of a conductor layer (roughness). Can be formed.

  Subsequently, in step S28 of FIG. 19, the solder resist 11 having the opening 11a and the solder resist 12 having the opening 12a are formed on the insulating layers 103 and 104 and the conductor layers 130 and 140, respectively (see FIG. 1). ). The conductor layers 130 and 140 are covered with solder resists 11 and 12 except for predetermined portions (pads P11 and P12, etc.) located in the openings 11a and 12a, respectively. The solder resists 11 and 12 can be formed by, for example, screen printing, spray coating, roll coating, or lamination.

  Subsequently, by electrolytic plating or sputtering, the corrosion resistance made of, for example, a Ni / Au film is formed on the conductor layers 130 and 140, specifically on the surfaces of the pads P11 and P12 (see FIG. 1) not covered with the solder resists 11 and 12, respectively. Form a layer. Moreover, you may form the corrosion-resistant layer which consists of an organic protective film by performing OSP process.

  The wiring board 10 (FIG. 1) of this embodiment is completed by the above process. Thereafter, if necessary, an electrical test (checking of capacitance value, insulation, etc.) of the electronic components 200a and 200b is performed.

  The manufacturing method of this embodiment is suitable for manufacturing the wiring board 10. With such a manufacturing method, it is considered that a good wiring board 10 can be obtained at low cost.

  The wiring board 10 of this embodiment can be electrically connected to, for example, an electronic component or another wiring board. For example, an electronic component (for example, a semiconductor element) can be mounted on the pad P11 or P12 of the wiring board 10 by solder. Further, the wiring board 10 can be mounted on another wiring board (for example, a mother board) by the pads P11 or P12. The wiring board 10 of the present embodiment can be used as a circuit board of a mobile device such as a mobile phone.

  The present invention is not limited to the above embodiment. For example, the present invention can be modified as follows.

  The depth of at least one (for example, all) of the openings R111, R121, R112, and R122 may be larger than the thickness of the electrodes (the upper portions 210a and 220a or the lower portions 210c and 220c) formed in the openings. For example, as shown in FIG. 36A, the depth of the opening R111 may be larger than the thickness of the upper portion 210a of the electrode 210. In the example of FIG. 36A, the height of the portion of the first main surface F31 of the main body 201 where the opening is not formed (upper surface F310) is the upper surface of the external electrode (upper portion 210a) formed in the opening R111. It is higher than the height of (first electrode surface F411).

  The depth of at least one (for example, all) of the openings R111, R121, R112, and R122 may be smaller than the thickness of the electrode (the upper part 210a, 220a or the lower part 210c, 220c) formed in the opening. For example, as shown in FIG. 36B, the depth of the opening R111 may be smaller than the thickness of the upper portion 210a of the electrode 210. In the example of FIG. 36B, the height of the portion (upper surface F310) where the opening is not formed in the first main surface F31 of the main body 201 is the upper surface of the external electrode (upper portion 210a) formed in the opening R111. It is lower than the height of (first electrode surface F411).

  36A and 36B, the difference D30 between the depth of the opening R111 and the thickness of the upper part 210a (or the difference between the depth of the opening R121 and the thickness of the upper part 220a, or the depth of the opening R112 and the thickness of the lower part 210c). Or the difference between the depth of the opening R122 and the thickness of the lower portion 220c) is preferably 5 μm or less. According to such a configuration, the flatness of the main surface of the electronic component is increased, so that cracks and the like due to the steps are less likely to occur.

  The depths of the openings R111, R112, R121, and R122 may not be substantially constant. For example, as shown in FIG. 37A, the depth D201 of the opening R111 may change stepwise. In the example of FIG. 37A, a step P101 is formed on the bottom surface of the opening R111, and the depth on the first side surface F33 side (end side) of the opening R111 is the side of the upper surface F310 of the opening R111. It is larger than the depth of (center side). For example, as shown in FIG. 37B, the depth D201 of the opening R111 may be continuously changed. In the example of FIG. 37B, the bottom surface of the opening R111 has a slope, and the depth of the opening R111 increases from the upper stage surface F310 toward the first side surface F33. The same applies to the openings R112, R121, and R122 other than the opening R111.

  In the above embodiment, the opening is formed only in the portion where the electrode is formed on the main surface (the first main surface F31 or the second main surface F32) of the main body 201. However, the present invention is not limited to this, and for the purpose of improving the adhesion between the electronic component and the insulating layer, for example, as shown in FIG. 38, openings R21 and R22 are formed in the upper surface F310 and F320 of the main body 201, respectively. May be.

  In the above embodiment, openings are formed on both surfaces (the first main surface F31 and the second main surface F32) of the main body 201. However, the present invention is not limited to this, and an opening may be formed only on one surface (first main surface F31 or second main surface F32) of the main body 201, and an external electrode of an electronic component may be formed in the opening.

  For example, as shown in FIG. 39A, openings R111 and R121 may be formed only on the first main surface F31 of the main body 201. In the example of FIG. 39A, since the lower portions 210c and 220c are respectively formed on the second main surface F32, a step is formed on the second main surface F4. However, since the upper portions 210a and 220a are respectively formed in the openings R111 and R121, at least one surface (for example, the first main surface F3) of the main surface of the electronic component is flattened, so that cracks are suppressed. It is done.

  For example, as shown in FIG. 39B, openings R111 and R121 are formed only on the first main surface F31 of the main body 201, and external electrodes (electrodes 210 or 220) of electronic components are formed in the openings R111 and R121, respectively. It may be formed. In the example of FIG. 39B, neither the opening nor the electrode is formed on the second main surface F32 of the main body 201. For this reason, the second main surface F4 of the electronic component corresponds to the second main surface F32 of the main body 201 and is flat. The electrode 210 includes an upper portion 210a that covers the entire lower surface F311 of the first main surface F31, a first side portion 210b that covers the entire first side surface F33, and a third side portion 210d that covers a part of the third side surface F35 (see FIG. 6B) and a fourth side portion 210e (see FIG. 6B) covering a part of the fourth side face F36. The electrode 220 includes an upper part 220a that covers the entire lower surface F321 of the first main surface F31, a second side part 220b that covers the entire second side face F34, and a third side part 220d that covers a part of the third side face F35. (See FIG. 6B) and a fourth side portion 220e (see FIG. 6B) covering a part of the fourth side face F36. For example, via conductors are connected to the upper part 210a of the electrode 210 and the upper part 220a of the electrode 220, respectively. The electrodes 210 and 220 (electrode pairs) each have an L-shaped cross-sectional shape (XZ cross section) as shown in FIG. 39B. One of the electrodes 210 and 220 (electrode pair) may be U-shaped (see FIG. 3A), and the other may be L-shaped (see FIG. 39B).

  As shown in FIG. 40, a non-penetrating opening R100 opening in the second surface F12 may be formed in the substrate 100, and the electronic component 200a may be disposed in the opening R100.

  Although the wiring board 10 of the said embodiment incorporates the two electronic components 200a and 200b, it is not restricted to this. The number of electronic components incorporated in the wiring board 10 is arbitrary, and may be one, for example, or three or more.

  In the wiring board 10 of the above-described embodiment, a plurality of electronic components (electronic components 200a and 200b) are accommodated in one cavity R10 (opening), but the invention is not limited to this. For example, as shown in FIG. 41 (a diagram corresponding to FIG. 7), a plurality of electronic components (for example, electronic components 200a, 200b, 200c, and 200d) are incorporated by accommodating one electronic component per cavity R10. It may be a wiring board.

  In the said embodiment, although the insulating layers 101, 102, 103, and 104 consist of resin containing a core material, respectively, it is not restricted to this. For example, in order to ensure the flatness of each interlayer insulating layer, it is particularly important that the insulating layers 101 and 102 constituting the lower layer buildup portion are made of a resin containing a core material. Therefore, for example, as shown in FIG. 42, even if the insulating layers 103 and 104 do not include the core material, the necessary flatness is often obtained if the insulating layers 101 and 102 include the core material. In FIG. 42, the presence or absence of the core material in the interlayer insulating layer is indicated by the presence or absence of hatching. Further, in the case where necessary flatness can be ensured, any of the insulating layers 101, 102, 103, and 104 may not include a core material.

  In the above embodiment, the electronic components 200a and 200b have a single-sided via structure, but the present invention is not limited to this. For example, as shown in FIG. 43, a wiring board having via conductors 311b, 312b, 321b, and 322b electrically connected to the electrodes 210 and 220 of the electronic components 200a and 200b on both sides of the electronic components 200a and 200b. Good.

  As shown in FIG. 44, the substrate 100 (for example, a core substrate of a wiring board) may be an insulating substrate containing a metal plate 100a (for example, copper foil). In such a substrate 100, heat dissipation is improved by the metal plate 100a. In the example of FIG. 44, a via conductor 100b reaching the metal plate 100a is formed on the substrate 100, and the metal plate 100a and power supply wiring (for example, conductor layers 301 and 302 electrically connected to the ground) are connected to the via conductor. They are electrically connected to each other via 100b. The planar shape (XY plane) of the metal plate 100a is arbitrary, and may be a quadrangle or a circle.

  Hereinafter, an example of a method for manufacturing the substrate 100 (core substrate) shown in FIG. 44 will be described with reference to FIGS. 45A and 45B.

  First, as shown in FIG. 45A, for example, an insulating layer 3001 and a metal foil 2001 (for example, a copper foil with resin), an insulating layer 3002 and a metal foil 2002 (for example, a copper with resin) so as to sandwich a metal plate 100a made of copper foil. Foil). Each of the insulating layers 3001 and 3002 is made of, for example, a glass prepreg.

  Subsequently, pressure is applied toward the metal plate 100a by pressing. By pressing the insulating layers 3001 and 3002 in a semi-cured state (B stage), as shown in FIG. 45B, the resin flows out from the insulating layers 3001 and 3002, respectively. Thereby, the insulating layer 3003 is formed on the side of the metal plate 100a. Then, each of the insulating layers 3001, 3002, and 3003 is cured by heating. Thereby, the board | substrate 100 which incorporates the metal plate 100a is completed.

  In addition, you may perform the said press and heat processing in multiple times. Further, the heat treatment and pressing may be performed separately or simultaneously.

  The shape of the electrode of the chip capacitor accommodated in the cavity R10 (opening) is arbitrary.

  The type of electronic component accommodated in the cavity R10 (opening) is arbitrary. For example, in addition to passive components such as capacitors, resistors, and coils, arbitrary electronic components such as active components such as IC circuits can be employed. Two or more types of electronic components (for example, a capacitor and a diode) may be accommodated in one cavity R10 (opening).

  The configuration of the wiring board 10, in particular, the type, performance, dimensions, material, shape, number of layers, arrangement, etc. of the components can be arbitrarily changed without departing from the spirit of the present invention.

  For example, the number of layers in the build-up part is arbitrary. Further, the number of layers of the build-up portion may be different between the first surface F11 side of the substrate 100 and the second surface F12 side of the substrate 100. However, in order to relieve the stress, it is preferable to increase the symmetry of the front and back by making the number of layers of the buildup portion the same on the first surface F11 side of the substrate 100 and the second surface F12 side of the substrate 100. it is conceivable that.

  Each via conductor is not limited to a filled conductor, and may be a conformal conductor, for example.

  The planar shape (XY plane) of the electronic component and the opening (accommodating portion) is arbitrary, and may be, for example, a substantially circle, or other than a substantially rectangular shape such as a substantially square, a substantially regular hexagon, or a substantially regular octagon. It may be a substantially polygon. The shape of the polygonal corners is arbitrary, and may be, for example, substantially right, acute, obtuse, or rounded. However, in order to reduce the opening (accommodating portion) for the purpose of increasing the wiring area on the substrate, the planar shape (XY plane) of the opening (accommodating portion) is set to the plane of the electronic component to be accommodated. It is preferable to correspond to the shape (XY plane).

  The manufacturing method of the chip capacitor or the wiring board is not limited to the order and contents shown in FIGS. 9 and 19, and the order and contents can be arbitrarily changed without departing from the gist of the present invention. . Moreover, you may omit the process which is not required according to a use etc.

  For example, the formation method of each conductor layer is arbitrary. For example, any one of a panel plating method, a pattern plating method, a full additive method, a semi-additive (SAP) method, a subtractive method, a transfer method, and a tenting method, or a combination of any two or more thereof. A conductor layer may be formed.

  Further, instead of the laser, processing may be performed by wet or dry etching. In the case of processing by etching, it is considered preferable to protect a portion that is not desired to be removed in advance with a resist or the like.

  The said embodiment and modification can be combined arbitrarily. It is considered preferable to select an appropriate combination according to the application. For example, a substrate containing a metal plate shown in FIG. 44 may be applied to the structure shown in any of FIGS.

  The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

  The electronic component built-in wiring board and the chip capacitor according to the present invention are each suitable for a circuit board such as a portable device. The method for manufacturing an electronic component built-in wiring board according to the present invention is suitable for manufacturing such an electronic component built-in wiring board.

DESCRIPTION OF SYMBOLS 10 Wiring board 11, 12 Solder resist 11a, 12a Opening part 100 Substrate 100a Metal plate 100b Via conductor 101, 102, 103, 104 Insulating layer 101a Insulator 110, 120, 130, 140 Conductor layer 200a, 200b, 200c, 200d Electron Component 201 Body 210, 220 Electrodes 210a, 220a Upper 210b First side 210c, 220c Lower 210d, 220d Third side 210e, 220e Fourth side 211-214 Conductor layer 220b Second side 221-224 Conductor layer 231 to 239 Dielectric layer 300a Through hole 300b Through hole conductor 300c Constricted part 301, 302 Conductor layer 311b, 312b Via conductor 313a, 321a to 323a, 333a, 343a Hole 313b, 321b to 323b, 33b, 343b Via conductor 1000 Tank 1001 First electrode layer 1002 Second electrode layer 2000 Double-sided copper-clad laminate 2001, 2002 Metal foil 2003a, 2003b Hole 2005 Carrier 2006, 2007 Metal foil 2008, 2009 Electroless plating film 2010, 2011 Plating Resist 2010a, 2011a Opening 2012, 2013 Electroplating 3001-3003 Insulating layer CK Crack F3 First main surface F4 Second main surface F10 Wall surface F11 First surface F12 Second surface F31 First main surface F32 Second main surface F33 First 1 side surface F34 2nd side surface F35 3rd side surface F36 4th side surface F310 Upper surface F311, F312 Lower surface F320 Upper surface F321, F322 Lower surface F411, F421 1st electrode surface F412, F422 2nd electrode surface P11, P1 Pad R10 cavity R21, R22 opening R100 opening R111, R112 opening R121, R122 opening T10 groove

Claims (23)

A substrate having a first surface and a second surface opposite to the first surface, and an opening opening at least in the second surface;
A main body having a third surface and a fourth surface opposite to the third surface, and an external electrode formed on the main body, so that the third surface is in the same direction as the first surface, An electronic component disposed in the opening formed in the substrate;
An insulating layer formed on the second surface of the substrate and on the electronic component;
A via conductor formed in the insulating layer and connected to the external electrode;
An electronic component built-in wiring board having
An opening is formed in the third surface or the fourth surface of the main body,
At least a part of the external electrode is formed in the opening formed in the third surface or the fourth surface.
An electronic component built-in wiring board. The depth of the opening formed in the third surface or the fourth surface is substantially the same as the thickness of at least a part of the external electrode formed in the opening.
The wiring board with a built-in electronic component according to claim 1. The difference between the depth of the opening formed in the third surface or the fourth surface and the thickness of at least a part of the external electrode formed in the opening is 5 μm or less.
The wiring board with a built-in electronic component according to claim 1 or 2. A depth of the opening formed in the third surface or the fourth surface is larger than a thickness of at least a part of the external electrode formed in the opening;
The wiring board with a built-in electronic component according to any one of claims 1 to 3, wherein the wiring board has a built-in electronic component. The opening formed in the third surface or the fourth surface forms a step in the third surface or the fourth surface of the main body;
The wiring board with a built-in electronic component according to any one of claims 1 to 4. The depth of the opening formed in the third surface or the fourth surface is substantially constant.
The wiring board with a built-in electronic component according to any one of claims 1 to 5. The opening formed in the third surface or the fourth surface is formed only in a portion where the external electrode is formed.
The wiring board with a built-in electronic component according to any one of claims 1 to 6. A first opening is formed in the third surface of the main body,
A second opening is formed in the fourth surface of the main body,
Each of the first opening and the second opening is formed with one portion of the external electrode.
The wiring board with a built-in electronic component according to claim 1, wherein the wiring board has a built-in electronic component. The main body has a first side surface and a second side surface on the opposite side.
The electronic component includes a first external electrode integrally formed over the first opening, the first side surface of the main body, and the second opening.
9. The electronic component built-in wiring board according to claim 8. The first opening and the third opening are formed on the third surface of the main body,
The second opening and the fourth opening are formed on the fourth surface of the main body,
The electronic component includes a second external electrode that is integrally formed over the third opening, the second side surface of the main body, and the fourth opening.
The wiring board with a built-in electronic component according to claim 9. A first via conductor connected to the first external electrode and a second via conductor connected to the second external electrode are formed in the insulating layer.
The wiring board with a built-in electronic component according to claim 10. An insulating layer formed on the first surface of the substrate and on the electronic component;
The opening formed in the substrate penetrates from the first surface to the second surface;
The wiring board with a built-in electronic component according to any one of claims 1 to 11, wherein the wiring board has a built-in electronic component. The insulating layer is made of a resin containing a core material.
The wiring board with a built-in electronic component according to any one of claims 1 to 12. The electronic component is a multilayer ceramic capacitor,
The wiring board with a built-in electronic component according to claim 1, wherein the wiring board has a built-in electronic component. On the insulating layer located at the outermost layer, a semiconductor element mounting pad is formed,
The via conductor is electrically connected to the semiconductor element mounting pad;
The wiring board with a built-in electronic component according to claim 1, wherein the wiring board has a built-in electronic component. A chip capacitor having a main body having a first main surface and a second main surface opposite to the first main surface, and an external electrode formed on the main body,
An opening is formed in the first main surface or the second main surface of the main body,
At least a part of the external electrode is formed in the opening formed in the first main surface or the second main surface.
A chip capacitor characterized by that. A first opening is formed in the first main surface of the main body,
A second opening is formed in the second main surface of the main body,
The main body has a first side surface and a second side surface on the opposite side.
A first external electrode integrally formed on the first opening, on the first side surface of the main body, and over the second opening;
The chip capacitor according to claim 16. The first opening and the third opening are formed on the first main surface of the main body,
The second opening and the fourth opening are formed on the second main surface of the main body,
A second external electrode integrally formed on the third opening, the second side surface of the main body, and the fourth opening;
The chip capacitor according to claim 17. Providing a substrate having a first side and a second side opposite thereto;
Forming an opening in the substrate at least in the second surface;
Providing an electronic component having a main body portion having a third surface and a fourth surface on the opposite side, and an external electrode formed on the main body portion;
Disposing the electronic component in the opening formed in the substrate so that the third surface is in the same direction as the first surface;
Forming an insulating layer on the second surface of the substrate and on the electronic component;
Forming a via conductor connected to the external electrode in the insulating layer;
A method of manufacturing an electronic component built-in wiring board including:
In the preparation of the electronic component, an opening is formed in the third surface or the fourth surface of the main body, and at least a part of the external electrode is formed on the third surface or the fourth surface. Forming in the opening,
A method of manufacturing an electronic component built-in wiring board. Forming an insulating layer on the first surface of the substrate and on the electronic component;
The opening formed in the substrate penetrates from the first surface to the second surface;
The method for manufacturing a wiring board with built-in electronic components according to claim 19. Prior to the placement of the electronic component, including closing the opening on the second surface side of the opening formed in the substrate with a support material,
In the arrangement of the electronic component, the electronic component is placed on the support material in the opening from the opening on the first surface side of the opening formed in the substrate,
After disposing the electronic component in the opening and removing the support material, forming the insulating layer on the second surface of the substrate and on the electronic component;
21. The method of manufacturing an electronic component built-in wiring board according to claim 20. In the formation of the insulating layer, by pressing an insulating layer made of a resin containing a core material, the insulating layer is bonded onto the second surface of the substrate and the electronic component.
The method of manufacturing a wiring board with a built-in electronic component according to any one of claims 19 to 21. In the preparation of the electronic component, the main body portion has a first side surface and a second side surface opposite to the first side surface, and a first opening portion and a third opening portion are formed on the third surface of the main body portion. A second opening and a fourth opening are formed on the fourth surface of the main body, and the first opening, the first side surface of the main body, and the second opening are formed. A first external electrode integrally formed over a portion, and a second external electrode integrally formed over the third opening, the second side surface of the main body, and the fourth opening. Prepare electronic components with
The method of manufacturing a wiring board with a built-in electronic component according to any one of claims 19 to 22.

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