WO2013008552A1

WO2013008552A1 - Wiring board incorporating electronic component, and method for manufacturing wiring board incorporating electronic component

Info

Publication number: WO2013008552A1
Application number: PCT/JP2012/063956
Authority: WO
Inventors: 清水　敬介; 幸信三門; 俊輔酒井; 満広冨川; 俊樹古谷
Original assignee: イビデン株式会社
Priority date: 2011-07-13
Filing date: 2012-05-30
Publication date: 2013-01-17

Abstract

A wiring board (10) has: a substrate (100), which has a first surface (F1), a second surface (F2) on the reverse side of the first surface (F1), a cavity (R10) that penetrates from the first surface (F1) to the second surface (F2), and a through hole (300a); and an electronic component (200) disposed in the cavity (R10). The through hole (300a) is configured by being filled with a conductor, a through hole conductor (300b) is formed of a first conductor portion that is tapered toward the second surface (F2) from the first surface (F1), and a second conductor portion that is tapered toward the first surface (F1) from the second surface (F2), and the first conductor portion and the second conductor portion are connected to each other in the substrate (100).

Description

Electronic component built-in wiring board and manufacturing method thereof

The present invention relates to an electronic component built-in wiring board and a manufacturing method thereof.

Patent Document 1 discloses an electronic component built-in wiring board having a resin substrate (core substrate) in which a cavity is formed and a capacitor disposed in the cavity and positioned on the side of the resin substrate.

Patent Document 2 discloses that an opening (cavity) is formed in the core substrate, a capacitor is accommodated in the opening, and a gap between the core substrate and the capacitor in the opening is filled with resin. Forming an insulating layer on both sides of the core substrate and forming a via conductor connected to the electrode of the capacitor in each insulating layer, and a method of manufacturing a wiring board with a built-in electronic component, and the method An electronic component built-in wiring board is disclosed.

JP 2007-266197 A JP 2002-204045 A

In recent years, thinning of wiring boards has been required. In the wiring board described in Patent Document 1, by incorporating a capacitor, warping is likely to occur due to the difference between the thermal expansion coefficient of the capacitor (particularly ceramic material) and the thermal expansion coefficient of the core substrate (resin substrate). Conceivable. When the wiring board is warped, the connection reliability between the capacitor electrode and the via conductor is likely to be lowered, or delamination of the insulating material is likely to occur on the surface of the capacitor electrode.

In the electronic component built-in wiring board described in Patent Document 2, the angle between the main surface of the core substrate and the side surface facing the opening is a right-angled corner (an angle composed of two planes that intersect at substantially right angles). Yes. For this reason, it is difficult for the capacitor (electronic component) to come into contact with the corner, and the capacitor is easily lost due to the impact. In order to avoid this, if the clearance between the opening and the capacitor is increased, there is a concern that alignment of the via conductors becomes difficult due to the movement of the capacitor after the capacitor is accommodated in the opening.

The present invention has been made in view of such circumstances, and an object thereof is to improve the reliability of electrical connection in a wiring board. Another object of the present invention is to make it easier to put an electronic component into the opening. Another object of the present invention is to make it possible to reduce the clearance between the opening and the electronic component.

The electronic component built-in wiring board according to the present invention,
A core substrate having a first surface, a second surface opposite to the first surface, an opening penetrating from the first surface to the second surface, and a through hole;
A capacitor disposed in the opening;
An electronic component built-in wiring board having
The through hole is filled with a conductor,
The conductor is formed of a first conductor portion that narrows from the first surface toward the second surface and a second conductor portion that narrows from the second surface toward the first surface. The first conductor part and the second conductor part are connected in the core substrate.

The electronic component built-in wiring board according to the present invention,
A substrate having a first surface, a second surface opposite to the first surface, and an opening;
An electronic component having a third surface and a fourth surface opposite to the third surface, the electronic component being disposed in the opening so that the third surface is in the same direction as the first surface of the substrate; ,
An electronic component built-in wiring board having
The electronic component has a curved surface at the corner between the side surface and the fourth surface,
The substrate has a tapered surface at the corner between the inner wall of the opening and the first surface from the first surface toward the second surface.

The manufacturing method of the electronic component built-in wiring board according to the present invention,
Providing a substrate having a first surface and a second surface opposite the first surface;
Preparing an electronic component having a third surface and a fourth surface opposite to the third surface, and having a curved surface at an angle between the fourth surface and the side surface;
Forming an opening in the substrate;
Forming a tapered surface from the first surface toward the second surface at an angle between the inner wall of the opening and the first surface;
Placing the electronic component in the opening with the third surface in the same orientation as the first surface;
including.

In addition, the order of description of each process in the said manufacturing method does not prescribe | regulate the order of a process. For example, the tapered surface may be formed at the same time as the opening is formed, before the opening is formed, or after the opening is formed.

According to the present invention, the reliability of electrical connection in the wiring board can be improved. Further, according to the present invention, in addition to this effect or instead of this effect, there is a case where an effect that it is easy to put an electronic component into the opening may be achieved. Further, according to the present invention, in addition to or in place of these effects, there may be an effect that the clearance between the opening and the electronic component is reduced.

It is sectional drawing of the wiring board which concerns on Embodiment 1 of this invention. It is an enlarged view of the through-hole conductor formed in the core board | substrate in FIG. It is a top view of the through-hole conductor shown to FIG. 2A. It is sectional drawing of the capacitor | condenser incorporated in the wiring board which concerns on Embodiment 1 of this invention. It is a top view which shows the arrangement | positioning and form of the capacitor | condenser accommodated in the cavity in the wiring board which concerns on Embodiment 1 of this invention. It is an enlarged view of the via conductor contained in the 1st buildup part formed in the 1st surface side of a core board | substrate. It is an enlarged view of the via conductor contained in the 2nd buildup part formed in the 2nd surface side of a core board | substrate. It is a figure which shows the capacitor | condenser which has the side electrode which the center part in the thickness direction swells outside the both ends. It is a flowchart which shows the manufacturing method of the wiring board which concerns on Embodiment 1 of this invention. FIG. 8 is a diagram for explaining a step of preparing a substrate (core substrate) in the manufacturing method shown in FIG. 7. In the manufacturing method shown in FIG. 7, it is a figure for demonstrating the 1st process of forming a through-hole conductor and a conductor layer in a board | substrate. It is a figure for demonstrating the 2nd process after the process of FIG. It is a figure for demonstrating the 3rd process after the process of FIG. FIG. 12 is a diagram showing a first example of the shape of a conductor layer formed by the steps shown in FIGS. 9 to 11. FIG. 12 is a view showing a second example of the shape of the conductor layer formed by the steps shown in FIGS. 9 to 11. It is a figure for demonstrating the process of forming a cavity in the manufacturing method shown in FIG. It is a figure which shows the board | substrate after cavity formation in the manufacturing method shown in FIG. FIG. 8 is a diagram for explaining a process of attaching a substrate on which a cavity is formed to a carrier in the manufacturing method shown in FIG. 7. FIG. 8 is a diagram for explaining a step of disposing a capacitor in the cavity in the manufacturing method shown in FIG. 7. FIG. 8 is a diagram showing a state where a capacitor is arranged in the cavity in the manufacturing method shown in FIG. 7. In the manufacturing method shown in FIG. 7, it is a figure for demonstrating the process of forming a 1st interlayer insulation layer and a 1st copper foil on an insulation board | substrate and a capacitor | condenser. In the manufacturing method shown in FIG. 7, it is a figure for demonstrating a press process. It is a figure which shows the state after the press of FIG. 19A. In the manufacturing method shown in FIG. 7, it is a figure for demonstrating the process of forming a 2nd interlayer insulation layer and a 2nd copper foil on an insulated substrate and a capacitor | condenser after carrier removal. In the manufacturing method shown in FIG. 7, a first step of forming a conductor layer on the first and second interlayer insulating layers and electrically connecting the conductor pattern of each conductor layer and the electrode of the capacitor to each other will be described. FIG. It is a figure for demonstrating the 2nd process after the process of FIG. It is a figure for demonstrating the 3rd process after the process of FIG. 22A. It is a figure for demonstrating the 4th process after the process of FIG. 22B. It is a figure for demonstrating the 5th process after the process of FIG. 22C. It is a figure which shows the state by which the electronic component was mounted on the surface of the wiring board which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the electronic component built-in wiring board which concerns on Embodiment 2 of this invention. In the electronic component built-in wiring board concerning Embodiment 2 of this invention, it is a top view which shows the state in which the electronic component was accommodated in the opening part of the core board. It is sectional drawing of the electronic component incorporated in a wiring board. FIG. 6 is a cross-sectional view showing a form of a tapered surface according to a second embodiment. It is sectional drawing which shows the 1st modification of the form of the taper surface which concerns on Embodiment 2. FIG. It is sectional drawing which shows the 2nd modification of the form of the taper surface which concerns on Embodiment 2. FIG. It is sectional drawing which shows the form of the curved surface of the electronic component which concerns on Embodiment 2. FIG. It is sectional drawing which shows the 1st modification of the form of the curved surface of the electronic component which concerns on Embodiment 2. FIG. It is sectional drawing which shows the 2nd modification of the form of the curved surface of the electronic component which concerns on Embodiment 2. FIG. It is a flowchart which shows the manufacturing method of the electronic component built-in wiring board which concerns on Embodiment 2 of this invention. In the manufacturing method which concerns on Embodiment 2, it is sectional drawing for demonstrating the process of preparing a board | substrate. It is a top view for demonstrating the process of carrying out the laser processing of the board | substrate after the process of FIG. 6 is a cross-sectional view for explaining laser processing according to Embodiment 2. FIG. It is sectional drawing which shows the board | substrate with which the opening part was formed by the laser processing which concerns on Embodiment 2. FIG. In the manufacturing method which concerns on Embodiment 2, it is sectional drawing for demonstrating the process of providing a carrier in the one side of a board | substrate. FIG. 10 is a cross-sectional view for explaining a step of preparing an electronic component having a curved surface in the manufacturing method according to the second embodiment. In the manufacturing method which concerns on Embodiment 2, it is sectional drawing which shows the 1st state in the process of putting an electronic component in an opening part. FIG. 36B is a cross-sectional view showing a second state after the first state shown in FIG. 36A. FIG. 36B is a cross-sectional view showing a third state after the second state shown in FIG. 36B. It is sectional drawing for demonstrating the effect | action based on a 1st taper angle. It is sectional drawing for demonstrating the effect | action based on a 2nd taper angle. It is sectional drawing for demonstrating the effect | action based on a 3rd taper angle. In the manufacturing method concerning Embodiment 2, it is sectional drawing which shows the state by which the electronic component was arrange | positioned at the opening part of the board | substrate. In the manufacturing method which concerns on Embodiment 2, it is a figure for demonstrating the process of forming an insulating layer on a board | substrate and an opening part. It is a figure for demonstrating the press process after the process of FIG. 39A. It is a figure which shows a mode that the insulator is filled into the opening part of a board | substrate by the press process of FIG. 39B. It is a figure which shows the state after the press of FIG. 39B. In the manufacturing method which concerns on Embodiment 2, it is a figure for demonstrating the 1st process of buildup. It is a figure for demonstrating the 2nd process after the process of FIG. 41A. It is a figure for demonstrating the 3rd process after the process of FIG. 41B. It is sectional drawing of the electronic component built-in wiring board which concerns on Embodiment 3 of this invention. In the manufacturing method which concerns on Embodiment 3, it is sectional drawing for demonstrating the process of preparing the wiring board used as a starting material. FIG. 44 is a plan view for explaining a step of laser processing the substrate after the step of FIG. 43. FIG. 10 is a plan view for explaining a modification of laser processing according to the third embodiment. It is sectional drawing for demonstrating the laser processing which concerns on Embodiment 3. FIG. In other embodiment of this invention, it is a figure which shows the 1st another example of the through-hole conductor formed in a core board | substrate. It is a figure for demonstrating a 1st process about an example of the manufacturing method of the through-hole conductor shown in FIG. FIG. 47B is a diagram for explaining a second step after the step of FIG. 47A. FIG. 48B is a diagram for explaining a third step after the step of FIG. 47B. FIG. 47D is a diagram for explaining a fourth step after the step of FIG. 47C. It is a figure for demonstrating the 5th process after the process of FIG. 48A. In other embodiment of this invention, it is a figure which shows the 2nd another example of the through-hole conductor formed in a core board | substrate. It is a figure for demonstrating a 1st process about an example of the manufacturing method of the through-hole conductor shown in FIG. It is a figure for demonstrating the 2nd process after the process of FIG. 50A. It is a figure for demonstrating the 3rd process after the process of FIG. 50B. It is a figure for demonstrating the 4th process after the process of FIG. 50C. It is a figure for demonstrating the 5th process after the process of FIG. 51A. In other embodiment of this invention, it is a figure which shows the 3rd another example of the through-hole conductor formed in a core board | substrate. It is a figure which shows the shape of a cavity in the wiring board which concerns on other embodiment of this invention. It is a figure which shows the regular tetragon as another example of the planar shape of a filled conductor. It is a figure which shows the cross shape as another example of the planar shape of a filled conductor. It is a figure which shows the regular polygon star as another example of the planar shape of a filled conductor. In other embodiment of this invention, it is a figure which shows a single-sided wiring board. In other embodiment of this invention, it is a figure which shows the wiring board which has a multilayer structure. In other embodiment of this invention, it is a figure which shows the wiring board which has a core board | substrate which incorporates a metal plate. It is a figure which shows the 1st form of the metal plate used for the wiring board shown in FIG. It is a figure which shows the 2nd form of the metal plate used for the wiring board shown in FIG. In the wiring board shown in FIG. 57, it is a figure which shows the 1st form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 57, it is a figure which shows the 2nd form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 57, it is a figure which shows the 3rd form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 57, it is a figure which shows the 4th form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. It is a figure for demonstrating the 1st process of manufacturing the core board | substrate used for the wiring board shown in FIG. FIG. 61B is a diagram for explaining a second step after the step of FIG. 61A. FIG. 58 is a view showing a periphery of a boundary portion between a capacitor and a core substrate arranged in an opening formed in the core substrate in the wiring board shown in FIG. 57. It is sectional drawing which shows a preferable example of an electronic component built-in wiring board. FIG. 63B is a plan view of the through-hole conductor shown in FIG. 63A. It is a top view which shows the 1st modification of the shape of an opening part. It is a top view which shows the 2nd modification of the shape of an opening part. It is sectional drawing which shows the electronic component built-in wiring board which has the via conductor electrically connected to the electrode of an electronic component on the side which has a taper surface of a core board about other embodiment. It is sectional drawing which shows the electronic component built-in wiring board which has two or more buildup layers on the one side of a core board | substrate about other embodiment. It is sectional drawing which shows the 1st example of the electronic component built-in wiring board which has a conductor layer only in the one side of a core board | substrate about other embodiment. It is sectional drawing which shows the 2nd example of the electronic component built-in wiring board which has a conductor layer only in the one side of a core board | substrate about other embodiment. It is sectional drawing which shows the electronic component built-in wiring board which has an opening part on the surface. It is sectional drawing which shows the electronic component built-in wiring board which has a taper surface on both sides of a core board | substrate. It is sectional drawing which shows the electronic component built-in wiring board by which the taper surface is partially formed in the peripheral part of the opening part. It is sectional drawing which shows the 1st example of the 1st layer from which a material differs, and a 2nd layer. It is sectional drawing which shows the 2nd example of the 1st layer from which a material differs, and a 2nd layer. It is sectional drawing which shows the 3rd example of the 1st layer from which a material differs, and a 2nd layer. It is sectional drawing which shows the 4th example of the 1st layer and 2nd layer from which a material differs. In other embodiment of this invention, it is sectional drawing which shows the electronic component built-in wiring board which has a core board | substrate which incorporates a metal plate. It is a figure for demonstrating the process of putting an electronic component in the opening part formed in the core board | substrate in the manufacturing process of the wiring board comprised from the core board | substrate with which the taper surface is not formed in the corner of the inner wall of an opening part. It is a figure which shows a mode that a mounter and a core board | substrate interfere in the process shown to FIG. 77A. FIG. 77 is a diagram for describing a process of putting an electronic component into the opening formed in the core substrate in the wiring board manufacturing process shown in FIG. 76. FIG. 77 is a diagram showing a first form of a metal plate used for the wiring board shown in FIG. 76. FIG. 77 is a diagram showing a second form of the metal plate used for the wiring board shown in FIG. 76. In the wiring board shown in FIG. 76, it is a figure which shows the 1st form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 76, it is a figure which shows the 2nd form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 76, it is a figure which shows the 3rd form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. In the wiring board shown in FIG. 76, it is a figure which shows the 4th form of the metal plate incorporated in a wiring board, and the conductor layer on a core board | substrate. FIG. 77 is a diagram for describing a first step for manufacturing a core substrate used for the wiring board shown in FIG. 76. It is a figure for demonstrating the 2nd process after the process of FIG. 82A. In the wiring board shown in FIG. 76, it is a figure which shows the periphery of the boundary part of the electronic component arrange | positioned at the opening part formed in the core board | substrate, and a core board | substrate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, arrows Z1 and Z2 indicate the stacking direction of the wiring boards (or the thickness direction of the wiring boards) corresponding to the normal direction of the main surface (front and back surfaces) of the wiring boards. On the other hand, arrows X1 and X2 and Y1 and Y2 respectively indicate directions orthogonal to the stacking direction (or sides of each layer). The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane.

The two principal surfaces facing the opposite normal directions are referred to as the first surface or the third surface (Z1 side surface), the second surface or the fourth surface (Z2 side surface). In the stacking direction, the side closer to the core is referred to as the lower layer (or inner layer side), and the side far from the core is referred to as the upper layer (or outer layer side). Directly above means the Z direction (Z1 side or Z2 side). The planar shape means the shape of the XY plane unless otherwise specified. In the XY plane, the side away from the electronic component (capacitor or the like) built in the wiring board is referred to as the outside, and the side close to the electronic component is referred to as the inside.

The conductor layer is a layer composed of one or more conductor patterns. The conductor layer may include a conductor pattern that constitutes an electric circuit, for example, a wiring (including a ground), a pad, a land, or the like, or a planar conductor pattern that does not constitute an electric circuit.

The opening includes notches and cuts in addition to holes and grooves. The hole is not limited to a through hole, and includes a non-through hole. The holes include via holes and through holes. Hereinafter, a conductor formed in the via hole (wall surface or bottom surface) is referred to as a via conductor, and a conductor formed in the through hole (wall surface) is referred to as a through hole conductor.

In addition to wet plating such as electrolytic plating, plating includes dry plating such as PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

“Preparing” includes purchasing and using finished products in addition to purchasing materials and parts and manufacturing them themselves.

Arrangement of an electronic component (for example, a capacitor) in the opening includes not only that the entire electronic component is completely accommodated in the opening, but also that only a part of the electronic component is arranged in the opening. It is.

Unless otherwise specified, the “width” of a hole or column (projection) means a diameter in the case of a circle, and 2√ (cross-sectional area / π) otherwise.

In principle, whether or not a non-uniform dimension (such as the thickness of a part with unevenness or the width of a tapered part) is included in a given range is the average value of that dimension (average of only effective values excluding abnormal values) Is included in the range. However, this does not apply when it is clearly stated that a value other than the average value is used, such as the maximum value.

In addition, when comparing the contents, unless otherwise specified, compare by weight per unit volume.

(Embodiment 1)
As shown in FIG. 1, the wiring board 10 according to the present embodiment includes a substrate 100 (insulating substrate), a first buildup unit B1, a second buildup unit B2, and an electronic component 200 (in this embodiment, Capacitor) and solder resists 11 and 12. The wiring board 10 of this embodiment is a rectangular wiring board. However, the wiring board 10 may be a flexible wiring board. Hereinafter, one of the front and back surfaces (two main surfaces) of the substrate 100 is referred to as a first surface F1, and the other is referred to as a second surface F2. Of the front and back surfaces (two main surfaces) of the electronic component 200, a surface facing the same direction as the first surface F1 is referred to as a third surface F3, and the other is referred to as a fourth surface F4.

The first buildup portion B1 is formed on the first surface F1 side of the substrate 100, and the second buildup portion B2 is formed on the second surface F2 side of the substrate 100. The first buildup part B1 is composed of an insulating layer 101 (interlayer insulating layer) and a conductor layer 110, and the second buildup part B2 is composed of an insulating layer 102 (interlayer insulating layer), a conductor layer 120, Consists of The electronic component 200 is built in the wiring board 10. Solder resists 11 and 12 are formed on the first buildup part B1 and the second buildup part B2, respectively.

The substrate 100 has an insulating property and becomes a core substrate of the wiring board 10. A conductor layer 301 is formed on the first surface F1 of the substrate 100, and a conductor layer 302 is formed on the second surface F2 of the substrate 100. A cavity R10 is formed in the substrate 100. The cavity R10 corresponds to an opening in which the electronic component 200 is accommodated. In the present embodiment, the cavity R 10 includes a hole that penetrates the substrate 100.

The electronic component 200 is located in the side of the substrate 100 (X direction or Y direction) by being disposed in the cavity R10. In the present embodiment, substantially the entire electronic component 200 is completely accommodated in the cavity R10. However, the present invention is not limited to this, and only a part of the electronic component 200 may be disposed in the cavity R10. In the present embodiment, the insulator 101a is filled in the gap R1 between the electronic component 200 and the substrate 100 in the cavity R10. In this embodiment, the insulator 101a is made of an insulating material (more specifically, a resin) constituting the upper insulating layer 101 (more specifically, a resin insulation layer) (see FIG. 19A). The insulator 101a has a larger thermal expansion coefficient than either the substrate 100 or the electronic component 200. The insulator 101a completely covers the periphery of the electronic component 200. Thereby, the electronic component 200 is protected by the insulator 101a (resin) and fixed at a predetermined position.

The insulating layer 101 (first insulating layer) is formed on the first surface F1 of the substrate 100 and the third surface F3 of the electronic component 200, and the insulating layer 102 (second insulating layer) is the second surface of the substrate 100. It is formed on F 2 and on the fourth surface F 4 of the electronic component 200. The opening on one side (first surface F1 side) of the cavity R10 (hole) is closed by the insulating layer 101, and the opening on the other side (second surface F2 side) of the cavity R10 (hole) is closed by the insulating layer 102. It is. In the present embodiment, the conductor layers 110 and 120 are the outermost layers. However, the present invention is not limited to this, and more interlayer insulating layers and conductor layers may be stacked (see FIG. 56 described later).

The conductor layer 110 is the outermost conductor layer on the first surface F1 side, and the conductor layer 120 is the outermost conductor layer on the second surface F2 side. Solder resists 11 and 12 are formed on the conductor layers 110 and 120, respectively. However,

openings

11a and 12a are formed in the solder resists 11 and 12, respectively. For this reason, the predetermined part (part located in the opening part 11a) of the conductor layer 110 is exposed without being covered with the solder resist 11, and becomes the pad P1. Moreover, the predetermined site | part (site located in the opening part 12a) of the conductor layer 120 becomes the pad P2. The pad P1 becomes an external connection terminal for electrical connection with, for example, another wiring board, and the pad P2 becomes an external connection terminal for mounting an electronic component, for example (see FIG. 24 described later). However, the application of the pads P1 and P2 is not limited to this and is arbitrary.

In this embodiment, the pads P1 and P2 have a corrosion-resistant layer made of, for example, a Ni / Au film on the surface thereof. The corrosion resistant layer can be formed by electrolytic plating or sputtering. Moreover, you may form the corrosion-resistant layer which consists of an organic protective film by performing OSP (Organic | Solderability | Preservative) process. The corrosion resistant layer is not an essential component and may be omitted if not necessary.

A through hole 300a is formed in the substrate 100 (core substrate), and a through hole conductor 300b is formed by filling the through hole 300a with a conductor (for example, copper plating). In the present embodiment, the through-hole conductor 300b has an hourglass shape (a drum shape).

As shown in FIG. 2A, the through-hole conductor 300b of the present embodiment includes a first conductor portion R11 having a width that increases from the reference surface F0 in the substrate 100 (core substrate) toward the first surface F1, and a reference surface F0. And a second conductor portion R12 that increases in width toward the second surface F2. As shown in FIG. 2B, the planar shape of the first conductor portion R11 and the second conductor portion R12 is, for example, a circle. That is, the shapes of the first conductor portion R11 and the second conductor portion R12 in the present embodiment are each a tapered cylinder (conical frustum) tapered so that the width becomes narrower (thinner) toward the reference plane F0. The through-hole conductor 300b is formed by directly connecting the first conductor portion R11 and the second conductor portion R12 at the reference plane F0. The through-hole conductor 300b has a constricted portion 300c having a minimum width, and the constricted portion 300c is located on the reference plane F0. In the present embodiment, the reference plane F0 corresponds to the XY plane. As shown in FIG. 2B, the planar shape of the constricted portion 300c is, for example, a circle.

In the present embodiment, the dimension T11 from the first surface F1 to the reference surface F0 and the dimension T12 from the second surface F2 to the reference surface F0 are substantially the same. The first conductor portion R11 gradually becomes thinner from the first surface F1 toward the constricted portion 300c (reference surface F0), and the second conductor portion R12 is constricted from the second surface F2 to the constricted portion 300c (reference surface F0). It gets thinner gradually as you get closer to. Here, the taper angle θ1 of the first conductor portion R11 and the taper angle θ2 of the second conductor portion R12 are substantially the same. The through-hole conductor 300b has a symmetrical shape with respect to the reference plane F0. Note that the taper angle corresponds to a rate at which the width is narrowed or a rate at which the width is widened.

In the present embodiment, the wall surface of the through hole 300a is a flat surface. Thereby, the taper angle of the first conductor portion R11 and the taper angle of the second conductor portion R12 are respectively substantially constant. However, the present invention is not limited to this, and the wall surface of the through hole 300a may be a curved surface (see FIGS. 46 and 49). Each of the conductor layers 301 and 302 includes a land of the through-hole conductor 300b.

Here, an example of a preferable value of each dimension of the through-hole conductor 300b is shown. The width D31 of the end surface on the first surface F1 side is 80 μm, the width D32 of the constricted portion 300c is 50 μm, and the width D33 of the end surface on the second surface F2 side is 80 μm.

The insulating layer 101 has

holes

311a and 312a (respectively via holes), and the insulating layer 102 has

holes

321a and 322a (respectively via holes). By filling the

holes

311a, 312a, 321a, and 322a with conductors (for example, copper plating), the conductors in the holes become via

conductors

311b, 312b, 321b, and 322b (respectively filled conductors). In the present embodiment, the hole 311a corresponds to the first via hole, and the hole 321a corresponds to the second via hole.

Each of the

holes

311a and 321a reaches the

electrodes

210 and 220 of the electronic component 200, and the via

conductors

311b and 321b are respectively connected to the

electrodes

210 and 220 of the electronic component 200 from the first surface F1 side or the second surface F2 side of the substrate 100. 220 is electrically connected. Each of the conductor (via conductor 311b) filled in the hole 311a (first via hole) and the conductor (via conductor 321b) filled in the hole 321a (second via hole) becomes narrower toward the electronic component 200. It is electrically connected to the electrode of the component 200. Thus, in this embodiment, the electronic component 200 is connected to the via

conductors

311b and 321b from both sides. Hereinafter, this structure is referred to as a double-sided via structure. In the present embodiment, it is considered that the double-sided via structure brings the structure of the wiring board 10 close to vertical symmetry and suppresses the warping of the wiring board 10.

Due to the double-sided via structure, the

electrodes

210 and 220 of the electronic component 200 and the conductor layer 110 on the insulating layer 101 are electrically connected to each other via the via conductor 311b, and the

electrodes

210 and 220 of the electronic component 200 are also connected. And the conductor layer 120 on the insulating layer 102 are electrically connected to each other through a via conductor 321b. In the present embodiment, the electronic component 200, the via conductor 311b, and the via conductor 321b constitute a power supply line.

In addition, the conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layer 110 on the insulating layer 101 are electrically connected to each other via the via conductor 312b, and on the second surface F2 of the substrate 100. The conductor layer 302 and the conductor layer 120 on the insulating layer 102 are electrically connected to each other through the via conductor 322b. Further, the conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layer 302 on the second surface F2 of the substrate 100 are electrically connected to each other through the through-hole conductor 300b. The via

conductors

312b and 322b and the through-hole conductor 300b are all filled conductors, and a filled stack S is formed by stacking them in the Z direction. In the present embodiment, the filled stack S constitutes a signal line.

The electronic component 200 is, for example, a chip-type MLCC (multilayer ceramic capacitor) as shown in FIG. 3, and includes a capacitor body 201 and

U-shaped electrodes

210 and 220. The capacitor body 201 includes a plurality of dielectric layers 231 to 239 and a plurality of conductor layers 211 to 214 and 221 to 224 that are alternately stacked. Each of the dielectric layers 231 to 239 is made of, for example, ceramic. The

electrodes

210 and 220 are formed at both ends of the capacitor body 201, respectively. The capacitor body 201 is covered with

electrodes

210 and 220 from the lower surface (the surface on the fourth surface F4 side), the side surface, and the upper surface (the surface on the third surface F3 side). Hereinafter, in the electrode 210, a portion covering the upper surface of the capacitor body 201 is referred to as an upper portion 210a, a portion covering the side surface of the capacitor body 201 is referred to as a side portion 210b, and a portion covering the lower surface of the capacitor body 201 is referred to as a lower portion 210c. Further, in the electrode 220, a portion covering the upper surface of the capacitor body 201 is referred to as an upper portion 220 a, a portion covering the side surface of the capacitor body 201 is referred to as a side portion 220 b, and a portion covering the lower surface of the capacitor body 201 is referred to as a lower portion 220 c. In the present embodiment, the

side portions

210b and 220b each correspond to a side electrode. The

upper portions

210a and 220a are each electrically connected to the via conductor 311b, and the

lower portions

210c and 220c are each electrically connected to the via conductor 321b. In the present embodiment, the surfaces of the

electrodes

210 and 220 of the electronic component 200 are not roughened.

As shown in FIG. 3, the central portion of the capacitor body 201 located between the electrode 210 and the electrode 220 is not covered with the

electrodes

210 and 220, and the dielectric layers 231 and 239 (ceramic) are exposed. The target strength is weakened. However, in the state in which the electronic component 200 is mounted (built in) the wiring board 10, the central portion of the capacitor body 201 is covered with the insulating

layers

101 and 102 or the insulator 101 a, so that the insulating material (resin or the like) is used. It is considered that the capacitor body 201 is protected.

FIG. 4 shows a state in which the electronic component 200 is accommodated in the cavity R10 of the substrate 100 (core substrate).

The cavity R10 penetrates the substrate 100. The opening shapes at both ends (the first surface F1 side and the second surface F2 side) of the cavity R10 are substantially rectangular. The shape of the electronic component 200 is, for example, a rectangular plate shape, and the shape of the main surface of the electronic component 200 is, for example, a substantially rectangular shape. In the present embodiment, the electronic component 200 has a planar shape (for example, a similar shape having substantially the same size) corresponding to the cavity R10.

Here, an example of a preferable value of each dimension shown in FIGS. 1 to 3 is shown.

The thickness T1 of the wiring board 10 (FIG. 1), that is, the thickness from the solder resist 11 to the solder resist 12 is 290 μm. The thickness T20 (FIG. 2A) of the substrate 100 (core substrate) is 106 μm. The thickness T3 (FIG. 3) of the electronic component 200, specifically the thickness including the

electrodes

210 and 220, is 150 μm. Each of the conductor layers 301 and 302 has a thickness T4 (FIG. 2A) of 20 μm. Each of the insulating

layers

101 and 102 has a thickness T5 (FIG. 1) of 39 μm. Each of the conductor layers 110 and 120 has a thickness T6 (FIG. 1) of 18 μm. Each of the solder resists 11 and 12 has a thickness T7 (FIG. 1) of 15 μm.

Regarding the thickness T1 of the wiring board 10, the total thickness T2 (= T20 + T4 × 2) of the substrate 100 (core substrate) and the conductor layers 301 and 302 on both sides thereof, and the thickness T3 of the electronic component 200, T3 It is preferable that / T2 is in the range of 0.6 to 1.7 and T3 / T1 is in the range of 0.2 to 0.7. If it is such a dimension, it will be estimated that it becomes easy to suppress curvature.

Next, an example of preferable values for each dimension shown in FIG. 4 is shown.

The longitudinal width D1 of the cavity R10 is 1080 μm, and the lateral width D2 of the cavity R10 is 580 μm. The width D11 in the longitudinal direction of the electronic component 200 is 1000 μm, and the width D12 in the short direction of the electronic component 200 is 500 μm. The width D3 in the longitudinal direction of the gap between the electronic component 200 and the cavity R10 is 40 μm (the clearance is twice 80 μm), and the width D4 in the short direction of the gap between the electronic component 200 and the cavity R10 is 40 μm (clearance). Is twice 80 μm). The width D13 of the upper part 210a or the lower part 210c of the electrode 210 or the upper part 220a or the lower part 220c of the electrode 220 is 230 μm.

The via conductor 311b and the via conductor 321b are arranged to face each other with the electronic component 200 interposed therebetween, for example. The pitch D5 of the via

conductor

311b or 321b is 770 μm.

At least one of the front and back surfaces (third surface F3 and fourth surface F4) of electronic component 200 preferably has

electrodes

210 and 220 with an area occupancy of 40% to 90%. In other words, the proportion of the

upper surface

210a and 220a in the third surface F3 of the electrode 210 (hereinafter referred to as the first area occupation ratio) is preferably in the range of 40% to 90%. Further, the ratio of the

lower portions

210c and 220c in the fourth surface F4 of the electrode 220 (hereinafter referred to as the second area occupation ratio) is preferably in the range of 40% to 90%. When the first or second area occupation ratio is 40% or more, alignment of electrical connection (via connection) between the

electrodes

210 and 220 and the via

conductors

311b and 321b becomes easy. In addition, when the first or second area occupancy is 90% or less, delamination is less likely to occur on the surfaces of the

electrodes

210 and 220. Therefore, a treatment for suppressing delamination, for example, the surfaces of the

electrodes

210 and 220 This makes it easy to omit the roughening process. In the present embodiment, the first and second area occupation ratios (%) correspond to 100 × (width D12 × width D13 + width D12 × width D13) / (width D11 × width D12), respectively.

In the present embodiment, for example, as shown in FIG. 4, a plurality of through-hole conductors 300 b (and filled stacks S) are arranged around the electronic component 200. However, the arrangement and the number of through-hole conductors 300b are not limited to this and are arbitrary. The number of through-hole conductors 300b may be one or plural.

The substrate 100 is made of, for example, a glass cloth (core material) impregnated with an epoxy resin (hereinafter referred to as glass epoxy). The core material is a material having a smaller coefficient of thermal expansion than the main material (in the present embodiment, epoxy resin). As a core material, it is thought that inorganic materials, such as glass fiber (for example, glass cloth or a glass nonwoven fabric), an aramid fiber (for example, an aramid nonwoven fabric), or a silica filler, are preferable, for example. However, the material of the substrate 100 is basically arbitrary. For example, polyester resin, bismaleimide triazine resin (BT resin), imide resin (polyimide), phenol resin, or allylated phenylene ether resin (A-PPE resin) may be used instead of epoxy resin. The substrate 100 may be composed of a plurality of layers made of different materials.

In this embodiment, each of the insulating

layers

101 and 102 is formed by impregnating a core material with resin. The insulating

layers

101 and 102 are made of glass epoxy, for example. However, the present invention is not limited to this. For example, the insulating

layers

101 and 102 may be made of a resin that does not contain a core material. In addition, the material of the insulating

layers

101 and 102 is basically arbitrary. For example, polyester resin, bismaleimide triazine resin (BT resin), imide resin (polyimide), phenol resin, or allylated phenylene ether resin (A-PPE resin) may be used instead of epoxy resin. Each insulating layer may be composed of a plurality of layers made of different materials.

The conductor layer 110 is composed of a copper foil 111 (lower layer) and a copper plating 112 (upper layer), and the conductor layer 120 is composed of a copper foil 121 (lower layer) and a copper plating 122 (upper layer). . The conductor layers 110 and 120 include, for example, wirings and lands constituting an electric circuit (for example, an electric circuit including the electronic component 200), a solid pattern for increasing the strength of the wiring board 10, and the like.

Each of the via conductors 312b electrically connected to the conductor layer 301 has a width narrowing toward the reference plane F0 as shown in FIG. Further, each of the via conductors 311b electrically connected to the electrodes 210 and 220 (specifically, the

upper portions

210a and 220a) of the electronic component 200 becomes narrower toward the reference plane F0 as shown in FIG. ing. In the present embodiment, as shown in FIG. 5A, the shape of each of the via

conductors

311b and 312b is a tapered cylinder tapered so as to increase in width from, for example, the conductor layer 301 or the

electrodes

210 and 220 of the electronic component 200 toward the upper layer. (Conical frustum). Each of the via

conductors

311b and 312b is made of, for example, copper plating.

On the other hand, as shown in FIG. 1, each of the via conductors 322b electrically connected to the conductor layer 302 has a width narrowing toward the reference plane F0. Further, each of the via conductors 321b electrically connected to the electrodes 210 and 220 (specifically, the

lower portions

210c and 220c) of the electronic component 200 becomes narrower toward the reference plane F0 as shown in FIG. ing. In this embodiment, as shown in FIG. 5B, the via

conductors

321b and 322b are tapered such that the width increases from the conductor pattern of the conductor layer 302 or the

electrodes

210 and 220 of the electronic component 200 toward the upper layer, for example. Taper cylinder (conical frustum). Each of the via

conductors

321b and 322b is made of, for example, copper plating.

The thermal expansion coefficient (X, Y direction) of the substrate 100 is in the range of 3 ppm to 11 ppm, for example, and the thermal expansion coefficient of the electronic component 200 is in the range of 10 ppm to 15 ppm, for example. However, when the thickness T20 of the substrate 100 (FIG. 2A) is in the range of 0.06 mm to 1.0 mm, the thermal expansion coefficient of the substrate 100 (core substrate) is the same as the thermal expansion coefficient of the electronic component 200 or It is preferable to be smaller than this. Thereby, even when the board | substrate 100 (core board | substrate) is thin, it becomes easy to suppress curvature.

The material of each conductor layer and each via conductor is arbitrary as long as it is a conductor, and may be metal or nonmetal. Each conductor layer and each via conductor may be composed of a plurality of layers made of different materials.

The substrate 100 according to the present embodiment includes a first conductor portion R11 that increases in width from the reference surface F0 in the substrate 100 (core substrate) toward the first surface F1, and from the reference surface F0 toward the second surface F2. A through-hole conductor 300b (see FIG. 2A) having a second conductor portion R12 that is wider is formed. For this reason, for example, as shown in FIG. 6, in the case where the central portion in the thickness direction (Z direction) of the electronic component 200 swells outside the both end portions in the side portion 210 b (side surface electrode) of the electrode 210. The distance D0 between 300b and the electronic component 200 (specifically, the surface of the side portion 210b) is likely to be substantially uniform in the thickness direction of the electronic component 200. As a result, the amount of shrinkage due to thermal stress between the through-hole conductor 300b and the electronic component 200 becomes substantially uniform in the thickness direction of the electronic component 200, so that the wiring board 10 is less likely to be distorted. As a result, warping of the wiring board 10 is suppressed. And by suppressing the curvature of the wiring board 10, it becomes difficult to produce the delamination on the surface of the

electrodes

210 and 220 of the electronic component 200, the crack in each electrical connection part, the crack of the electronic component 200, etc. As a result, the reliability of electrical connection in the wiring board 10 is improved. In addition, since the distance D0 is uniform, it is easy to ensure the insulation reliability between the through-hole conductor 300b and the electronic component 200. As a result, the through-hole conductor 300b and the electronic component 200 can be brought close to each other, and the through-hole conductor 300b can be easily disposed in the vicinity of the electronic component 200. The distance D0 between the through-hole conductor 300b and the electronic component 200 is preferably in the range of 150 μm to 500 μm. When the distance D0 is within such a range, it is easy to reduce the size of the wiring board 10 while ensuring the insulation reliability between the through-hole conductor 300b and the electronic component 200. In a particularly preferred example, the distance D0 is 200 μm.

In the example of FIG. 6, the center part of the side electrode (side part 210b) swells outward by a dimension D20 from both end parts.

In the present embodiment, all via conductors (via

conductors

311b and 312b) formed in the insulating layer 101 (first insulating layer) become narrower toward the reference plane F0, and the insulating layer 102 (second insulating layer). All via conductors (via

conductors

321b and 322b) formed in the layer) become narrower toward the reference plane F0. Thereby, it is considered that stress and the like are easily concentrated on the reference plane F0 in the substrate 100 (core substrate), and the stress distribution in the XY plane can be made uniform. As a result, it is considered that the warpage of the wiring board 10 is suppressed and the reliability of electrical connection in the wiring board 10 is improved.

The via conductor of the wiring board 10 has a symmetrical structure with respect to the reference plane F0. Specifically, the via conductors (via

conductors

311b and 312b) located on the first surface F1 side of the reference surface F0 and the via conductors (via

conductors

321b and 322b) located on the second surface F2 side of the reference surface F0 are: They have a symmetrical arrangement and shape (see FIG. 1). Thereby, it is considered that stress is easily canceled on both sides of the reference plane F0. As a result, it is considered that the warpage of the wiring board 10 is suppressed and the reliability of electrical connection in the wiring board 10 is improved.

When there is an imbalance between thermal expansion and thermal contraction between the upper and lower sides (Z1 side and Z2 side) sandwiching the reference plane F0 of the wiring board 10, it is considered that the wiring board 10 is likely to warp. However, in the present embodiment, since the highly rigid electronic component 200 (for example, MLCC) and the through-hole conductor 300b are located in the vicinity of the reference plane F0, even in such a case, the wiring board 10 is hardly warped. That is, in the region where the electronic component 200 exists, the warpage is suppressed because the rigidity of the electronic component 200 is high. Further, even in a region where the electronic component 200 does not exist, thermal stress is propagated outward from the reference plane F0 and thus to the entire substrate 100 by the through-hole conductor 300b which has high rigidity and becomes wider as it is away from the reference plane F0. It becomes difficult. As a result, warping of the wiring board 10 is suppressed.

Hereinafter, a method for manufacturing the wiring board 10 will be described with reference to FIG. FIG. 7 is a flowchart showing a schematic content and procedure of the method for manufacturing the wiring board 10 according to the present embodiment.

In step S11, as shown in FIG. 8, a double-sided copper-clad laminate 1000 is prepared as a starting material. The double-sided copper clad laminate 1000 includes a substrate 100 (core substrate), a copper foil 1001 formed on the first surface F1 of the substrate 100, a copper foil 1002 formed on the second surface F2 of the substrate 100, Consists of In the present embodiment, at this stage, the substrate 100 is made of a glass epoxy in a completely cured state (C stage).

Subsequently, in step S12 of FIG. 7, the through-hole conductor 300b and the conductor layers 301 and 302 are formed.

Specifically, as shown in FIG. 9, for example, using a CO ₂ laser, a hole 1003 is formed by irradiating the double-sided copper-clad laminate 1000 with a laser from the first surface F1 side, and a laser is emitted from the second surface F2 side. Is formed on the double-sided copper-clad laminate 1000 to form a hole 1004. The shape of the hole 1003 corresponds to the first conductor portion R11 (see FIGS. 2A and 2B), and the shape of the hole 1004 corresponds to the second conductor portion R12 (see FIGS. 2A and 2B). The hole 1003 and the hole 1004 are formed at substantially the same position in the XY plane and are finally connected to form a through hole 300a penetrating the double-sided copper-clad laminate 1000. The shape of the through hole 300a corresponds to the through hole conductor 300b (see FIGS. 2A and 2B), and has an hourglass shape (a drum shape). The boundary between the hole 1003 and the hole 1004 corresponds to the constricted portion 300c (see FIGS. 2A and 2B). The laser irradiation on the first surface F1 and the laser irradiation on the second surface F2 may be performed simultaneously or one surface at a time. After the through hole 300a is formed, it is preferable to perform desmearing on the through hole 300a. Undesirable conduction (short circuit) is suppressed by desmear. Further, the surface of the copper foils 1001 and 1002 may be blackened prior to laser irradiation in order to increase the absorption efficiency of laser light. The through hole 300a may be formed by a method other than laser, such as drilling or etching. However, fine processing is easy with laser processing. In particular, when the thermal expansion coefficient of the substrate 100 is small, drilling becomes difficult, so laser processing is effective.

Subsequently, for example, a copper plating 1005 is formed on the copper foils 1001 and 1002 and in the through hole 300a as shown in FIG. Specifically, first, electroless plating is performed, and then plating 1005 is formed by performing electrolytic plating using the electroless plating film as a seed layer using a plating solution. Thereby, the through hole 300a is filled with the plating 1005, and the through hole conductor 300b is formed.

Subsequently, patterning of each conductor layer formed on the first surface F1 and the second surface F2 of the substrate 100 is performed using, for example, an etching resist and an etching solution. Specifically, each conductor layer is covered with an etching resist having a pattern corresponding to the conductor layers 301 and 302, and a portion of each conductor layer that is not covered with the etching resist (part exposed at the opening of the etching resist) Remove by etching. Thus, as shown in FIG. 11, conductor layers 301 and 302 are formed on the first surface F1 and the second surface F2 of the substrate 100, respectively. Note that the etching is not limited to wet, and may be dry.

In this embodiment, as shown in FIG. 12A, the conductor layer 301 is not formed on the substrate 100 in the region R100 corresponding to the cavity R10. When the conductor layer 301 has such a conductor pattern, the position and shape of the cavity R10 are clarified, so that laser irradiation alignment for forming the cavity R10 is facilitated in the subsequent process (step S13 in FIG. 7). .

However, the conductor pattern of the conductor layer 301 is not limited to the pattern shown in FIG. 12A. For example, as shown in FIG. 12B, the conductor layer 301 may not be formed only on a portion (hereinafter referred to as a laser irradiation path) on the substrate 100 where the laser is irradiated in the subsequent process (step S13 in FIG. 7). . In this case, the conductor layer 301 exists inside the laser irradiation path. Even with such a conductor layer 301, alignment of laser irradiation for forming the cavity R10 is facilitated.

In this embodiment, as shown in FIG. 12A, the conductor layer 301 has an alignment mark 301a. The alignment mark 301a is a pattern that can be optically recognized in a later process (step S14 in FIG. 7), for example, and can be formed by partially removing the conductor, for example, by etching or the like. In the present embodiment, alignment marks 301a are arranged around the region R100 (for example, four corners). However, the present invention is not limited to this, and the arrangement and shape of the alignment mark 301a are arbitrary.

Subsequently, in step S13 of FIG. 7, a cavity R10 is formed in the substrate 100 (core substrate). In the present embodiment, as shown in FIG. 13, the cavity R10 is formed by irradiating the substrate 100 with a laser. Specifically, for example, as shown in FIG. 12A, the region R100 corresponding to the cavity R10 in the substrate 100 is cut out from the surrounding portion by irradiating the laser so as to draw a square. The laser irradiation angle is set to be substantially perpendicular to the first surface F1 of the substrate 100, for example. As a result, a cavity R10 is formed as shown in FIG. In this embodiment, since the cavity R10 is formed by a laser, the cavity R10 can be easily obtained. The cavity R10 is a space for accommodating the electronic component 200.

Subsequently, the electronic component 200 is placed in the cavity R10 of the substrate 100 in step S14 of FIG.

Specifically, as shown in FIG. 15, a carrier 1006 made of, for example, PET (polyethylene terephthalate) is provided on one side (for example, the second surface F2) of the substrate 100. Thereby, one opening of the cavity R10 (hole) is closed by the carrier 1006. In this embodiment, the carrier 1006 is made of an adhesive sheet (for example, a tape) and has adhesiveness on the substrate 100 side. The carrier 1006 is bonded to the substrate 100 by lamination, for example.

Subsequently, as shown in FIG. 16, the electronic component 200 is inserted into the cavity R10 from the opposite side (Z1 side) to the opening where the cavity R10 (hole) is blocked. The electronic component 200 is inserted into the cavity R10 by a component mounting machine, for example. For example, the electronic component 200 is held by a vacuum chuck or the like, conveyed to the upper side (Z1 side) of the cavity R10, and then descends along the vertical direction, and is put into the cavity R10. Thereby, as shown in FIG. 17, the electronic component 200 is arrange | positioned on the carrier 1006 (adhesive sheet). When positioning the electronic component 200, it is preferable to use an alignment mark 301a (see FIGS. 12A and 12B). By doing so, it is considered possible to increase the accuracy of alignment between the electronic component 200 and the cavity R10.

In the present embodiment, the surfaces of the

electrodes

210 and 220 and the conductor layers 301 and 302 of the electronic component 200 are not roughened. However, it may be roughened by etching or the like as necessary.

Subsequently, in step S15 of FIG. 7, as shown in FIG. 18, in the semi-cured state, the first surface of the substrate 100 opposite to the opening where the cavity R10 (hole) is blocked (Z1 side). An insulating layer 101 (first interlayer insulating layer) is disposed on F1 and the third surface F3 of the electronic component 200. Further, a copper foil 111 (first copper foil) is disposed on the insulating layer 101. The insulating layer 101 is made of, for example, a glass prepreg. Subsequently, as shown in FIG. 19A, by pressing the insulating layer 101 in a semi-cured state, the resin flows out from the insulating layer 101 and flows into the cavity R10. As a result, as shown in FIG. 19B, a gap R1 between the substrate 100 and the electronic component 200 in the cavity R10 is filled with the insulator 101a (resin constituting the insulating layer 101). At this time, if the gap between the substrate 100 and the electronic component 200 is narrow, even if the fixing of the electronic component 200 is weak, the resin flows into the cavity R10 and the electronic component 200 is less likely to be displaced or undesirably tilted. . Note that the insulator 101 a has a larger thermal expansion coefficient than both the substrate 100 and the electronic component 200.

Once the cavity R10 is filled with the insulator 101a, the filling resin (insulator 101a) and the electronic component 200 are temporarily welded. Specifically, the holding resin has such a degree that the electronic component 200 can be supported by the filling resin by heating. As a result, the electronic component 200 supported by the carrier 1006 is supported by the filling resin. Thereafter, the carrier 1006 is removed.

At this stage, the insulator 101a (filling resin) and the insulating layer 101 are only semi-cured and not completely cured. However, the invention is not limited to this. For example, the insulator 101a and the insulating layer 101 may be completely cured at this stage.

Subsequently, build-up is performed on the second surface F2 side of the substrate 100 in step S16 of FIG.

Specifically, as shown in FIG. 20, an insulating layer 102 (second interlayer insulating layer) and a copper foil 121 (second copper foil) are disposed on the second surface F2 of the substrate 100. The insulating layer 102 is made of, for example, a glass prepreg. Subsequently, the insulating layer 102 is bonded to the substrate 100 and the electronic component 200 in a semi-cured state by pressing, for example, and then heated to cure each of the insulating

layers

101 and 102. In this embodiment, since the resin filled in the cavity R10 is cured after removing the adhesive sheet (carrier 1006), the insulating

layers

101 and 102 can be cured simultaneously. Then, by simultaneously curing the insulating

layers

101 and 102 on both sides, warpage of the substrate 100 is suppressed, so that the substrate 100 can be easily thinned.

In subsequent step S17 of FIG. 7, via conductors and conductor layers are formed.

Specifically, as shown in FIG. 21,

holes

311a and 312a (respectively via holes) are formed in the insulating layer 101 and the copper foil 111 by, for example, laser, and

holes

321a and 322a (respectively via holes) are formed in the insulating layer 102 and the copper foil 121. Form. Each of the

holes

311 a and 312 a penetrates the insulating layer 101 and the copper foil 111, and each of the

holes

321 a and 322 a penetrates the insulating layer 102 and the copper foil 121. Each of the

holes

311a and 321a reaches the

electrode

210 or 220 of the electronic component 200, and each of the

holes

312a and 322a reaches just above the through-hole conductor 300b. Then, desmear is performed as needed.

Subsequently, as shown in FIG. 22A, for example, copper electroless plating

films

1007 and 1008 are formed on the copper foils 111 and 121 and in the

holes

311a, 312a, 321a and 322a by, for example, chemical plating. Prior to electroless plating, a catalyst made of palladium or the like may be adsorbed on the surfaces of the insulating

layers

101 and 102, for example, by dipping.

Subsequently, as shown in FIG. 22B, a plating resist 1009 having an opening 1009a is formed on the main surface (on the electroless plating film 1007) on the first surface F1 side by the lithography technique or printing, and the second surface. A plating resist 1010 having an opening 1010a is formed on the main surface on the F2 side (on the electroless plating film 1008). The

openings

1009a and 1010a have patterns corresponding to the conductor layers 110 and 120 (FIG. 1), respectively.

Subsequently, as shown in FIG. 22C, for example, copper

electrolytic plating

1011 and 1012 are formed in the

openings

1009a and 1010a of the plating resists 1009 and 1010, for example, by pattern plating. Specifically, copper that is a material to be plated is connected to the anode, and

electroless plating films

1007 and 1008 that are materials to be plated are connected to the cathode and immersed in a plating solution. Then, a direct current voltage is applied between the two electrodes to pass a current, and copper is deposited on the surfaces of the

electroless plating films

1007 and 1008. As a result, the

holes

311a and 312a and the

holes

321a and 322a are filled with the

electrolytic plating

1011 and 1012, respectively, and via

conductors

311b, 312b, 321b, and 322b made of, for example, copper plating are formed.

Thereafter, the plating resists 1009 and 1010 are removed by, for example, a predetermined stripping solution, and then the unnecessary

electroless plating films

1007 and 1008 and the copper foils 111 and 121 are removed, as shown in FIG. 110 and 120 are formed.

Note that the seed layer for electrolytic plating is not limited to the electroless plating film, and a sputtered film or the like may be used as the seed layer instead of the

electroless plating films

1007 and 1008.

Subsequently, in step S18 of FIG. 7, a solder resist 11 having an opening 11a and a solder resist 12 having an opening 12a are formed on the insulating

layers

101 and 102, respectively (see FIG. 1). The conductor layers 110 and 120 are covered with the solder resists 11 and 12 except for predetermined portions (pads P1 and P2 and lands, etc.) located in the

openings

11a and 12a, respectively. The solder resists 11 and 12 can be formed by, for example, screen printing, spray coating, roll coating, or lamination.

Subsequently, by electrolytic plating or sputtering, the corrosion resistance made of, for example, a Ni / Au film on the conductor layers 110 and 120, specifically on the surfaces of the pads P1 and P2 (see FIG. 1) not covered with the solder resists 11 and 12, respectively. Form a layer. Moreover, you may form the corrosion-resistant layer which consists of an organic protective film by performing OSP process.

Thus, the first buildup part B1 composed of the insulating layer 101 and the conductor layer 110 is formed on the first surface F1 of the substrate 100, and the insulating layer 102 and the conductor layer 120 are formed on the second surface F2 of the substrate 100. A second buildup part B2 composed of As a result, the wiring board 10 (FIG. 1) of this embodiment is completed. Thereafter, if necessary, an electrical test (checking of capacitance value, insulation, etc.) of the electronic component 200 is performed.

The manufacturing method of the present embodiment is suitable for manufacturing the wiring board 10. With such a manufacturing method, it is considered that a good wiring board 10 can be obtained at low cost.

The wiring board 10 of this embodiment can be electrically connected to, for example, an electronic component or another wiring board. For example, as shown in FIG. 24, an electronic component 400 (for example, an IC chip) can be mounted on the pad P2 of the wiring board 10 by solder or the like. Further, the wiring board 10 can be mounted on another wiring board 500 (for example, a mother board) by the pad P1. The wiring board 10 of this embodiment can be used as a circuit board of a mobile phone, for example.

(Embodiment 2)
The wiring board 20 according to the second embodiment is a wiring board with a built-in electronic component, and includes a substrate 100, insulating

layers

101 and 102, conductor layers 110 and 120, and an electronic component 200 as shown in FIG. . In addition, the wiring board 20 of this embodiment is a rigid wiring board. However, the wiring board 20 may be a flexible wiring board.

The substrate 100 has an insulating property and becomes a core substrate of the wiring board 20. Hereinafter, one of the front and back surfaces (two main surfaces) of the substrate 100 is referred to as a first surface F1, and the other is referred to as a second surface F2.

The electronic component 200 is built in the wiring board 20. Hereinafter, one of the front and back surfaces (two main surfaces) of the electronic component 200 is referred to as a third surface F3, and the other is referred to as a fourth surface F4.

A cavity R10 (opening) is formed in the substrate 100, and the electronic component 200 is accommodated in the cavity R10. FIG. 26 shows a state where the electronic component 200 is accommodated in the cavity R10 of the substrate 100 (core substrate).

The cavity R10 is formed of a partially tapered hole and penetrates the substrate 100. The shape of the wide side (Z1 side) opening (hereinafter referred to as the first opening) and the shape of the narrow side (Z2 side) opening (hereinafter referred to as the second opening) of the cavity R10 are substantially rectangular. Here, the shape of the second opening corresponds to the shape of the region surrounded by the side surface F10 of the substrate 100 facing the cavity R10 (the inner wall of the cavity R10). The electronic component 200 is a chip having an outer shape (for example, a similar shape having substantially the same size) corresponding to the shape of the second opening of the cavity R10, for example. The thickness of the electronic component 200 and the depth of the cavity R10 (hole) are: It almost agrees. Further, the thickness of the substrate 100 and the thickness of the electronic component 200 are substantially the same.

As shown in FIG. 26, in both the X direction and the Y direction, the width of the electronic component 200 is smaller than the width of the second opening of the cavity R10, and a predetermined size is required to accommodate the electronic component 200 in the cavity R10. Clearance is secured. The clearance is obtained by subtracting the width of the electronic component 200 from the width of the second opening of the cavity R10. It is considered preferable that the clearances in the X direction and the Y direction are each in the range of about 0 μm to about 142 μm. About 142 μm is a value in consideration of mounting accuracy and component outline accuracy.

The electronic component 200 is arranged in the cavity R10 with the third surface F3 in the same direction as the first surface F1 of the substrate 100. The electronic component 200 is located in the side (X direction or Y direction) of the substrate 100 by being disposed in the cavity R10. In the present embodiment, substantially the entire electronic component 200 is completely accommodated in the cavity R10. However, the present invention is not limited to this, and only a part of the electronic component 200 may be disposed in the cavity R10. In the present embodiment, the insulator 101a is filled in the gap between the electronic component 200 and the substrate 100 in the cavity R10. The insulator 101a is made of, for example, only a resin constituting the upper insulating layer 101 (resin insulating layer) (see FIG. 40A). However, the present invention is not limited thereto, and instead of or in addition to the resin constituting the insulating layer 101, a material (for example, resin) constituting the substrate 100 or the insulating layer 102 may be filled, or a separately prepared insulating material is used. It may be filled. In the present embodiment, the insulator 101a completely covers the periphery of the electronic component 200. Thereby, the electronic component 200 is protected by the insulator 101a (resin) and fixed at a predetermined position.

The insulating layer 101 is formed on the first surface F1 of the substrate 100 and the third surface F3 of the electronic component 200. The insulating layer 102 is formed on the second surface F2 of the substrate 100 and the fourth surface F4 of the electronic component 200. The cavity R10 includes a hole penetrating the substrate 100. The insulating layer 101 closes one opening of the cavity R10 (hole), and the insulating layer 102 closes the other opening of the cavity R10 (hole). The conductor layer 110 is formed on the insulating layer 101, and the conductor layer 120 is formed on the insulating layer 102. In the present embodiment, the conductor layers 110 and 120 are the outermost layers. However, the present invention is not limited to this, and more interlayer insulating layers and conductor layers may be stacked.

A hole 321 a (via hole) is formed in the insulating layer 102. By filling the hole 321a with a conductor (for example, copper plating), the conductor in the hole 321a becomes a via conductor 321b (filled conductor). The hole 321 a reaches the

electrodes

210 and 220 of the electronic component 200, and the via conductor 321 b in the hole 321 a is electrically connected to the

electrodes

210 and 220. The

electrodes

210 and 220 of the electronic component 200 and the conductor layer 120 on the insulating layer 102 are electrically connected to each other via the via conductor 321b.

The shapes of the substrate 100, the insulating

layers

101 and 102, and the electronic component 200 are, for example, rectangular plates. The shape of the main surface of the electronic component 200 is, for example, a substantially rectangular shape. However, it is not limited to this, and these shapes are arbitrary.

The substrate 100 is made of, for example, a glass cloth (core material) impregnated with an epoxy resin (hereinafter referred to as glass epoxy). The core material is a material having a smaller coefficient of thermal expansion than the main material (in the present embodiment, epoxy resin). As a core material, it is thought that inorganic materials, such as glass fiber (for example, glass cloth or a glass nonwoven fabric), an aramid fiber (for example, an aramid nonwoven fabric), or a silica filler, are preferable, for example. However, the shape, thickness, material and the like of the substrate 100 are basically arbitrary. For example, polyester resin, bismaleimide triazine resin (BT resin), imide resin (polyimide), phenol resin, or allylated phenylene ether resin (A-PPE resin) may be used instead of epoxy resin. The substrate 100 may be composed of a plurality of layers made of different materials.

The insulating

layers

101 and 102 are made of, for example, an epoxy resin. In the present embodiment, the substrate 100 is made of a resin containing a core material, and the insulating

layers

101 and 102 are made of a resin not containing a core material. However, the present invention is not limited to this, and the shape, thickness, material, and the like of the insulating

layers

101 and 102 are basically arbitrary. For example, polyester resin, bismaleimide triazine resin (BT resin), imide resin (polyimide), phenol resin, or allylated phenylene ether resin (A-PPE resin) may be used instead of epoxy resin. Each insulating layer may be composed of a plurality of layers made of different materials.

The via conductor 321b is made of, for example, copper plating. The shape of the via conductor 321b is, for example, a tapered cylinder (conical frustum) tapered so as to increase in diameter from the substrate 100 (core substrate) toward the upper layer, and the shape of the cross section (XY plane) of the via conductor is For example, it is a substantially perfect circle. However, it is not limited to this, and the shape of the via conductor is arbitrary.

The conductor layer 110 is composed of a copper foil 111 (lower layer) and a copper plating 112 (upper layer), and the conductor layer 120 is composed of a copper foil 121 (lower layer) and a copper plating 122 (upper layer). . The conductor layers 110 and 120 have, for example, wiring that forms an electric circuit (for example, an electric circuit including the electronic component 200), a solid pattern for increasing the strength of the wiring board 20, and the like.

(However, the material of the conductor layer and the via conductor is not limited to this, and is arbitrary. Each conductor layer and each via conductor may be composed of a plurality of layers made of different materials.

The electronic component 200 is, for example, a chip capacitor. The electronic component 200 has, for example, a rectangular plate-shaped outer shape with a thickness in the range of about 50 μm to about 300 μm and a length of each side in the range of about 0.5 mm to about 2 mm. The shape of the main surface (the third surface F3 and the fourth surface F4) of the electronic component 200 is, for example, a substantially rectangular shape. However, the present invention is not limited to this, and the type, shape, size, and the like of the electronic component 200 are arbitrary.

The electronic component 200 includes a capacitor main body 201 and

U-shaped electrodes

210 and 220 as shown in FIG. The capacitor body 201 includes a plurality of dielectric layers 231 to 239 and a plurality of conductor layers 211 to 214 and 221 to 224 that are alternately stacked. Each of the dielectric layers 231 to 239 is made of, for example, ceramic. The

electrodes

210 and 220 are formed at both ends of the capacitor body 201, respectively. Thus, both ends of the capacitor body 201, specifically, the fourth surface F4 (lower surface), the side surface, and the third surface F3 (upper surface) are covered with the

electrodes

210 and 220.

Here, as shown in FIG. 26, the central portion of the capacitor body 201 located between the

electrodes

210 and 220 is not covered with the

electrodes

210 and 220, and the dielectric layers 231 and 239 (ceramic) are exposed. Therefore, the strength is relatively weak. However, in a state where the electronic component 200 is mounted (built in) the wiring board 20, the central portion of the capacitor body 201 is covered with the insulator 101a (resin). As a result, it is considered that the capacitor body 201 is protected by the insulator 101a.

In the wiring board 20 of the present embodiment, the substrate 100 is directed from the first surface F1 to the second surface F2 at the corner between the side surface F10 of the substrate 100 facing the cavity R10 (the inner wall of the cavity R10) and the first surface F1. A tapered surface C11 is provided to reduce the width of the cavity R10.

As shown in FIG. 28, the substrate 100 includes a first layer 100a and a second layer 100b made of different materials. The first layer 100a and the second layer 100b are arranged in this order from the first surface F1 toward the second surface F2. That is, the second layer 100b is formed on the first layer 100a. In the present embodiment, the first layer 100a and the second layer 100b are each composed of the same resin (for example, epoxy resin), and the second layer 100b includes an inorganic material (for example, glass cloth). 100a does not include an inorganic material.

Here, the side surface F10 of the substrate 100 facing the cavity R10 corresponds to the side surface of the second layer 100b, the first surface F1 of the substrate 100 corresponds to the main surface of the first layer 100a, and the side surface F10 and the first surface. The tapered surface C11 located at the corner with F1 corresponds to the side surface of the first layer 100a.

In this embodiment, in FIG. 28, the angle θ1 between the side surface F10 of the substrate 100 facing the cavity R10 and the second surface F2 is about 90 °. That is, the side surface F10 (the inner wall of the cavity R10) is a surface substantially perpendicular to the second surface F2.

The tapered surface C11 is a flat surface (slope) inclined with respect to the first surface F1 of the substrate 100, as shown in FIG. The angle between the first surface F1 of the substrate 100 and the tapered surface C11 (hereinafter referred to as the taper angle θ2) is an angle larger than at least 90 °, preferably in the range of about 120 ° to about 150 °, It is considered particularly preferable that the angle is 135 °. The larger the taper angle θ2, the greater the reduction ratio of the cavity R10.

The tapered surface C11 is formed on the entire peripheral edge (four sides) of the cavity R10, for example, as shown in FIG. However, the present invention is not limited to this, and the tapered surface C11 may be partially formed on the peripheral edge of the cavity R10 (see FIG. 53 described later). In the present embodiment, the widths D11 and D12 of the tapered surface C11 are substantially uniform. That is, the width D11 in the X direction and the width D12 in the Y direction are substantially the same, for example. However, the present invention is not limited to this, and the width D11 in the X direction and the width D12 in the Y direction may be different sizes.

The dimensions and shape of the tapered surface C11 are not limited to those described above, and are arbitrary. The tapered surface C11 may be anything that reduces the width of the cavity R10 from the first surface F1 toward the second surface F2. For example, as illustrated in FIG. 29A, the tapered surface C11 may be a curved surface that decreases in width reduction rate from the first surface F1 toward the second surface F2. For example, as illustrated in FIG. 29B, the tapered surface C11 may be a curved surface having a reduced width ratio that increases from the first surface F1 toward the second surface F2.

In FIG. 26, the width D3 indicates the maximum value of the gap in the X direction between the substrate 100 and the electronic component 200 (the larger of the gap on the X1 side and the gap on the X2 side), and the width D4 indicates the width of the substrate 100 and the electronic component. The maximum value of the gap in the Y direction with respect to 200 (the larger of the gap on the Y1 side and the gap on the Y2 side) is shown. The width D3 or D4 (more preferably both) is preferably in the range of about 0 μm to about 100 μm, and in particular, it is considered particularly preferable to be in the range of about 0 μm to about 5 μm. When the width D3 or D4 is about 100 μm or less (particularly about 5 μm or less), the gap in which the electronic component 200 can move in the cavity R10 is reduced, and the positional accuracy of the electronic component 200 is increased. As a result, the alignment accuracy between the electronic component 200 and the via conductor 321b is also improved. Further, it becomes easy to secure a region for forming wiring (conductor layers 301 and 302 shown in FIG. 42 described later) on the substrate 100. In addition, the flatness of the insulating layers (insulating layers 101 and 102) formed over the substrate 100 can be easily increased.

It is considered that the side surface F10 (the inner wall of the cavity R10) of the substrate 100 facing the cavity R10 is preferably formed by a laser cut surface. If it is a cut surface by a laser, it tends to be a smooth surface. Further, by cutting a predetermined portion (a portion corresponding to the cavity R10) of the substrate 100 with a laser, the tapered surface C11 can be easily formed together with the cavity R10.

27. As shown in FIGS. 27 and 30A, the electronic component 200 has a curved surface C21 at the corner between the side surface F20 and the fourth surface F4. Each of the corners of the capacitor body 201 is composed of two planes that intersect at right angles and does not have a curved surface, but the side surface F20 and the fourth surface of the electronic component 200 are covered by the

electrode

210 or 220 that covers the surface of the capacitor body 201. A curved surface C21 is formed at the corner with F4.

The curved surface C21 is formed by the surface of the

electrode

210 or 220 of the electronic component 200. If the curved surface C21 is as strong as the electrode material, it is considered that the performance degradation of the electronic component 200 hardly occurs even when the curved surface C21 hits the tapered surface C11 when the electronic component 200 is put into the cavity R10.

It is considered that at least the surfaces of the

electrodes

210 and 220 of the electronic component 200 are each preferably made of a plating film. If the plating conditions are adjusted, it is considered that a desired curved surface C21 can be easily obtained on the surface of the capacitor body 201 even when the corner of the capacitor body 201 does not have a curved surface. Further, it becomes easy to form a smooth curved surface C21. If the smooth curved surface C21 is obtained, the electronic component 200 can easily slide on the curved surface C21. The radius of curvature of the curved surface C21 is preferably in the range of about 20 μm to about 40 μm, and it is considered that about 30 μm is particularly preferable. In the present embodiment, each of the corners of the capacitor body 201 is constituted by a plane that intersects at right angles. However, the present invention is not limited to this, and the corner of the capacitor body 201 may have a curved surface.

In the present embodiment, as shown in FIG. 26, a curved surface C21 is formed at a portion where the

electrodes

210 and 220 are provided among the corners of the four side surfaces F20 and the fourth surface F4 of the electronic component 200. . However, it is not limited to this, and the form of the curved surface C21 is arbitrary. In the present embodiment, the widths D21 and D22 of the curved surface C21 are substantially uniform. That is, the width D21 in the X direction and the width D22 in the Y direction are substantially the same, for example. It is believed that widths D21 and D22 are each preferably in the range of about 0 μm to about 71 μm. About 71 μm is a value in consideration of mounting accuracy and component outline accuracy. However, the present invention is not limited to this, and the width D11 in the X direction and the width D12 in the Y direction may be different sizes.

30A, in this embodiment, the boundary P21 between the curved surface C21 and the side surface F20 of the electronic component 200 is located on the inner side of the lower surface F21 of the capacitor body 201. In addition, a boundary P 22 between the curved surface C 21 and the fourth surface F 4 (lower surface) of the electronic component 200 is positioned outside the side surface F 22 of the capacitor main body 201. However, the present invention is not limited to this, and as shown in FIG. 30B, the boundary P21 may be located outside the lower surface F21, and the boundary P22 may be located outside the side surface F22. In addition, as illustrated in FIG. 30C, the boundary P21 may be located outside the lower surface F21, and the boundary P22 may be located inside the side surface F22.

27. As shown in FIG. 27, the electronic component 200 of the present embodiment has a curved surface C22 at the corner between the side surface F20 and the third surface F3. The curved surface C22 has the same shape as the curved surface C21, for example. However, the present invention is not limited to this. For example, at the corner between the side surface F20 and the third surface F3, the side surface F20 and the third surface F3 (planes) may be perpendicular to each other without a curved surface.

In FIG. 30A, it is considered that the thickness D23 on the side surface F20 side of the

electrodes

210 and 220 is preferably in the range of about 5 μm to about 30 μm. In addition, it is considered that the thickness D24 on the fourth surface F4 side of the

electrodes

210 and 220 is preferably in the range of about 5 μm to about 30 μm.

As described above, the wiring board 20 of the present embodiment includes the substrate 100 on which the cavity R10 is formed and the electronic component 200 that is disposed in the cavity R10 with the third surface F3 in the same direction as the first surface F1 of the substrate 100. And having. The electronic component 200 has a curved surface C21 at the corner between the side surface F20 and the fourth surface F4. Further, the substrate 100 has a tapered surface C11 that reduces the width of the cavity R10 from the first surface F1 toward the second surface F2 at the corner between the side surface F10 (the inner wall of the cavity R10) facing the cavity R10 and the first surface F1. Have. Such a structure makes it easy to put the electronic component 200 into the cavity R10. In addition, it is possible to easily align the electronic component 200 and the via conductor 321b. Moreover, it becomes possible to suppress the crack of the electronic component 200.

Hereinafter, a method for manufacturing the wiring board 20 will be described with reference to FIG. FIG. 31 is a flowchart showing a schematic content and procedure of the method for manufacturing the wiring board 20 according to the present embodiment.

In step S21, a substrate 100 (starting material) is prepared as shown in FIG. The substrate 100 is made of, for example, a completely cured glass epoxy.

Subsequently, in step S22 of FIG. 31, a cavity R10 (FIGS. 25 and 26) is formed in the substrate 100. FIG.

Specifically, for example, as shown in FIG. 33, the region R100 corresponding to the cavity R10 in the substrate 100 is cut out from the surrounding portion by irradiating a laser so as to draw a square. At this time, as shown in FIG. 34, the laser is applied to the first surface F1 of the substrate 100 so as to penetrate the first layer 100a and reach the second layer 100b. The laser irradiation angle is set to be substantially perpendicular to the first surface F1 of the substrate 100, for example. In the present embodiment, since the second layer 100b includes an inorganic material and the first layer 100a does not include an inorganic material, the first layer 100a is dissolved in the X direction and the Y direction by laser irradiation. Thus, the tapered surface C11 is obtained, and in the second layer 100b, the dissolution in the X direction and the Y direction hardly proceeds, and the side surface F10 (the inner wall of the cavity R10) substantially along the Z direction is obtained. For this reason, the taper surface C11 can be easily formed at the corner between the side surface F10 of the substrate 100 facing the cavity R10 and the first surface F1.

The cavity R10 is formed in the substrate 100 by the laser processing as shown in FIG. 35A. The cavity R 10 is a hole that penetrates the substrate 100. The tapered surface C11 is located at a corner between the first surface F1 and the side surface F10 (inner wall of the cavity R10) of the substrate 100 facing the cavity R10, and reduces the width of the cavity R10 from the first surface F1 toward the second surface F2. . In this embodiment, since the cavity R10 is formed by a laser, the cavity R10 having the above-described structure (see FIG. 28) can be easily obtained. The cavity R10 is a space for accommodating the electronic component 200.

Subsequently, in step S23 of FIG. 31, the electronic component 200 having the curved corner (the corner having the curved surface C21) is arranged in the cavity R10 of the substrate 100.

Specifically, as shown in FIG. 35B, a carrier 2001 made of, for example, PET (polyethylene terephthalate) is provided on one side (for example, the second surface F2) of the substrate 100. Thereby, one opening of the cavity R10 (hole) is closed by the carrier 2001. In the present embodiment, the carrier 2001 is made of an adhesive sheet (for example, a tape) and has adhesiveness on the substrate 100 side. The carrier 2001 is bonded to the substrate 100 by lamination, for example.

Subsequently, as shown in FIG. 35C, an electronic component 200 having a curved surface C21 at the corner between the fourth surface F4 and the side surface F20 is prepared. The curved surface C21 is composed of the surfaces of the

electrodes

210 and 220 of the electronic component 200. The

electrodes

210 and 220 of the electronic component 200 are each made of a plating film.

Subsequently, the electronic component 200 is placed on the carrier 2001 (adhesive sheet) by inserting the electronic component 200 into the cavity R10 from the opposite side (Z1 side) to the opening where the cavity R10 (hole) is blocked.

The electronic component 200 is inserted into the cavity R10 by, for example, a component mounter (mounter). For example, the electronic component 200 is held by a vacuum chuck or the like and, as shown in FIG. 36A, is carried upward (Z1 side) of the cavity R10, and then descends along the vertical direction and is put into the cavity R10. When the electronic component 200 is placed in the cavity R10, the curved corner (curved surface C21) of the electronic component 200 faces the substrate 100. When the alignment between the electronic component 200 and the cavity R10 is slightly shifted due to variations in component mounting accuracy, etc., as shown in FIG. 36B, the tapered surface C11 of the substrate 100 and the curved surface C21 of the electronic component 200 come into contact with each other. The electronic component 200 is guided to the cavity R10 while sliding on the tapered surface C11 while the tapered surface C11 and the curved surface C21 are in contact with each other, and is housed in the cavity R10 of the substrate 100 and stabilized as shown in FIG. 36C. . In FIGS. 36A to 36C, the Z direction corresponds to the vertical direction. The operation of inserting the electronic component 200 may be performed by a person or may be performed by an apparatus. Further, the electronic component 200 may be placed in the cavity R10 by dropping the electronic component 200 toward the cavity R10 using gravity.

In the present embodiment, when the electronic component 200 and the substrate 100 collide with each other, the tapered surface C11 and the curved surface C21 are not contacted by the tapered surface C11 and the right-angled corner (an angle formed by two planes intersecting substantially at right angles). Therefore, it is considered that the impact on the electronic component 200 is suppressed and the electronic component 200 is hardly cracked.

In this embodiment, the electronic component 200 is disposed in the cavity R10 while the curved surface C21 of the electronic component 200 is in contact with the tapered surface C11 of the substrate 100. For this reason, the electronic component 200 is guided to the cavity R10 by sliding on the tapered surface C11, and the electronic component 200 is arranged in the cavity R10 of the substrate 100 even if the alignment between the electronic component 200 and the cavity R10 is slightly shifted. become. In addition, even a small pressure can be accommodated while sliding.

Also, since the alignment between the electronic component 200 and the cavity R10 is facilitated, the clearance between the cavity R10 and the electronic component 200, and thus the gap (width D3, D4) between the substrate 100 and the electronic component 200 can be easily reduced. It has been confirmed by the inventors that this point is significantly improved.

Further, by narrowing the gap (width D3, D4) between the substrate 100 and the electronic component 200, the positional accuracy of the electronic component 200 is increased. As a result, the alignment accuracy between the electronic component 200 and the via conductor 321b is also improved.

In addition, since the curved surface C21 is composed of the surfaces of the electrodes 210 and 220 (plating film), the electronic component 200 is easily slid on the curved surface C21. Thereby, it is considered that the impact on the electronic component 200 is suppressed, and the electronic component 200 is hardly cracked.

Hereinafter, with reference to FIGS. 37A to 37C, the difference in the action of the tapered surface C11 based on the difference in the taper angle θ2 will be described. The taper angle θ2 is the largest in the substrate 100 shown in FIG. 37C, next the largest in the substrate 100 shown in FIG. 37A, and the smallest in the substrate 100 shown in FIG. 37B.

As shown in FIGS. 37A to 37C, as the taper angle θ2 decreases, the force for guiding the electronic component 200 to the cavity R10 increases. Further, as the taper angle θ2 increases, the width D11 or D12 of the tapered surface C11 is easily increased, and thus the electronic component 200 is more likely to fall on the tapered surface C11.

In view of these points, the taper angle θ2 is preferably in the range of about 120 ° to about 150 °, and is considered to be particularly preferably about 135 °. With such a taper angle θ2, a sufficient force is obtained to guide the electronic component 200 to the cavity R10, and a sufficient width D11 or D12 of the tapered surface C11 is required to align the electronic component 200 and the cavity R10. Is obtained.

38, the electronic component 200 is arranged in the cavity R10 with the third surface F3 in the same direction as the first surface F1 of the substrate 100 (all in the direction of Z1). The electronic component 200 is placed on the carrier 2001 and fixed (temporarily fixed) by the adhesiveness of the carrier 2001. By placing the electronic component 200 on the carrier 2001, the inclination of the electronic component 200 can be easily leveled.

Subsequently, in step S24 of FIG. 31, as shown in FIG. 39A, the insulating layer 101 is semi-cured and the substrate on the side opposite to the opening where the cavity R10 (hole) is blocked (Z1 side) It is formed on 100 and the electronic component 200. Further, a copper foil 2003 is formed on the insulating layer 101. The insulating layer 101 is made of, for example, a prepreg of an epoxy resin having thermosetting properties. Subsequently, as shown in FIG. 39B, by pressing the insulating layer 101 in a semi-cured state, the resin flows out from the insulating layer 101 and flows into the cavity R10 as shown in FIG. 40A. Thereby, as shown in FIG. 40B, the insulator 101a (resin constituting the insulating layer 101) is filled between the substrate 100 and the electronic component 200 in the cavity R10. At this time, if the gap (width D3, D4) between the substrate 100 and the electronic component 200 is narrow, even if the fixing of the electronic component 200 is weak, the resin flows into the cavity R10, and the displacement of the electronic component 200, Undesirable tilt is unlikely to occur. Then, after the cavity 101 is filled with the insulator 101a, the filling resin (insulator 101a) and the electronic component 200 are temporarily welded. Specifically, the holding resin has such a degree that the electronic component 200 can be supported by the filling resin by heating. As a result, the electronic component 200 supported by the carrier 2001 is supported by the filling resin. Thereafter, the carrier 2001 is removed.

Subsequently, in step S25 of FIG. 31, each main surface is built up.

Specifically, as shown in FIG. 41A, the insulating layer 102 and the copper foil 2004 are formed on the second surface F2 of the substrate 100. The

electrodes

210 and 220 of the electronic component 200 are each covered with the insulating layer 102. For example, after the insulating layer 102 is bonded to the substrate 100 in a prepreg state by pressing, the insulating

layers

101 and 102 are cured by heating. In this embodiment, since the resin filled in the cavity R10 is cured after removing the adhesive sheet (carrier 2001), the insulating

layers

In the subsequent step S26 of FIG. 31, as shown in FIG. 41B, holes 321a (via holes) are formed in the insulating layer 102 and the copper foil 2004 by, for example, a laser. The hole 321 a passes through the insulating layer 102 and the copper foil 2004 and reaches the

electrode

210 or 220 of the electronic component 200. Then, desmear is performed as needed.

Subsequently, as shown in FIG. 41C, for example, a copper electroplating 2005 is formed on the copper foil 2003 by, for example, a panel plating method, and for example, the copper electroplating 2006 is formed on the copper foil 2004 and in the hole 321a. Form. The conductor in the hole 321a becomes the via conductor 321b. In addition, an electroless plating film may be formed between the copper foil 2003 and the electrolytic plating 2005 or between the copper foil 2004 and the electrolytic plating 2006 by performing the electroless plating prior to the electrolytic plating. .

Thereafter, in step S27 of FIG. 31, the

electroplating

2005 and 2006 are patterned by etching, for example, to form conductor layers 110 and 120, whereby the wiring board 20 (FIG. 25) of the present embodiment is completed. Thereafter, if necessary, an electrical test (checking of capacitance value, insulation, etc.) of the electronic component 200 is performed.

In the manufacturing method of the present embodiment, the substrate 100 is prepared (FIG. 32), the electronic component 200 having the curved surface C21 at the corner between the fourth surface F4 and the side surface F20 (FIG. 35C), and the substrate 100 is prepared. Forming a cavity R10 (FIG. 33, FIG. 34), and at the corner between the side surface F10 (inner wall of the cavity R10) of the substrate 100 facing the cavity R10 and the first surface F1, the first surface F1 to the second surface F2. Forming a tapered surface C11 that reduces the width of the cavity R10 toward the surface (FIGS. 33 and 34), and disposing the electronic component 200 in the cavity R10 with the third surface F3 in the same direction as the first surface F1 (see FIG. 33). 36A to 36C). According to such a manufacturing method, the electronic component 200 can be easily placed in the cavity R10. Further, the clearance between the cavity R10 and the electronic component 200 can be reduced. In addition, it is possible to easily align the electronic component 200 and the via conductor 321b. Moreover, it becomes possible to suppress the crack of the electronic component 200.

In the second embodiment, the tapered surface C11 is formed by laser processing. However, the tapered surface C11 can be obtained by other methods such as dry etching. However, it is considered that a particularly good tapered surface C11 can be obtained by laser processing. In addition, the first layer 100a and the second layer 100b of different materials can provide a good tapered surface C11 without using a special technique such as oblique laser irradiation.

(Embodiment 3)
The third embodiment of the present invention will be described focusing on the differences from the second embodiment. Here, the same elements as those shown in FIG. 25 and the like are denoted by the same reference numerals, and the description of common parts that have already been described, that is, parts that are duplicated, is omitted or simplified for convenience. We will make it.

In the wiring board 30 of the present embodiment, as shown in FIG. 42, through holes 300a are formed in the substrate 100 (core substrate), and a conductor (for example, copper plating) is filled in the through holes 300a. A conductor 300b is formed. The shape of the through-hole conductor 300b is, for example, a drum shape. However, the shape is not limited to this, and the shape of the through-hole conductor 300b is arbitrary, and may be, for example, a substantially cylindrical shape.

The conductor layer 301 is formed on the first surface F1 of the substrate 100, and the conductor layer 302 is formed on the second surface F2 of the substrate 100. Each of the conductor layers 301 and 302 includes a land of the through-hole conductor 300b.

Holes

311a and 312a (via holes) are formed in the insulating layer 101, and

holes

321a and 322a (via holes) are formed in the insulating layer 102. By filling the

holes

311a, 312a, 321a, and 322a with conductors (for example, copper plating), the conductors in the

holes

311a, 312a, 321a, and 322a are respectively via

conductors

311b, 312b, 321b, and 322b ( Filled conductor). The via

conductors

311b and 321b are electrically connected to the

electrodes

210 and 220 of the electronic component 200 from the first surface F1 side or the second surface F2 side of the substrate 100, respectively. Thus, in this embodiment, the electronic component 200 is connected to the via

conductors

311b and 321b from both sides. Hereinafter, this structure is referred to as a double-sided via structure.

The conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layer 302 on the second surface F2 of the substrate 100 are electrically connected to each other through the through-hole conductor 300b. The via

conductors

312b and 322b and the through-hole conductor 300b are all filled conductors and are stacked in the Z direction.

The conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layer 110 on the insulating layer 101 are electrically connected to each other through the via conductor 312b. Further, the conductor layer 302 on the second surface F2 of the substrate 100 and the conductor layer 120 on the insulating layer 102 are electrically connected to each other through the via conductor 322b.

The wiring board 30 according to the present embodiment is also manufactured in the procedure as shown in FIG. 31, for example, as in the second embodiment.

In step S21 of FIG. 31, a wiring board 3000 (starting material) is prepared as shown in FIG. In the present embodiment, the wiring board 3000 includes a substrate 100, a conductor layer 3001 formed on the first surface F1 of the substrate 100, a conductor layer 3002 formed on the second surface F2 of the substrate 100, and a through hole. And a conductor 300b. The substrate 100 is made of, for example, a completely cured glass epoxy. Each of the conductor layers 3001 and 3002 has a two-layer structure of, for example, copper foil (lower layer) and electrolytic copper plating (upper layer).

The drum-shaped through hole 300a can be formed, for example, by irradiating laser from both sides of the substrate 100 (double-sided copper-clad laminate) having copper foil formed on both sides. Then, in a state in which the copper foil is formed on the substrate 100 and the through hole 300a is formed in the substrate 100, for example, by performing copper electroplating, the conductor layers 3001, 3002 and the through hole conductor 300b are formed. Can be formed.

It is considered preferable to perform desmearing on the through hole 300a after the laser irradiation. Undesirable conduction (short circuit) is suppressed by desmear. In addition, it is considered preferable to roughen the surfaces of the conductor layers 3001 and 3002 by etching or the like as necessary.

In this embodiment, as shown in FIG. 44A, the conductor layer 3001 is not formed on the substrate 100 in the region R100 corresponding to the cavity R10. When the conductor layer 3001 has such a conductor pattern, the position and shape of the cavity R10 are clarified. Therefore, in the subsequent process (step S22 in FIG. 31), alignment of laser irradiation for forming the cavity R10 is facilitated. .

However, the conductor pattern of the conductor layer 3001 is not limited to the pattern shown in FIG. 44A. For example, as shown in FIG. 44B, the conductor layer 3001 may not be formed on the substrate 100 only in a portion (hereinafter referred to as a laser irradiation path) where laser irradiation is performed in a subsequent process (step S22 in FIG. 31). In this case, the conductor layer 3001 exists inside the laser irradiation path. Even with such a conductor layer 3001, alignment of laser irradiation for forming the cavity R10 is facilitated.

In this embodiment, as shown in FIG. 44A, the conductor layer 3001 has an alignment mark 301a. The alignment mark 301a is, for example, a pattern that can be optically recognized in a later process (step S23 in FIG. 31), and can be formed by partially removing the conductor, for example, by etching or the like. In the present embodiment, alignment marks 301a are arranged around the region R100 (for example, four corners). However, the present invention is not limited to this, and the arrangement and shape of the alignment mark 301a are arbitrary.

In this embodiment, the side surface F30 of the conductor layer 3001 is tapered as shown in FIG. It is considered preferable that the taper angle θ3 of the side surface F30 substantially matches the taper angle θ2 of the taper surface C11.

Subsequently, a cavity R10 is formed in the substrate 100 in step S22 of FIG. Specifically, for example, as shown in FIG. 44A, the region R100 corresponding to the cavity R10 in the substrate 100 is cut out from the surrounding portion by irradiating the laser so as to draw a square. At this time, as shown in FIG. 45, the laser is applied to the first surface F1 of the substrate 100 so as to penetrate the first layer 100a and reach the second layer 100b. The laser irradiation angle is set to be substantially perpendicular to the first surface F1 of the substrate 100, for example. When the side surface F30 of the conductor layer 3001 is tapered, the laser beam is reflected by the side surface F30 and proceeds obliquely, so that the tapered surface C11 is easily formed.

Thereafter, the wiring board 30 (FIG. 42) of this embodiment can be manufactured through steps S23 to S27 of FIG.

However, in this embodiment, the electronic component 200 is positioned using the alignment mark 301a in step S23 of FIG. Thereby, it is possible to increase the accuracy of alignment between the electronic component 200 and the cavity R10.

In step S26 of FIG. 31,

holes

311a, 312a, and 322a are formed in the same manner as hole 321a (see FIG. 41B), and then via

conductors

311b, 312b, and 322b are formed in the same manner as via conductor 321b. Form (see FIG. 41C).

The manufacturing method of the present embodiment is suitable for manufacturing the wiring board 30. With such a manufacturing method, a good wiring board 30 can be obtained at low cost.

With regard to the same configuration and processing as in the second embodiment, this embodiment can provide an effect similar to that of the second embodiment described above. For example, a preferable range of each dimension of the wiring board 30 according to the third embodiment is the same as that of the wiring board 20 according to the second embodiment. In addition, in terms of cost reduction and ease of manufacture, the wiring board 20 according to the second embodiment having a simple structure is considered preferable to the wiring board 30 according to the third embodiment. In terms of performance enhancement, the wiring board 30 according to the third embodiment having a double-sided via structure is considered preferable to the wiring board 20 according to the second embodiment.

(Other embodiments)
In the above embodiment, the through-hole conductor 300b has a symmetrical shape with respect to the reference plane F0, but the shape of the through-hole conductor 300b is not limited to this. As shown in FIG. 46, a through-hole conductor 300b having an asymmetric shape with respect to the reference plane F0 may be used. In the example of FIG. 46, the dimension T12 from the second surface F2 to the reference surface F0 is larger than the dimension T11 from the first surface F1 to the reference surface F0. In addition, regarding the dimensions of the through-hole conductor 300b, the width D31 of the first surface F1 side end surface, the width D32 of the constricted portion 300c, and the width D33 of the second surface F2 side end surface are, from the larger, the width D31 and the width D33. The width D32 is in this order. The side surface of the first conductor portion R11 is a curved surface, and the side surface of the second conductor portion R12 is a plane. The taper angle θ1 of the first conductor portion R11 is larger than the taper angle θ2 of the second conductor portion R12.

Hereinafter, an example of a method for manufacturing the through-hole conductor 300b shown in FIG. 46 will be described with reference to FIGS. 47A to 48B.

First, as shown in FIG. 47A, a double-sided copper-clad laminate 1000 is prepared as in the above embodiment (see step S11 in FIG. 7).

Subsequently, as shown in FIG. 47B, a hole 1003 is formed by irradiating the double-sided copper-clad laminate 1000 with a laser from the first surface F1 side using, for example, a CO ₂ laser. The hole 1003 is a bottomed hole, and the shape of the hole 1003 is, for example, a hemispherical shape that is tapered so that the width becomes narrower as it becomes deeper. The shape of the hole 1003 corresponds to the first conductor portion R11 (see FIG. 46). That is, the wall surface of the hole 1003 is a curved surface.

Subsequently, as shown in FIG. 47C, for example, the double-sided copper-clad laminate 1000 is turned over, and a laser beam is irradiated to the double-sided copper-clad laminate 1000 from the second surface F2 side, thereby forming a hole 1004 connected to the hole 1003. . The shape of the hole 1004 corresponds to the second conductor portion R12 (see FIG. 46). By connecting the hole 1003 and the hole 1004, a through hole 300a penetrating the double-sided copper-clad laminate 1000 is formed. Thereafter, desmearing is performed on the through hole 300a as necessary. The shape of the through hole 300a corresponds to the through hole conductor 300b (see FIG. 46) and has an hourglass shape (a drum shape). The boundary between the hole 1003 and the hole 1004 corresponds to the constricted portion 300c (see FIG. 46). The laser irradiation on the first surface F1 and the laser irradiation on the second surface F2 may be performed simultaneously.

Subsequently, as shown in FIG. 48A, electroless plating is performed to form, for example, a copper electroless plating film 1005a on the copper foils 1001 and 1002 and in the through hole 300a.

Subsequently, as shown in FIG. 48B, electrolytic plating 1005b is formed by performing electroplating using the electroless plating film 1005a as a seed layer using a plating solution. As a result, the plating 1005 composed of the electroless plating film 1005a and the electrolytic plating 1005b is filled in the through hole 300a, and the through hole conductor 300b is formed.

Subsequently, patterning of each conductor layer formed on the first surface F1 and the second surface F2 of the substrate 100 is performed using, for example, an etching resist and an etching solution. Thereby, conductor layers 301 and 302 are formed on the first surface F1 and the second surface F2 of the substrate 100, respectively (see FIG. 46). Note that the etching is not limited to wet, and may be dry.

In the above embodiment, the taper angles of the first conductor portion R11 and the second conductor portion R12 in the through-hole conductor 300b are substantially constant, but the present invention is not limited to this. For example, as shown in FIG. 49, the first conductor portion R11 has a conductor portion R21 having a taper angle θ11 and a taper angle θ12 smaller than the taper angle θ11 (that is, the ratio of the width being narrowed or the ratio of the width being increased). (Small) conductor portion R22. In the example of FIG. 49, the conductor portion R21 whose width decreases from the first surface F1 toward the boundary surface F100 between the conductor portion R21 and the conductor portion R22, and the conductor whose width decreases from the boundary surface F100 toward the reference surface F0. The through-hole conductor 300b is formed by connecting the portion R22 and the second conductor portion R12 having a width that increases from the reference surface F0 toward the second surface F2. The conductor portion R21, the conductor portion R22, and the second conductor portion R12 are formed continuously (integrally). The side surface of the conductor portion R21 and the side surface of the second conductor portion R12 are curved surfaces, and the side surface of the conductor portion R22 is a flat surface. The taper angle θ11 of the conductor portion R21 and the taper angle θ2 of the second conductor portion R12 are substantially the same.

Further, the dimension T12 from the second surface F2 to the reference surface F0 is smaller than the dimension T11 from the first surface F1 to the reference surface F0. Regarding the dimensions of the through-hole conductor 300b, the width D31 of the first surface F1 side end surface, the width D32 of the constricted portion 300c, the width D33 of the second surface F2 side end surface, and the boundary portion between the conductor portion R21 and the conductor portion R22 The width D34 is in the order of the width D31 (= width D33), the width D34, and the width D32 from the larger one.

Hereinafter, an example of a method for manufacturing the through-hole conductor 300b shown in FIG. 49 will be described with reference to FIGS. 50A to 51B.

First, as shown in FIG. 50A, a double-sided copper-clad laminate 1000 is prepared as in the above embodiment (see step S11 in FIG. 7).

Subsequently, as shown in FIG. 50B, a hole 1003a is formed by irradiating the double-sided copper-clad laminate 1000 with a laser from the first surface F1 side using, for example, a CO ₂ laser, and a laser is emitted from the second surface F2 side. Is formed on the double-sided copper-clad laminate 1000 to form a hole 1004. The hole 1003a and the hole 1004 are each a bottomed hole, and are formed at substantially the same position in the XY plane and shifted in the Z direction. Thereby, the hole 1003a and the hole 1004 are disposed so as to face each other with the substrate 100 interposed therebetween. The shape of the hole 1003a corresponds to the conductor portion R21 (see FIG. 49), and the shape of the hole 1004 corresponds to the second conductor portion R12 (see FIG. 49). Each of the shapes of the

holes

1003a and 1004 is, for example, a hemisphere that is tapered so that the width becomes narrower as it becomes deeper. Each of the wall surfaces of the

holes

1003a and 1004 is, for example, a curved surface. Laser irradiation on the first surface F1 and laser irradiation on the second surface F2 may be performed one side at a time or simultaneously.

Subsequently, as shown in FIG. 50C, by using, for example, a CO ₂ laser, the double-sided copper-clad laminate 1000 (specifically, in the hole 1003a) is irradiated with laser from the first surface F1 side, whereby the hole 1003a and the hole 1004 are irradiated. Hole 1003b is formed. The shape of the hole 1003b corresponds to the conductor portion R22 (see FIG. 49). By connecting the hole 1003a, the hole 1003b, and the hole 1004, a through hole 300a penetrating the double-sided copper-clad laminate 1000 is formed. Thereafter, desmearing is performed on the through hole 300a as necessary. The shape of the through hole 300a corresponds to the through hole conductor 300b (see FIG. 49) and has an hourglass shape (a drum shape). The boundary between the hole 1003b and the hole 1004 corresponds to the constricted portion 300c (see FIG. 49).

Subsequently, as shown in FIG. 51A, electroless plating is performed to form, for example, a copper electroless plating film 1005a on the copper foils 1001 and 1002 and in the through hole 300a.

Subsequently, as shown in FIG. 51B, electrolytic plating 1005b is formed by performing electroplating using the electroless plating film 1005a as a seed layer using a plating solution. As a result, the plating 1005 composed of the electroless plating film 1005a and the electrolytic plating 1005b is filled in the through hole 300a, and the through hole conductor 300b is formed.

Subsequently, patterning of each conductor layer formed on the first surface F1 and the second surface F2 of the substrate 100 is performed using, for example, an etching resist and an etching solution. Thereby, conductor layers 301 and 302 are formed on the first surface F1 and the second surface F2 of the substrate 100, respectively (see FIG. 49). Note that the etching is not limited to wet, and may be dry.

As shown in FIG. 52, the first conductor portion R11 and the second conductor portion R12 in the through-hole conductor 300b may be connected so as to be shifted in the X direction or the Y direction. Further, the boundary surface between the first conductor portion R11 and the second conductor portion R12 may be inclined with respect to the main surface of the wiring board or may be a curved surface.

The shapes of the electronic component 200 and the cavity R10 are arbitrary. For example, as shown in FIG. 53, the opening shape of the cavity R10 may be substantially oval. The shape of the main surface of the electronic component 200 and the shape of the opening of the cavity R10 may be substantially circles (substantially perfect circles), and are substantially many other than substantially rectangular, such as substantially squares, substantially regular hexagons, and substantially regular octagons. It may be square. In addition, the shape of the polygonal corner is arbitrary, and may be rounded, for example, substantially right angle, acute angle, obtuse angle.

The planar shape of a filled conductor such as the through-hole conductor 300b or the via conductor 311b is not limited to a circle and is arbitrary. The planar shape of the filled conductor in the wiring board may be a quadrangle such as a square as shown in FIG. 54A, for example, from the center such as a cross or a regular polygonal star as shown in FIG. 54B or 54C. It may be a shape in which a straight line is drawn radially (a shape in which a plurality of blades are arranged radially), or may be an ellipse or a triangle. In addition, the planar shapes of the first conductor portion R11, the second conductor portion R12, and the constricted portion 300c may be different from each other. For example, the planar shape of the first conductor portion R11 and the second conductor portion R12 may be a circle, and the planar shape of the constricted portion 300c may be a rectangle.

In the above embodiment, the electronic component 200 has a double-sided via structure, but the present invention is not limited to this. For example, as shown in FIG. 55, a wiring board having via conductors 311b electrically connected to the

electrodes

210 and 220 of the electronic component 200 only on one side may be used.

In the first embodiment, the double-sided wiring board (wiring board 10) having the conductor layers on both sides of the core substrate is shown, but the invention is not limited to this. For example, as shown in FIG. 55, a single-sided wiring board having a first buildup portion B1 (including the conductor layer 110) only on one side of the core substrate (substrate 100) may be used.

For example, as shown in FIG. 55, the cavity R 10 (the storage space for the electronic component 200) may be a hole (concave) that does not penetrate the substrate 100. Also in this case, it is considered preferable that the thickness of the electronic component 200 and the depth of the cavity R10 (hole) substantially coincide.

In the above embodiment, an example is shown in which the thickness of the substrate 100 and the thickness of the electronic component 200 are substantially the same, but the present invention is not limited to this. For example, as shown in FIG. 55, the thickness of the substrate 100 may be larger than the thickness of the electronic component 200.

A wiring board having two or more build-up layers on one side of the substrate 100 (core substrate) may be used. For example, as shown in FIG. 56, two insulating

layers

101 and 103 and two

conductor layers

110 and 130 are alternately stacked on the first surface F1 side of the substrate 100, and the second surface F2 side of the substrate 100 is formed. In addition, the two insulating

layers

102 and 104 and the two

conductor layers

120 and 140 may be alternately stacked. In the example of FIG. 56, the conductor layer 110 on the insulating layer 101 and the conductor layer 130 on the insulating layer 103 are electrically connected to each other via the via conductor 332b in the hole 332a (via hole) formed in the insulating layer 103. Connected to. In addition, the conductor layer 120 on the insulating layer 102 and the conductor layer 140 on the insulating layer 104 are electrically connected to each other via a via conductor 342b in a hole 342a (via hole) formed in the insulating layer 104. . The through-hole conductor 300b and the via

conductors

312b, 322b, 332b, and 342b are all filled conductors, and these are stacked in the Z direction, so that a filled stack S is formed.

In the example of FIG. 56, all the via conductors (via

conductors

311b, 312b, and 332b) included in the first buildup portion B1 formed on the first surface F1 side of the substrate 100 (core substrate) are respectively the reference surface F0. All the via conductors (via

conductors

321b, 322b, and 342b) included in the second buildup portion B2 formed on the second surface F2 side of the substrate 100 (core substrate) are reduced to the reference, respectively. The width decreases toward the surface F0. Thereby, it is considered that stress and the like are easily concentrated on the reference plane F0 in the substrate 100 (core substrate), and the stress distribution in the XY plane can be made uniform. As a result, it is considered that the warpage of the wiring board is suppressed and the reliability of electrical connection in the wiring board is improved. In particular, all the via conductors (via

conductors

311b and 312b) formed in the insulating layer 101 (first insulating layer) become narrower toward the reference plane F0, and the insulating layer 102 (second insulating layer). It is considered that the structure in which all the via conductors (via

conductors

321b and 322b) formed in () are narrowed toward the reference plane F0 contributes to the effect of suppressing the warping of the wiring board described above.

Further, the number of build-up layers may be different between the first surface F1 side of the substrate 100 and the second surface F2 side of the substrate 100. However, in order to relieve stress, it is preferable to increase the symmetry of the front and back by making the number of buildup layers the same on the first surface F1 side of the substrate 100 and the second surface F2 side of the substrate 100. Conceivable.

As shown in FIG. 57, the substrate 100 (core substrate) may incorporate a metal plate 100d (for example, copper foil). In such a substrate 100, heat dissipation is improved by the metal plate 100d. In the example of FIG. 57, the via conductor 100e reaching the metal plate 100d is formed on the substrate 100, and the metal plate 100d and the ground line (conductor patterns included in the conductor layers 301 and 302) are mutually connected via the via conductor 100e. Electrically connected. As shown in FIG. 57, the metal plate 100d is preferably disposed near the reference plane F0. The planar shape of the metal plate 100d is arbitrary, and may be a quadrangle as shown in FIG. 58A, for example, or a circle as shown in FIG. 58B.

The metal plate 100d may be formed so as to surround the cavity R10 (opening), for example, as shown in FIG. In the example of FIG. 59, through-hole conductors 300b are arranged in the four directions of the cavity R10. On the substrate 100 (core substrate), the land 301b of the through-hole conductor 300b and the wiring 301c connected to the land 301b are formed. The conductor layer 301 is included in the land 301b and the wiring 301c.

In the example of FIG. 59, a metal plate 100d is provided on substantially the entire surface excluding the vicinity of the penetrating portion (such as the cavity R10 or the through hole 300a) of the substrate 100 (core substrate). The metal plate 100d is formed so as to avoid the vicinity of the penetrating portion (for example, the range of the distance D40 from the penetrating portion). The distance D40 is 120 μm, for example. The conductor layer 301 on the substrate 100 (core substrate) is formed at a position farther from the cavity R10 (opening) than the metal plate 100d. That is, the conductor layer 301 and the metal plate 100d are each formed to avoid the vicinity of the cavity R10. Furthermore, a part of the metal plate 100d is disposed between the through-hole conductor 300b (or the through-hole 300a) and the cavity R10.

FIG. 59 shows a preferred example of dimensions in FIG. A distance D41 between the electronic component 200 and the metal plate 100d is, for example, 160 μm. A gap R1 (each of the widths D3 and D4) between the electronic component 200 and the substrate 100 is, for example, 40 μm.

The metal plate 100d is not formed, for example, in the range of 120 μm (distance D41−width D3) from the cavity R10. The conductor layer 301 on the substrate 100 (core substrate) is formed at a position farther from the cavity R10 (opening) than the metal plate 100d. That is, the conductor layer 301 and the metal plate 100d are each formed to avoid the vicinity of the cavity R10.

The conductor layer 301 on the substrate 100 (core substrate) may be formed at a position closer to the cavity R10 (opening) than the metal plate 100d, for example, as shown in FIGS. 60A to 60C.

In the example of FIG. 60A, the land 301b of the through-hole conductor 300b is formed at a position closer to the cavity R10 (opening) than the metal plate 100d. That is, the distance D42 between the electronic component 200 and the land 301b is smaller than the distance D41 between the electronic component 200 and the metal plate 100d.

In the example of FIG. 60B, the reinforcing pattern 301d included in the conductor layer 301 is formed at a position closer to the cavity R10 (opening) than the metal plate 100d. That is, the distance D43 between the electronic component 200 and the reinforcing pattern 301d is smaller than the distance D41 between the electronic component 200 and the metal plate 100d. In the example of FIG. 60B, a reinforcing pattern 301d having a ring-shaped outer shape is formed so as to surround the cavity R10 (opening).

In the example of FIG. 60C, the wiring pattern 301e included in the conductor layer 301 is formed at a position closer to the cavity R10 (opening) than the metal plate 100d. That is, the distance D44 between the electronic component 200 and the wiring pattern 301e is smaller than the distance D41 between the electronic component 200 and the metal plate 100d.

Hereinafter, an example of a method for manufacturing the substrate 100 (core substrate) shown in FIG. 57 will be described with reference to FIGS. 61A and 61B.

First, as shown in FIG. 61A, insulating

layers

4001 and 4002 are disposed so as to sandwich a metal plate 100d made of, for example, copper foil, copper foil 4001a is further disposed on insulating layer 4001, and copper foil is disposed on insulating layer 4002. 4001b is arranged. Thereby, the insulating layer 4001 (first insulating resin layer), the metal plate 100d having a predetermined pattern, and the insulating layer 4002 (second insulating resin layer) are laminated in this order. Each of the insulating

layers

4001 and 4002 is made of, for example, glass prepreg. For example, the metal plate 100d has a pattern (XY plane) shown in FIG. The thickness D22 of the metal plate 100d is, for example, 35 μm.

Subsequently, the laminated body of the copper foil 4001a, the insulating layer 4001, the metal plate 100d, the insulating layer 4002, and the copper foil 4001b is pressed, and pressure is applied toward the metal plate 100d. By pressing the insulating

layers

4001 and 4002 in a semi-cured state, as shown in FIG. 61B, the resin flows out from the insulating

layers

4001 and 4002, respectively. As a result, the resin constituting the insulating

layer

4001 or 4002 is filled into the side of the metal plate 100d (the portion without the metal plate 100d in the pattern of the metal plate 100d), and the insulating layer 4003 is formed. Thereafter, the insulating

layers

4001, 4002, and 4003 are cured by heating. Thereby, the substrate 100 (core substrate) incorporating the metal plate 100d is completed.

In the wiring board manufactured by such a method, as shown in FIG. 62, the insulator 101a (first insulator) is filled in the gap R1 between the electronic component 200 and the substrate 100 (core substrate) in the cavity R10 (opening). Then, the substrate 100 has an insulating layer 4003 (second insulator) between the metal plate 100d and the cavity R10. The insulating layer 4003 is made of a material different from that of the insulator 101a. Specifically, the insulator 101a is made of a resin constituting the insulating

layer

101 or 102 formed on the substrate 100 and the electronic component 200 across the gap R1 between the electronic component 200 and the substrate 100 in the cavity R10 ( (See FIG. 19A). On the other hand, the insulating layer 4003 is made of a resin constituting the insulating layers 4001 and 4002 (see FIG. 61B). Here, each of the resins constituting the insulating

layers

101 and 102 has a lower coefficient of thermal expansion (CTE) than the resins constituting the insulating

layers

4001 and 4002. Therefore, the thermal expansion coefficient of the insulator 101a is lower than that of the insulating layer 4003. Thereby, the CTE mismatch between the capacitor and the resin is relaxed, and the adhesion between the capacitor and the resin is improved. Each of the insulating

layers

101 and 102 is made of, for example, an epoxy resin film with an inorganic filler (inorganic filler content 40% or more), and each of the insulating

layers

4001 and 4002 is, for example, a prepreg (an epoxy resin sheet with a glass substrate). Consists of.

As a preferred example of the electronic component built-in wiring board, a wiring board as shown in FIG. 63A is also conceivable. Hereinafter, the wiring board shown in FIG. 63A will be described focusing on differences from the above embodiment.

In the example of FIG. 63A, four insulating

layers

101, 103, 105, and 107 (interlayer insulating layers, respectively) and four

conductor layers

110, 130, 150, and 170 are alternately arranged on the first surface F1 side of the substrate 100. These are stacked to form the first buildup part B1. Further, four insulating

layers

102, 104, 106, 108 (interlayer insulating layers) and four

conductor layers

120, 140, 160, 180 are alternately stacked on the second surface F2 side of the substrate 100. These constitute the second buildup part B2. The conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layers 110, 130, 150, and 170 higher than the conductor layer 301 are mutually connected by via

conductors

312b, 332b, 352b, and 372b formed in each interlayer insulating layer. Is electrically connected. In addition, the conductor layer 302 on the second surface F2 of the substrate 100 and the conductor layers 120, 140, 160, and 180 higher than the conductor layer 302 are formed by via

conductors

322b, 342b, 362b, and 382b formed in each interlayer insulating layer. Are electrically connected to each other.

In the example of FIG. 63A, as in the above embodiment, the electronic component 200 is disposed in the cavity R10 (through hole) formed in the substrate 100 and is located on the side of the substrate 100 (X direction or Y direction). However, the

electrodes

210 and 220 of the electronic component 200 are connected to the via conductor 311b only from one surface (the first surface F1 side). The

electrodes

210 and 220 of the electronic component 200 are electrically connected to the conductor layer 110 via via conductors 311b formed in the insulating layer 101, respectively. The electronic component 200 is built (mounted) on the wiring board by a single-sided via structure.

In a preferred example, the substrate 100 is made of glass epoxy, the insulating

layers

101 and 102 are made of copper foil with resin (prepreg), and the insulating

layers

103, 104, 105, 106, 107 and 108 are made of ABF (AjinomotoinoBuild- up Film: made by Ajinomoto Fine Techno Co., Ltd. ABF is a film in which an insulating material is sandwiched between two protective sheets.

Each of the conductor layers 110 and 120 is made of, for example, copper foil (lower layer) and copper plating (upper layer), and is formed by, for example, a subtractive method. Further, each of the conductor layers 130, 140, 150, 160, 170, 180 is made of, for example, copper plating, and is formed by, for example, a semi-additive (SAP) method. The via

conductors

311b, 312b, and 322b are conformal conductors made of, for example, copper plating, and the via

conductors

332b, 342b, 352b, 362b, 372b, and 382b are filled conductors made of, for example, copper plating.

In a preferred example, the thickness of the substrate 100 is 600 μm, the thickness of the electronic component 200 (including the electrodes 210 and 220) is 550 μm, the thickness of the conductor layers 301 and 302 is 35 μm, respectively. Each of 110, 120, 130, 140, 150, 160, 170, and 180 has a thickness of 60 μm.

Through-hole 300a is formed in substrate 100 (core substrate), and through-hole conductor 300d is formed by forming a conductor film (for example, copper plating) on the wall surface of through-hole 300a. The conductor layer 301 on the first surface F1 of the substrate 100 and the conductor layer 302 on the second surface F2 of the substrate 100 are electrically connected to each other via a through-hole conductor 300d. The shape of the through hole 300a is, for example, a cylinder.

The insulator 300e is filled inside the through-hole conductor 300d in the through-hole 300a (specifically, a space surrounded by the through-hole conductor 300d, the

lands

300f, and 300g). As shown in FIG. 63B, each of the

lands

300f and 300g included in the conductor layers 301 and 302 is a planar conductor (cover plating) formed on the insulator 300e by copper plating, for example. Is electrically connected. The insulator 300e is made of resin, for example.

The conductor layer 170 is the outermost conductor layer on the first surface F1 side, and the conductor layer 180 is the outermost conductor layer on the second surface F2 side. Solder resists 11 and 12 are formed on the conductor layers 170 and 180, respectively. However,

openings

11a and 12a are formed in the solder resists 11 and 12, respectively. For this reason, the predetermined part (part located in the opening part 11a) of the conductor layer 170 is exposed without being covered with the solder resist 11, and becomes the pad P1. In addition, a predetermined part of the conductor layer 180 (part located in the opening 12a) is a pad P2. The pads P1 and P2 respectively have corrosion

resistant layers

170a and 180a made of, for example, a Ni / Au film on the surface thereof. Each of the corrosion-

resistant layers

170a and 180a can be formed by, for example, electrolytic plating or sputtering. Further, the corrosion

resistant layers

170a and 180a made of an organic protective film may be formed by performing an OSP (Organic Solderability Preservative) process.

In the wiring board shown in FIG. 63A, instead of the through-hole conductor 300d (conformal conductor), an hourglass-shaped (drum-shaped) through-hole conductor 300b (filled conductor) according to the above-described embodiment (see FIG. 1 and the like) is used. You may apply. In this case as well, the reliability of the electrical connection in the wiring board can be increased as in the above embodiment.

The shape of the main surface of the electronic component 200 and the shape of the first opening and the second opening of the cavity R10 are not limited to a substantially rectangular shape, but are arbitrary. For example, as shown in FIG. 64A, the shape of the first opening and the shape of the second opening of the cavity R10 may be substantially oval. Further, as shown in FIG. 64B, the shape of the first opening and the shape of the second opening of the cavity R10 may be in a similar relationship. In the example of FIG. 64B, the shape of the first opening of the cavity R10 is substantially elliptical, and the shape of the second opening of the cavity R10 is substantially rectangular.

Further, the shape of the main surface of the electronic component 200, and the shape of the first opening and the shape of the second opening of the cavity R10 may be substantially circular (substantially perfect circle). Further, it may be a substantially polygonal shape other than a substantially rectangular shape, such as a substantially square shape, a substantially regular hexagonal shape, or a substantially regular octagonal shape. In addition, the shape of the polygonal corner is arbitrary, and may be rounded, for example, substantially right angle, acute angle, obtuse angle.

The

wiring boards

20 or 30 according to the second and third embodiments have the via conductor 321b electrically connected to the

electrodes

210 and 220 of the electronic component 200 on the second surface F2 side (the side opposite to the tapered surface C11). However, it is not limited to this. For example, as shown in FIG. 65, via conductor 311b (conductor in hole 311a formed in insulating layer 101) electrically connected to

electrodes

210 and 220 of electronic component 200 is connected to first surface F1 side of substrate 100 ( A wiring board provided on the side having the tapered surface C11 may be used.

The wiring board with a built-in electronic component having two or more build-up layers on one side of the core substrate may be used. For example, as shown in FIG. 66, two insulating

layers

101 and 103 and two

conductor layers

layers

102 and 104 and the two

conductor layers

120 and 140 may be alternately stacked. In the example of FIG. 66, a hole 331a (via hole) is formed in the insulating layer 103, and a conductor (for example, copper plating) is filled in the hole 331a, whereby the conductor in the hole 331a becomes a via conductor 331b ( Filled conductor). The conductor layer 110 on the insulating layer 101 and the conductor layer 130 on the insulating layer 103 are electrically connected to each other through the via conductor 331b. In addition, a hole 341a (via hole) is formed in the insulating layer 104, and a conductor (for example, copper plating) is filled in the hole 341a, whereby the conductor in the hole 341a becomes a via conductor 341b (filled conductor). Become. The conductor layer 120 on the insulating layer 102 and the conductor layer 140 on the insulating layer 104 are electrically connected to each other through the via conductor 341b.

The number of buildup layers may be different between the first surface F1 side of the substrate 100 and the second surface F2 side of the substrate 100. However, in order to relieve stress, it is preferable to increase the symmetry of the front and back by making the number of buildup layers the same on the first surface F1 side of the substrate 100 and the second surface F2 side of the substrate 100. Conceivable.

In the second embodiment, the double-sided wiring board (wiring board 20) having the conductor layers on both sides of the core substrate is shown, but the invention is not limited to this. For example, as shown in FIG. 67, a single-sided wiring board having a conductor layer only on one side of the core substrate (substrate 100) may be used. FIG. 67 shows a single-sided wiring board having the conductor layer 110 only on the first surface F1 side (side having the tapered surface C11), but is not limited thereto. For example, as shown in FIG. 68, a single-sided wiring board having

conductor layers

120 and 140 only on the second surface F2 side (the side opposite to the tapered surface C11) may be used.

Further, for example, as shown in FIG. 67, the cavity R10 (the storage space for the electronic component 200) may be a hole (concave) that does not penetrate the substrate 100. Also in this case, it is considered preferable that the thickness of the electronic component 200 and the depth of the cavity R10 (hole) substantially coincide.

In each of the above embodiments, the example in which the thickness of the substrate 100 and the thickness of the electronic component 200 are substantially the same is shown, but the present invention is not limited to this. For example, as shown in FIG. 67, the thickness of the substrate 100 may be larger than the thickness of the electronic component 200.

69, a wiring board having a cavity R10 on the surface may be used. In the example of FIG. 69, the gap between the electronic component 200 and the substrate 100 in the cavity R10 is filled with the insulator 101a, but the present invention is not limited to this. For example, the electronic component 200 may be partially fixed to the substrate 100 with an adhesive or the like.

A wiring board having tapered surfaces on both sides of the core substrate may be used. As shown in FIG. 70, a tapered surface C11 is formed at the corner between the side surface F10 (inner wall of the cavity R10) of the substrate 100 and the first surface F1, and the side surface F10 (inner wall of the cavity R10) of the substrate 100 and the second surface F2. A tapered surface C12 may be formed at the corner. If the tapered surfaces C11 and C12 are formed on both sides of the substrate 100, a step of aligning the orientation (front / back) of the substrate 100 during manufacturing can be omitted.

In each of the above embodiments, the tapered surface C11 is formed on the entire periphery of the cavity R10. However, the present invention is not limited to this. For example, as shown in FIG. 71, the tapered surface C11 may be partially formed on the peripheral edge of the cavity R10. In the example of FIG. 71, the clearances for accommodating the electronic component 200 in the cavity R10 are different from each other in the X direction and the Y direction. For example, the tapered surface C11 is formed only on two opposing sides.

In each of the above embodiments, the first layer 100a does not contain an inorganic material, but the present invention is not limited to this. For example, as shown in FIG. 72, it is considered that the tapered surface C11 can be easily formed even when the first layer 100a contains less inorganic material than the second layer 100b.

In addition, as shown in FIG. 73, for example, the substrate 100 is formed of a first layer 100a, a second layer 100b, and a third layer 100c of different materials in this order from the first surface F1 toward the second surface F2. You may have. In the example of FIG. 73, the first layer 100a does not include an inorganic material, the second layer 100b includes an inorganic material, and the third layer 100c includes more inorganic materials than the second layer 100b. The side surface F10 of the substrate 100 facing the cavity R10 is composed of the side surface F12 of the second layer 100b and the side surface F11 of the third layer 100c. In this example, in FIG. 73, the taper angle θ22 of the side surface F12 is smaller than the taper angle θ21 of the taper surface C11.

Further, for example, as shown in FIG. 74, the substrate 100 may have a first layer 100a and a second layer 100b of different materials in this order from the first surface F1 toward the second surface F2. . In the example of FIG. 74, the first layer 100a does not include an inorganic material, and the second layer 100b includes an inorganic material.

A wiring board having a layer containing the most inorganic material in the inner layer of the substrate 100 may be used. For example, as shown in FIG. 75, the substrate 100 includes a first layer 100a that does not include an inorganic material, a second layer 100b that includes an inorganic material, and an inorganic material from the first surface F1 toward the second surface F2. A third layer 100c that is not present. With such a structure, the tapered surfaces C 11 and C 12 can be easily formed on both sides of the substrate 100. It is considered that the first layer 100a and the third layer 100c (tapered surfaces C11 and C12) are preferably thinner than the electronic component 200, respectively.

The material of the first layer 100a and the material of the second layer 100b may be different except for the content of the inorganic material. For example, the first layer 100a and the second layer 100b may be made of different resins. Also in this case, if the first layer 100a is stronger than the second layer 100b with respect to the processing (for example, laser processing) of the substrate 100, it is considered that the tapered surface C11 can be easily formed.

In each of the above embodiments, the tapered surface C11 is formed by laser processing. However, the present invention is not limited to this, and when the tapered surface C11 is formed by dry etching or the like, the first layer 100a and the second layer made of different materials are used. It is considered that the taper surface C11 can be easily formed by 100b. However, it is considered that a particularly good tapered surface C11 can be obtained by laser processing.

As shown in FIG. 76, the substrate 100 (core substrate) may incorporate a metal plate 100d (for example, copper foil). In such a substrate 100, heat dissipation is improved by the metal plate 100d. In the example of FIG. 76, the via conductor 100e reaching the metal plate 100d is formed on the substrate 100, and the metal plate 100d and the ground line (conductor patterns included in the conductor layers 301 and 302) are mutually connected via the via conductor 100e. Electrically connected.

A substrate with a built-in metal plate tends to be thicker than a substrate without a built-in metal plate. For this reason, the board | substrate which incorporates a metal plate tends to be thicker than the electronic component arrange | positioned at the opening part of a board | substrate. Moreover, the thickness of the substrate is likely to increase as the thickness of the metal plate incorporated in the substrate increases. As the thickness of the substrate increases, the difference between the thickness of the substrate and the thickness of the electronic component tends to increase.

When the difference between the thickness of the substrate and the thickness of the electronic component becomes large, the mounter easily hits the substrate in the step of putting the electronic component into the opening formed in the substrate. However, in the wiring board shown in FIG. 76, since the tapered surface C11 is formed on the substrate 100, interference between the mounter and the substrate 100 can be suppressed. Hereinafter, this will be further described with reference to FIGS. 77A to 78.

FIG. 77A shows a wiring board composed of the substrate 100 (core substrate) on which the tapered surface C11 is not formed. In such a wiring board manufacturing process, when the electronic component 200 is put into the cavity R10 formed in the substrate 100, the mounter 3000a holds the electronic component 200 by, for example, a vacuum chuck. Then, after the mounter 3000a is moved above the cavity R10 (Z1 side), the mounter 3000a is gradually brought closer to the substrate 100 from there to place the electronic component 200 in the cavity R10. At this time, since the electronic component 200 is smaller than the cavity R10 and can pass through the cavity R10, the mounter 3000a is not necessarily smaller than the cavity R10. Therefore, depending on the size of the mounter 3000a, as shown in FIG. 77B The mounter 3000a may hit the substrate 100 (especially its corner).

In this regard, in the wiring board shown in FIG. 76, the substrate 100 extends from the first surface F1 to the second surface F2 at the corner between the side surface F10 of the substrate 100 facing the cavity R10 (the inner wall of the cavity R10) and the first surface F1. A tapered surface C11 is formed to reduce the width of the cavity R10. By forming the taper surface C11 on the substrate 100, the corners of the side surface F10 and the first surface F1 of the substrate 100 are chamfered, and the width of the cavity R10 is increased on the first surface F1 side of the substrate 100 where the mounter 3000a easily interferes. Become wider. As a result, as shown in FIG. 78, the mounter 3000a and the substrate 100 are less likely to interfere (contact).

Such interference between the mounter 3000a and the substrate 100 is particularly likely to occur when the difference (D51-D53) between the thickness D51 of the substrate 100 and the thickness D53 of the electronic component 200 in FIG. 78 is about 20 μm or more. In this regard, according to the wiring board in which the tapered surface C11 is formed on the substrate 100, it is possible to suppress the interference between the mounter 3000a and the substrate 100 as described above. It is possible to improve the yield when manufacturing a wiring board having a difference (D51−D53) of 200 from the thickness D53 of about 20 μm or more.

Moreover, in order to ensure heat dissipation or strength, it is preferable that the thickness D52 of the metal plate 100d is about 30 μm or more. However, the thicker the metal plate 100d, the thicker the substrate 100 becomes, so that the mounter 3000a and the substrate 100 are likely to interfere with each other in the step of inserting the electronic component 200 into the cavity R10. In this respect, according to the wiring board in which the taper surface C11 is formed on the substrate 100, it is possible to suppress the interference between the mounter 3000a and the substrate 100 as described above. Therefore, the wiring board incorporating the thick metal plate 100d. It is possible to improve the yield in the case of manufacturing.

78, the tapered surface C11 is preferably formed from the first surface F1 to a position deeper than the third surface F3 of the electronic component 200. That is, it is preferable that the depth D54 of the tapered surface C11 is larger than the difference between the thickness D51 of the substrate 100 and the thickness D53 of the electronic component 200 (D54> D51-D53). Thereby, before the mounter 3000a advances deeper than the taper surface C11, the arrangement (accommodation) of the electronic component 200 is easily completed. As a result, the mounter 3000a and the substrate 100 (especially the corner) are less likely to interfere with each other.

In a preferred example, the thickness D51 of the substrate 100 is about 180 μm, the thickness D53 of the electronic component 200 is about 140 μm, the depth D54 of the tapered surface C11 is about 40 μm, and the thickness D52 of the metal plate 100d is About 35 μm. The difference (D51−D53) between the thickness D51 of the substrate 100 and the thickness D53 of the electronic component 200 is about 40 μm.

The planar shape of the metal plate 100d is arbitrary, and may be, for example, a square as shown in FIG. 79A, or may be a circle as shown in FIG. 79B, for example.

The metal plate 100d may be formed so as to surround the cavity R10, for example, as shown in FIG. In the example of FIG. 80, through-hole conductors 300b are arranged in the four directions of the cavity R10. On the substrate 100 (core substrate), the land 301b of the through-hole conductor 300b and the wiring 301c connected to the land 301b are formed. The conductor layer 301 is included in the land 301b and the wiring 301c.

In the example of FIG. 80, a metal plate 100d is provided on substantially the entire surface excluding the vicinity of the through portion (cavity R10 or through hole 300a) of the substrate 100 (core substrate). The metal plate 100d is formed so as to avoid the vicinity of the penetrating portion (for example, the range of the distance D40 from the penetrating portion). The conductor layer 301 on the substrate 100 (core substrate) is formed at a position farther from the cavity R10 than the metal plate 100d. That is, the conductor layer 301 and the metal plate 100d are each formed to avoid the vicinity of the cavity R10. Furthermore, a part of the metal plate 100d is disposed between the through-hole conductor 300b (or the through-hole 300a) and the cavity R10.

The conductor layer 301 on the substrate 100 (core substrate) may be formed at a position closer to the cavity R10 than the metal plate 100d, for example, as shown in FIGS. 81A to 81C.

In the example of FIG. 81A, the land 301b of the through-hole conductor 300b is formed at a position closer to the cavity R10 than the metal plate 100d. That is, the distance D42 between the electronic component 200 and the land 301b is smaller than the distance D41 between the electronic component 200 and the metal plate 100d.

81B, the reinforcing pattern 301d included in the conductor layer 301 is formed at a position closer to the cavity R10 than the metal plate 100d. That is, the distance D43 between the electronic component 200 and the reinforcing pattern 301d is smaller than the distance D41 between the electronic component 200 and the metal plate 100d. In the example of FIG. 81B, a reinforcing pattern 301d having a ring-shaped outer shape is formed so as to surround the cavity R10.

In the example of FIG. 81C, the wiring pattern 301e included in the conductor layer 301 is formed at a position closer to the cavity R10 than the metal plate 100d. That is, the distance D44 between the electronic component 200 and the wiring pattern 301e is smaller than the distance D41 between the electronic component 200 and the metal plate 100d.

Hereinafter, an example of a method for manufacturing the substrate 100 (core substrate) shown in FIG. 76 will be described with reference to FIGS. 82A and 82B.

First, as shown in FIG. 82A, insulating

layers

4001 and 4002 is made of, for example, glass prepreg. For example, the metal plate 100d has a pattern (XY plane) shown in FIG.

layers

4001 and 4002 in a semi-cured state, as shown in FIG. 82B, the resin flows out from the insulating

layers

4001 and 4002, respectively. As a result, the resin constituting the insulating

layer

layers

In the wiring board manufactured by such a method, as shown in FIG. 83, a gap R1 between the electronic component 200 and the substrate 100 (core substrate) in the cavity R10 is filled with the insulator 101a (first insulator). Has an insulating layer 4003 (second insulator) between the metal plate 100d and the cavity R10. The insulating layer 4003 is made of a material different from that of the insulator 101a. Specifically, the insulator 101a is made of a resin that constitutes the insulating

layer

101 or 102 formed on the substrate 100 and the electronic component 200 across the gap R1 between the electronic component 200 and the substrate 100 in the cavity R10. On the other hand, the insulating layer 4003 is made of a resin that forms the insulating layers 4001 and 4002 (see FIG. 82B). Here, each of the resins constituting the insulating

layers

101 and 102 has a lower coefficient of thermal expansion (CTE) than each resin constituting the insulating

layers

4001 and 4002 is, for example, a prepreg (an epoxy resin sheet with a glass base material). Consists of.

In each of the above embodiments, a wiring board having only one electronic component 200 in the cavity R10 (accommodating space for the electronic component 200) is shown, but the present invention is not limited to this. For example, a wiring board having a plurality of electronic components 200 in the cavity R10 may be used. The plurality of electronic components 200 may be arranged in the stacking direction (Z direction) or in the X direction or the Y direction. A plurality of cavities R10 may be formed.

Regarding the other points, the configuration of the

wiring boards

10, 20, and 30 (wiring boards with built-in electronic components), in particular, the type, performance, dimensions, material, shape, number of layers, arrangement, etc. of the constituent elements of the present invention. Any change may be made without departing from the spirit of the invention.

The shape of the

electrodes

210 and 220 of the electronic component 200 is not limited to a U shape, and for example, the capacitor body 201 may be sandwiched between flat electrode pairs.

The type of electronic component 200 is not limited to MLCC and is arbitrary. For example, in addition to passive components such as capacitors, resistors, and coils, arbitrary electronic components such as active components such as IC circuits can be employed. However, since the chip capacitor is easily cracked, it is particularly important to suppress cracking when the chip capacitor is disposed in the cavity R10.

The shape of the

electrodes

For example, the via conductor 311b is not limited to the filled conductor, and may be a conformal conductor, for example.

The electronic component 200 may be mounted by other methods such as wire bonding connection instead of being mounted by via connection (via

conductors

311b and 321b).

The manufacturing process of the electronic component built-in wiring board is not limited to the order and contents shown in FIG. 7 or FIG. 31, and the order and contents can be arbitrarily changed without departing from the gist of the present invention. . Moreover, you may omit the process which is not required according to a use etc.

For example, the tapered surface C11 may be formed at the same time as the formation of the cavity R10, before the formation of the cavity R10, or after the formation of the cavity R10.

For example, the formation method of each conductor layer is arbitrary. For example, any one of a panel plating method, a pattern plating method, a full additive method, a semi-additive (SAP) method, a subtractive method, a transfer method, and a tenting method, or a method in which two or more of these are arbitrarily combined, A conductor layer may be formed.

Further, instead of laser, processing may be performed by wet or dry etching. In the case of processing by etching, it is considered preferable to protect a portion that is not desired to be removed in advance with a resist or the like.

The above embodiments and modifications can be arbitrarily combined. It is considered preferable to select an appropriate combination according to the application. For example, the structure shown in FIG. 46 or 49 may be applied to the structure shown in any of FIGS. 52 to 63B. For example, the structure shown in any of FIGS. 64A and 64B may be applied to the structure shown in any of FIGS. For example, the structure shown in FIG. 66 or 70 may be applied to a double-sided via structure (see Embodiment 3).

The embodiment of the present invention has been described above. However, various modifications and combinations required for design reasons and other factors are not limited to the invention described in the “claims” or the “mode for carrying out the invention”. It should be understood that it is included in the scope of the invention corresponding to the specific examples described in the above.

In this specification, the contents of Japanese Patent Application Laid-Open Nos. 2007-266197 and 2002-204045 are incorporated.

This application includes Japanese Patent Application No. 2011-155277 filed on July 13, 2011, Japanese Patent Application No. 2011-155278 filed on July 13, 2011, and October 5, 2011. Priority is claimed based on Japanese Patent Application No. 2011-220865 filed on the day, and in the specification of this application, Japanese Patent Application No. 2011-155277, Japanese Patent Application No. 2011-155278 And the contents of Japanese Patent Application No. 2011-220865, claims, and drawings.

The electronic component built-in wiring board of the present invention is suitable for realizing a circuit board such as a mobile phone. Moreover, the method for manufacturing an electronic component built-in wiring board according to the present invention is suitable for manufacturing a circuit board such as a mobile phone.

10, 20, 30 Wiring board 11, 12 Solder resist 11a, 12a Opening 100 Substrate 100a First layer 100b Second layer 100c Third layer 100d Metal plate 100e Via conductor 101-108 Insulating layer 101a Insulator 110, 120, 130 , 140, 150, 160, 170, 180 Conductor layer 111, 121 Copper foil 112, 122 Copper plating 170a, 180a Corrosion resistant layer 200 Electronic component 201 Capacitor body 210, 220 Electrode 210a, 220a Upper part 210b, 220b Side part 210c, 220c Lower part 211 to 214 Conductor layers 221 to 224 Conductor layers 231 to 239 Dielectric layer 300a Through hole 300b Through hole conductor 300c Constricted portion 300d Through hole conductor 300e Insulator 300f, 300g Land 301, 30 Conductor layer 301a Alignment mark 301b Land 301c Wiring 301d Reinforcement pattern 301e Wiring pattern 311a, 312a, 321a, 322a Hole 311b, 312b, 321b, 322b Via conductor 331a, 332a, 341a, 342a Hole 331b, 332b, 341b, 342b , 362b, 372b, 382b Via conductor 400 Electronic component 500 Wiring board 1000 Double-sided copper-clad laminate 1001, 1002 Copper foil 1003, 1003a, 1003b, 1004 Hole 1005 Plating 1005a Electroless plating film 1005b Electrolytic plating 1006 Carrier 1007, 1008 Electroless Plating film 1009, 1010 Plating resist 1009a, 1010a Opening 2001 Carrier 2003, 2004 Copper 3000 Wiring board 3000a Mounter 3001, 3002 Conductor layer 4001 to 4003 Insulating layer 4001a, 4001b Copper foil B1 First buildup part B2 Second buildup part C11, C12 Tapered surface C21, C22 Curved surface F0 Reference surface F1 First surface F2 First 2nd surface F3 3rd surface F4 4th surface F10 side surface F11 side surface F12 side surface F20 side surface F21 bottom surface F22 side surface F30 side surface F100 boundary surface P1, P2 pad R1 clearance R10 cavity R11 first conductor portion R12 second conductor portion R21, R22 conductor portion R100 area S filled stack

Claims

A core substrate having a first surface, a second surface opposite to the first surface, an opening penetrating from the first surface to the second surface, and a through hole;
A capacitor disposed in the opening;
In the electronic component built-in wiring board having
The through hole is filled with a conductor,
The conductor is formed of a first conductor portion that narrows from the first surface toward the second surface and a second conductor portion that narrows from the second surface toward the first surface. The first conductor portion and the second conductor portion are connected in the core substrate.
An electronic component built-in wiring board.
A first insulating layer formed on the first surface of the core substrate;
A second insulating layer formed on the second surface of the core substrate;
A first via hole formed in the first insulating layer;
A second via hole formed in the second insulating layer;
Further comprising
The first via hole and the second via hole are filled with a conductor;
The conductor filled in the first via hole and the conductor filled in the second via hole are each narrowed toward the capacitor and electrically connected to the electrode of the capacitor.
The wiring board with a built-in electronic component according to claim 1.
All the via holes of the first insulating layer are filled with a conductor, and the conductor becomes thinner toward the first surface,
All the via holes of the second insulating layer are filled with a conductor, and the conductor becomes narrower toward the second surface.
The wiring board with a built-in electronic component according to claim 2.
All via holes of the first buildup portion formed on the first surface side of the core substrate are filled with a conductor, and the conductor becomes thinner toward the first surface,
All via holes of the second build-up part formed on the second surface side of the core substrate are filled with a conductor, and the conductor becomes thinner toward the second surface.
The wiring board with a built-in electronic component according to claim 3.
The via hole located on the first surface side of the core substrate and the via hole located on the second surface side of the core substrate have a symmetrical arrangement and shape.
The wiring board with a built-in electronic component according to claim 4.
The conductor in the through hole is formed by directly connecting the first conductor portion and the second conductor portion.
The wiring board with a built-in electronic component according to any one of claims 1 to 5.
The core substrate has a thickness in the range of 0.06 mm to 1.0 mm,
The thermal expansion coefficient of the core substrate is the same as or smaller than the thermal expansion coefficient of the capacitor,
The wiring board with a built-in electronic component according to any one of claims 1 to 6.
When the thickness of the electronic component built-in wiring board is T1, the total thickness of the core substrate and the conductor layers on both sides thereof is T2, and the thickness of the capacitor is T3,
T3 / T2 is in the range of 0.6 to 1.7, and T3 / T1 is in the range of 0.2 to 0.7.
The wiring board with a built-in electronic component according to claim 1, wherein the wiring board has a built-in electronic component.
At least one of the front and back surfaces of the capacitor has an electrode with an area occupation ratio of 40% to 90%.
The wiring board with a built-in electronic component according to claim 1, wherein the wiring board has a built-in electronic component.
The capacitor has side electrodes;
In the side electrode, the central portion in the thickness direction of the capacitor swells outside the both end portions,
The wiring board with a built-in electronic component according to any one of claims 1 to 9.
A substrate having a first surface, a second surface opposite to the first surface, and an opening;
An electronic component having a third surface and a fourth surface opposite to the third surface, the electronic component being disposed in the opening so that the third surface is in the same direction as the first surface of the substrate; ,
In the electronic component built-in wiring board having
The electronic component has a curved surface at the corner between the side surface and the fourth surface,
The substrate has a tapered surface at the corner between the inner wall of the opening and the first surface from the first surface toward the second surface.
An electronic component built-in wiring board.
An insulator is filled between the substrate and the electronic component in the opening,
The wiring board with a built-in electronic component according to claim 11.
On the substrate and the opening, an insulating layer made of resin is provided,
The insulator is made of a resin constituting the insulating layer.
The wiring board with a built-in electronic component according to claim 12.
The electronic component is a passive component.
The wiring board with a built-in electronic component according to any one of claims 11 to 13.
The electronic component is a chip capacitor.
The electronic component built-in wiring board according to claim 14.
The inner wall of the opening is made of a laser cut surface.
The wiring board with a built-in electronic component according to any one of claims 11 to 15, wherein the wiring board has a built-in electronic component.
The substrate has a first layer and a second layer of different materials in this order from the first surface to the second surface.
The wiring board with a built-in electronic component according to any one of claims 11 to 16.
Each of the first layer and the second layer is made of resin,
The second layer includes an inorganic material,
The first layer includes less inorganic material than the second layer or does not include an inorganic material.
The wiring board with a built-in electronic component according to claim 17.
The curved surface consists of the surface of the electrode of the electronic component,
The wiring board with a built-in electronic component according to any one of claims 11 to 18.
At least the surface of the electrode of the electronic component is made of a plating film,
20. The electronic component built-in wiring board according to claim 19.
An insulating layer on the substrate and the electronic component;
In the insulating layer, a via conductor that is electrically connected to the electrode of the electronic component is formed.
The wiring board with a built-in electronic component according to any one of claims 11 to 20, wherein the wiring board has a built-in electronic component.
The inner wall of the opening is a surface substantially perpendicular to the second surface.
The wiring board with a built-in electronic component according to any one of claims 11 to 21, wherein the wiring board has a built-in electronic component.
The opening comprises a hole penetrating the substrate,
Having an insulating layer on the second surface of the substrate;
The insulating layer blocks one opening of the hole;
The wiring board with a built-in electronic component according to any one of claims 11 to 22.
The maximum value of the gap between the substrate and the electronic component is in the range of about 0 μm to about 100 μm.
The wiring board with a built-in electronic component according to any one of claims 11 to 23.
The radius of curvature of the curved surface is in the range of about 20 μm to about 40 μm.
The wiring board with a built-in electronic component according to any one of claims 11 to 24.
The substrate is thicker than the electronic component,
The tapered surface is formed from the first surface to a position deeper than the third surface of the electronic component.
The wiring board with a built-in electronic component according to any one of claims 11 to 25.
The substrate is thicker than the electronic component,
The difference between the thickness of the substrate and the thickness of the electronic component is about 20 μm or more.
The wiring board with a built-in electronic component according to any one of claims 11 to 26, wherein:
Providing a substrate having a first surface and a second surface opposite the first surface;
Preparing an electronic component having a third surface and a fourth surface opposite to the third surface, and having a curved surface at an angle between the fourth surface and the side surface;
Forming an opening in the substrate;
Forming a tapered surface from the first surface toward the second surface at an angle between the inner wall of the opening and the first surface;
Placing the electronic component in the opening with the third surface in the same orientation as the first surface;
including,
A method of manufacturing an electronic component built-in wiring board.
The opening is formed by a laser;
The method of manufacturing an electronic component built-in wiring board according to claim 28.
The substrate has a first layer and a second layer of different materials in this order from the first surface to the second surface,
The laser is applied to the first surface of the substrate so as to penetrate at least the first layer and reach the second layer;
30. The method of manufacturing an electronic component built-in wiring board according to claim 29.
Each of the first layer and the second layer is made of resin,
The second layer includes an inorganic material,
The first layer includes less inorganic material than the second layer or does not include an inorganic material.
The method for manufacturing an electronic component built-in wiring board according to claim 30.
Placing the electronic component in the opening while contacting the curved surface of the electronic component to the tapered surface;
32. The method of manufacturing an electronic component built-in wiring board according to any one of claims 28 to 31.
Forming an insulating layer made of a resin on the substrate and the opening;
Filling the resin constituting the insulating layer between the substrate and the electronic component in the opening;
Curing the filled resin;
including,
33. A method of manufacturing an electronic component built-in wiring board according to any one of claims 28 to 32.
The insulating layer is formed on the substrate and the opening in a semi-cured state,
In filling the resin, by pressing the insulating layer in a semi-cured state, the resin flows out from the insulating layer and flows into the opening.
34. A method of manufacturing an electronic component built-in wiring board according to claim 33.
The opening comprises a hole penetrating the substrate,
Before placing the electronic component in the opening, including closing one opening of the hole with an adhesive sheet,
35. The method of manufacturing an electronic component built-in wiring board according to any one of claims 28 to 34.
In the arrangement of the electronic component, by placing the electronic component into the opening from the side opposite to the closed opening, the electronic component is disposed on the adhesive sheet,
Forming an insulating layer made of a resin on the substrate and the opening on the opposite side of the blocked opening;
Filling the resin constituting the insulating layer between the substrate and the electronic component in the opening;
Removing the adhesive sheet;
After removing the adhesive sheet, curing the filled resin;
including,
36. A method of manufacturing an electronic component built-in wiring board according to claim 35.
Forming a conductor layer having an alignment mark on the substrate before placing the electronic component in the opening;
In the arrangement of the electronic component, the alignment mark is used to position the electronic component.
37. The method of manufacturing an electronic component built-in wiring board according to any one of claims 28 to 36.
The curved surface consists of the surface of the electrode of the electronic component,
38. A method of manufacturing an electronic component built-in wiring board according to any one of claims 28 to 37.
At least the surface of the electrode of the electronic component is made of a plating film,
The method for manufacturing a wiring board with a built-in electronic component according to claim 38.