JP4702029B2 - 同軸型光モジュールの製造方法 - Google Patents
同軸型光モジュールの製造方法 Download PDFInfo
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- JP4702029B2 JP4702029B2 JP2005359012A JP2005359012A JP4702029B2 JP 4702029 B2 JP4702029 B2 JP 4702029B2 JP 2005359012 A JP2005359012 A JP 2005359012A JP 2005359012 A JP2005359012 A JP 2005359012A JP 4702029 B2 JP4702029 B2 JP 4702029B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Description
本発明に係る同軸型光モジュールの製造方法の第1実施形態について、以下に説明する。図1は、本実施形態において用いられる治具1に、同軸型光モジュール10を装着した状態を示す斜視図である。図1を参照すると、本実施形態の治具1は、台座プレート2と、台座プレート2上に設けられた埋込部材3と、埋込部材3上に設けられた上取付基板5及び下取付基板6と、上取付基板5と下取付基板6との間に挟まれた2枚の金属プレート7及び8と、上取付基板5上に設けられた押当部材4とを備える。また、治具1は、押当部材4を押圧するための押圧部9を更に備える。この押圧部9は、例えばトグルクランプ(不図示)といった押圧機構に結合されている。そして、治具1は、埋込部材3と下取付基板6との間、2枚の金属プレート7及び8の間、並びに押当部材4と上取付基板5との間のそれぞれに同軸型光モジュール10のリードピンを挟み込んだ状態で、同軸型光モジュール10の電気的特性の確認に用いられる。
本発明に係る方法の第2実施形態について、以下に説明する。図8は、本実施形態に用いられる治具1aの構成を示す分解斜視図である。この治具1aと上記第1実施形態の治具1との構成上の相違点は、金属プレートの有無、並びに上取付基板及び下取付基板の形状の相違である。すなわち、本実施形態の治具1aは、金属プレート7及び8(図1,図5参照)を備えておらず、上取付基板15及び下取付基板16の形状が、それぞれ上取付基板5(図4(a))及び下取付基板6(図4(b))と異なっている。なお、台座プレート2、埋込部材3、及び押当部材4の形状については、上記第1実施形態と同様なので詳細な説明を省略する。
Claims (6)
- 基準電位用リードピン及び信号伝達用リードピンを有する同軸型光モジュールの製造方法であって、
主面に配線パターンを有し、裏面に第1の金属膜を有する第1の基板と、裏面に第2の金属膜を有する第2の基板とを、前記第1の金属膜及び前記第2の金属膜が互いに対向するように重ね合わせ、
前記第1の金属膜と前記第2の金属膜との間に前記基準電位用リードピンを挟み込み、
前記第1の基板の前記配線パターンと前記信号伝達用リードピンとを接触させた状態で、前記第1の金属膜及び前記第2の金属膜へ基準電位を供給し、前記配線パターンに検査用信号の入力または出力を行う、同軸型光モジュールの製造方法。 - 前記第1の基板の前記裏面及び前記第2の基板の前記裏面のうち少なくとも一方の面に、前記基準電位用リードピンを固定するための溝が形成されている、請求項1に記載の方法。
- 基準電位用リードピン及び信号伝達用リードピンを有する同軸型光モジュールの製造方法であって、
2枚の金属プレートを互いに重ね合わせ該2枚の金属プレートの間に前記基準電位用リードピンを挟み込み、
主面に配線パターンを有する第1の基板の裏面と前記金属プレートの一方とが対向するように前記第1の基板を前記一方の金属プレート上に重ね合わせ、前記第1の基板の前記配線パターンと前記信号伝達用リードピンとを接触させた状態で、前記2枚の金属プレートへ基準電位を供給し、前記配線パターンに検査用信号の入力または出力を行う、同軸型光モジュールの製造方法。 - 少なくとも一方の前記金属プレートに、前記基準電位用リードピンを固定するための溝が形成されている、請求項3に記載の方法。
- 前記第1の基板の前記主面側に樹脂製の押圧部材を配置し、前記押圧部材と前記第1の基板との間に前記信号伝達用リードピンを挟み込んだ状態で前記押圧部材を前記第1の基板に押し当てる、請求項1〜4のいずれか一項に記載の方法。
- 前記押圧部材の前記第1の基板と対向する面に、前記信号伝達用リードピンを固定するための溝が形成されている、請求項5に記載の方法。
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JP2005359012A JP4702029B2 (ja) | 2005-12-13 | 2005-12-13 | 同軸型光モジュールの製造方法 |
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JP2005359012A JP4702029B2 (ja) | 2005-12-13 | 2005-12-13 | 同軸型光モジュールの製造方法 |
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JP2007165536A JP2007165536A (ja) | 2007-06-28 |
JP4702029B2 true JP4702029B2 (ja) | 2011-06-15 |
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JP2005359012A Active JP4702029B2 (ja) | 2005-12-13 | 2005-12-13 | 同軸型光モジュールの製造方法 |
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Families Citing this family (1)
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JP6199683B2 (ja) * | 2013-10-01 | 2017-09-20 | Ritaエレクトロニクス株式会社 | 多層プリント基板のパターン設計手法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62283689A (ja) * | 1986-06-02 | 1987-12-09 | Rohm Co Ltd | 半導体レ−ザの検査装置 |
JPH0459484U (ja) * | 1990-09-28 | 1992-05-21 | ||
JPH04245659A (ja) * | 1991-01-31 | 1992-09-02 | Anritsu Corp | 光半導体の保持具 |
JPH08313586A (ja) * | 1995-05-19 | 1996-11-29 | Advantest Corp | リード型電子デバイス用測定治具の構造 |
JP2003258272A (ja) * | 2002-02-27 | 2003-09-12 | Sumitomo Electric Ind Ltd | 光受信モジュール |
JP2006126138A (ja) * | 2004-11-01 | 2006-05-18 | Anritsu Corp | テストフィクスチャ |
JP2006133179A (ja) * | 2004-11-09 | 2006-05-25 | Anritsu Corp | テストフィクスチャ |
-
2005
- 2005-12-13 JP JP2005359012A patent/JP4702029B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62283689A (ja) * | 1986-06-02 | 1987-12-09 | Rohm Co Ltd | 半導体レ−ザの検査装置 |
JPH0459484U (ja) * | 1990-09-28 | 1992-05-21 | ||
JPH04245659A (ja) * | 1991-01-31 | 1992-09-02 | Anritsu Corp | 光半導体の保持具 |
JPH08313586A (ja) * | 1995-05-19 | 1996-11-29 | Advantest Corp | リード型電子デバイス用測定治具の構造 |
JP2003258272A (ja) * | 2002-02-27 | 2003-09-12 | Sumitomo Electric Ind Ltd | 光受信モジュール |
JP2006126138A (ja) * | 2004-11-01 | 2006-05-18 | Anritsu Corp | テストフィクスチャ |
JP2006133179A (ja) * | 2004-11-09 | 2006-05-25 | Anritsu Corp | テストフィクスチャ |
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