JP4681260B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4681260B2 JP4681260B2 JP2004227884A JP2004227884A JP4681260B2 JP 4681260 B2 JP4681260 B2 JP 4681260B2 JP 2004227884 A JP2004227884 A JP 2004227884A JP 2004227884 A JP2004227884 A JP 2004227884A JP 4681260 B2 JP4681260 B2 JP 4681260B2
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims description 155
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 69
- 238000007789 sealing Methods 0.000 claims description 32
- 229920005989 resin Polymers 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 28
- 230000006870 function Effects 0.000 description 25
- 238000000034 method Methods 0.000 description 22
- 238000007796 conventional method Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000013585 weight reducing agent Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Description
(第一の実施の形態)
本発明の実施の形態の半導体装置を、汎用のUSBコネクタのシリーズAと呼ばれるタイプのものに適用した場合を例として以下に説明する。本実施の形態の半導体装置は、USBコネクタのオス側を例として説明するが、これに限定されない。本実施の形態の半導体装置は、USBコネクタのメス側およびオス側いずれにも適用可能である。
(第二の実施の形態)
図5は、本実施の形態の半導体装置の基板の例を示す断面図である。図6は、図5の半導体装置の基板の上面図である。図7は、図5の半導体装置を封止樹脂で被覆する前の基板の裏面図である。図8は、図5の半導体装置の基板の裏面図である。図9は、図5の半導体装置を使用したUSBコネクタの正面図である。
[1] 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されることを特徴とする半導体装置。
[2] 請求項1の半導体装置が外部との接続時にその半導体装置の一部を接続使用の目的に用いることを特徴とする方法。
[3] 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されている部分を接続目的に保護することを特徴とする製造方法。
[4] 外部との接続を目的とする端子が形成された基板エリアの裏面部に半導体素子及び受動素子が搭載されている部分とそれ以外を同一成型することを特徴とする製造方法。
(実施例)
(比較例1)
(比較例2)
2 受動部品
3 出力端子
5 半導体素子
6 封止樹脂
7a 端子領域
7b 領域
8 ハウジング
Claims (5)
- 汎用のコネクタの外部ラインに電気的に接続する端子と、
前記端子に電気的に接続され、所定の機能を有する回路素子と、
前記端子が配設された端子領域を有する基板と、
を備え、
前記基板の前記端子領域の裏側に位置する領域の内側に前記回路素子が搭載されており、
前記基板の端子が配設された側とは反対の側が樹脂封止されており、
前記基板の前記端子及び前記回路素子を含む部分が前記汎用のコネクタと嵌合する嵌合部を構成していることを特徴とする半導体装置。 - 前記回路素子は、複数積層して前記基板上に搭載されることを特徴とする請求項1に記載の半導体装置。
- 前記基板の前記端子領域の裏側の領域に、半導体素子が搭載されることを特徴とする請求項1又は2に記載の半導体装置。
- 汎用のコネクタの外部ラインに電気的に接続する端子を基板の一方の面の端子領域に配設する工程と、
前記基板の前記端子領域の裏側に位置する領域に回路素子を搭載する工程と、
前記基板の端子が配設された側とは反対の側を封止樹脂によって封止する工程と、を含み、
前記基板の前記端子及び前記回路素子を含む部分を前記汎用のコネクタと嵌合する嵌合部とすることを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記回路素子を前記基板上に複数積層して搭載する工程を含むことを特徴とする請求項4に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004227884A JP4681260B2 (ja) | 2003-11-28 | 2004-08-04 | 半導体装置及びその製造方法 |
Applications Claiming Priority (2)
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JP2003398364 | 2003-11-28 | ||
JP2004227884A JP4681260B2 (ja) | 2003-11-28 | 2004-08-04 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2005183925A JP2005183925A (ja) | 2005-07-07 |
JP4681260B2 true JP4681260B2 (ja) | 2011-05-11 |
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JP2004227884A Active JP4681260B2 (ja) | 2003-11-28 | 2004-08-04 | 半導体装置及びその製造方法 |
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI288315B (en) * | 2004-11-01 | 2007-10-11 | Innodisk Corp | Universal serial bus applied device |
JP4886308B2 (ja) * | 2005-09-16 | 2012-02-29 | 株式会社東芝 | Usbメモリ装置 |
KR101033772B1 (ko) * | 2008-11-21 | 2011-05-13 | 에스티에스반도체통신 주식회사 | Usb 저장장치, 상기 usb 저장장치가 삽입되는 usb소켓 및 상기 usb 저장장치를 형성하기 위한 인쇄회로기판 |
US8724339B2 (en) * | 2009-12-01 | 2014-05-13 | Apple Inc. | Compact media player |
TWI406390B (zh) * | 2010-02-26 | 2013-08-21 | Walton Advanced Eng Inc | High density integrated circuit module structure |
TW201142610A (en) * | 2010-05-28 | 2011-12-01 | Walton Advanced Eng Inc | Data storage device |
KR101450068B1 (ko) * | 2010-06-10 | 2014-10-15 | 에스티에스반도체통신 주식회사 | Usb 메모리 장치 및 이를 포함하는 usb 시스템 |
KR101450067B1 (ko) * | 2010-06-10 | 2014-10-15 | 에스티에스반도체통신 주식회사 | Usb 메모리 장치 및 이를 포함하는 usb 시스템 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63194773U (ja) * | 1987-06-04 | 1988-12-15 | ||
JPH0846881A (ja) * | 1994-07-29 | 1996-02-16 | Matsushita Electric Ind Co Ltd | 固体撮像装置 |
JPH09321200A (ja) * | 1996-05-29 | 1997-12-12 | Niles Parts Co Ltd | 電子回路モジュール装置 |
JP2002015296A (ja) * | 2000-06-30 | 2002-01-18 | Matsushita Electric Ind Co Ltd | メモリカード |
JP2002050721A (ja) * | 2000-08-03 | 2002-02-15 | Hitachi Cable Ltd | 電子装置及びその製造方法 |
-
2004
- 2004-08-04 JP JP2004227884A patent/JP4681260B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63194773U (ja) * | 1987-06-04 | 1988-12-15 | ||
JPH0846881A (ja) * | 1994-07-29 | 1996-02-16 | Matsushita Electric Ind Co Ltd | 固体撮像装置 |
JPH09321200A (ja) * | 1996-05-29 | 1997-12-12 | Niles Parts Co Ltd | 電子回路モジュール装置 |
JP2002015296A (ja) * | 2000-06-30 | 2002-01-18 | Matsushita Electric Ind Co Ltd | メモリカード |
JP2002050721A (ja) * | 2000-08-03 | 2002-02-15 | Hitachi Cable Ltd | 電子装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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JP2005183925A (ja) | 2005-07-07 |
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