JP4678941B2 - Composite semiconductor device - Google Patents

Composite semiconductor device Download PDF

Info

Publication number
JP4678941B2
JP4678941B2 JP2000381029A JP2000381029A JP4678941B2 JP 4678941 B2 JP4678941 B2 JP 4678941B2 JP 2000381029 A JP2000381029 A JP 2000381029A JP 2000381029 A JP2000381029 A JP 2000381029A JP 4678941 B2 JP4678941 B2 JP 4678941B2
Authority
JP
Japan
Prior art keywords
semiconductor device
insulating substrate
heat sink
composite semiconductor
radiating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000381029A
Other languages
Japanese (ja)
Other versions
JP2002184914A (en
Inventor
永吾 福田
Original Assignee
日本インター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本インター株式会社 filed Critical 日本インター株式会社
Priority to JP2000381029A priority Critical patent/JP4678941B2/en
Publication of JP2002184914A publication Critical patent/JP2002184914A/en
Application granted granted Critical
Publication of JP4678941B2 publication Critical patent/JP4678941B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

Description

【0001】
【発明の属する技術分野】
本発明はベーシング後及び経時的変化を経た後の放熱板の反り量を抑制した複合半導体装置に関するものである。
【0002】
【従来の技術】
この種の複合半導体装置の概略構造を図3に示す。
図において、1は複合半導体装置全体を示し、この複合半導体装置1は、その底面に放熱板2を備えている。この放熱板2上に絶縁基板3が半田9により半田付けされ、この絶縁基板3上に半導体ペレット4、外部導出端子5等の電子部品が載置・固着されている。外部導出端子5の他端は蓋体6の透孔7を介して外部に引き出されている。
【0003】
ところで、上記放熱板2の上面には図5に示すように、絶縁基板3の導体パターン3a上に半導体ペレット4が半田付けされるが、絶縁基板3の下面のメタライズ層(図示省略)と放熱板2とも前記のように半田9により半田付けされる。
【0004】
かかる場合に、Al2O3,AlN等のセラミック基板からなる絶縁基板3と、銅材からなる放熱板2とを半田付けすると、両者の熱膨張の差により反りが発生する。この反りの発生方向は図5に示すように、放熱板2の下面中央部が凹状(上方に向かって凸状)になる。
【0005】
上記の状態のままで、図3に示す複合半導体装置1を組み立てる。そして放熱板3の図示を省略した取付孔を利用して他の部材、例えば放熱フィンに取り付けた場合、放熱板3と放熱フィンとの間に隙間が形成されてしまい放熱効果を悪くする。
【0006】
上記の点を改善するため、従来では放熱板2を製作するときに図4に示すように、予め下面の中央部2aを凸状にして反り量S1を制御している。
さらに、絶縁基板3を放熱板2に半田付けした直後の反り量S2(図5参照)は、数日間放置しておくと、該反り量S2は小さくなり、遂には図6に示すように、放熱板2の中央部2aが凸状に変化し反り量S3にて安定する。このようなことを考慮して従来では完成品での放熱板2の反り量S3が最小になるように放熱板2の製作時に逆方向の反り量S1を最初に決めて置くようにしている。
【0007】
【発明が解決しようとする課題】
しかしながら、上記のような処置では次のような問題がある。
すなわち、絶縁基板3を放熱板2に半田付けした後に、100μm以上の反りが反転して加わることになる。放熱板2の下に凸状の最初の状態からベーシング時に第1回目の反転があり、下に凹状となり、さらに経時的変化により下に凸状に反る2回目の反転がある。この反転のため絶縁基板3に機械的ストレスが加わり、延いては絶縁基板3上の半導体ペレット4にも悪影響を与え、複合半導体装置1の特性が劣化するおそれがある。
【0008】
【発明の目的】
本発明は上記のような課題を解決するためになされたもので、放熱板の最終的な反り量S3を小さくすると共に、反りの変化量を相対的に小さくして絶縁基板の割れや半導体ペレットの悪影響を防止した複合半導体装置を提供することを目的とするものである。
【0009】
【課題を解決するための手段】
本発明の複合半導体装置は、放熱板上に半田付けにより半導体ペレット等の電子部品が載置される絶縁基板を有する複合半導体装置において、
上記放熱板に、該放熱板自体の反り量を小さくするためのスリット等を設けたことを特徴とするものである。
【0010】
【作用】
本発明の複合半導体装置は、放熱板の絶縁基板が載置・固定される隣接位置にスリットを形成したので、該スリットによりベーシング時及び経時的変化時に加わる応力が緩和され、初期状態に戻るまでの反りの変化量が少なくなる。このため、絶縁基板の割れや半導体ペレットに与える機械的ストレス等の悪影響を最小限に留めることができる。
【0011】
【実施例】
以下に、本発明の実施例を、図を参照して説明する。
図1は本発明の複合半導体装置に使用する放熱板の平面図、図2は該放熱板上に絶縁基板を載置・固着させた状態の縦断面図である。
これらの図において、12は銅材により形成した放熱板である。
なお、この実施例では板厚5mm、寸法186mm×93mmのものを使用した。
【0012】
図1および図2でわかるように、上記の放熱板12の複数箇所にスリット20を上記絶縁基板13,13の巾寸法程度で放熱板12を貫通するよう設ける。このスリット20の位置は、互いに隣接する絶縁基板13,13の間とする。なお、この実施例で該スリット20の寸法は、5mm×70mmとした。また、絶縁基板13の寸法は、50mm×70mmとした。上記放熱板12の外周部には放熱フィン等の外部部材に取り付けるための複数の取付孔21が設けられている。
【0013】
次に、上記放熱板12に対して、下にS1(図4参照)=100μm程度凸状になるようにプレス機械等によりプリベンド加工を施す。
次いで、上記放熱板12上に絶縁基板13を、半田9を介して載置・固着させ、さらに、絶縁基板13上に図5と同様に半導体ペレット4を半田により固着させる。このベーシング工程により、放熱板12は図2に示すように下に凹状に反る。
【0014】
しかし、その反り量S2は、スリット20の形成により緩和され上記の実施例の場合、S2=1mm程度であった。
その後、上記放熱板12を自然環境下に48時間放置し、経時的変化を観測したところ、図6と同様に下に凸状に反っていたが、S3=0.3mm程度であった。
【0015】
上記の現象を解析すると、概略次のようなことである。
すなわち、ベーシング工程後の放熱板12は下に凹状になっていて、その時点では絶縁基板13と放熱板12との接続部である半田層に残留応力が存在している。その残留応力が半田のすべり現象により時間と共に消去され、最終的にプリベンド時の形状に戻って下に凸状に反るが、スリット20を形成しておくことにより最初のベーシング時の応力、その後の経時的変化時の応力が共に緩和され反り量が減少すると考えられる。
【0016】
上記放熱板12は、図3に示した両端開口の絶縁ケース10の一方の開口端に固定される。この場合、絶縁ケース10の内部にゲル状物質等を充填する際には、上記放熱板12に形成したスリット20を塞ぐ閉塞用部材(図示せず)を設けることにより絶縁ケース10外へ該ゲル状物質等が流出するのを防止することができる。
【0017】
【発明の効果】
以上のように本発明によれば、放熱板の所定位置に絶縁基板の巾寸法程度の放熱板を貫通するスリットを設けたので、複合半導体装置の製作過程で生じる放熱板の反り量を、絶縁基板の巾に対応して相対的に小さくすることができる。そのため、放熱板上に載置・固定される絶縁基板の割れ及び該絶縁基板上に載置・固定される半導体ペレットに与える機械的ストレスを効果的に減少させることができるなどの効果がある。
【図面の簡単な説明】
【図1】本発明の複合半導体装置に使用する放熱板の平面図である。
【図2】上記放熱板の縦断面図である。
【図3】従来の複合半導体装置の概略構造を示す縦断面図である。
【図4】上記複合半導体装置に使用するプリベンドした絶縁板の側面図である。
【図5】絶縁基板を載置・固着させたベーシング工程後の上記絶縁基板の側面図である。
【図6】経時的変化後の上記絶縁基板の側面図である。
【符号の説明】
1 複合半導体装置
9 半田
12 放熱板
13 絶縁基板
20 スリット
21 取付孔
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a composite semiconductor device that suppresses the amount of warping of a heat sink after basing and after a change with time.
[0002]
[Prior art]
A schematic structure of this type of composite semiconductor device is shown in FIG.
In the figure, reference numeral 1 denotes the entire composite semiconductor device, and this composite semiconductor device 1 has a heat sink 2 on its bottom surface. An insulating substrate 3 is soldered onto the heat radiating plate 2 with solder 9, and electronic components such as a semiconductor pellet 4 and an external lead-out terminal 5 are mounted and fixed on the insulating substrate 3. The other end of the external lead-out terminal 5 is drawn out through the through hole 7 of the lid body 6.
[0003]
By the way, as shown in FIG. 5, the semiconductor pellet 4 is soldered onto the conductive pattern 3a of the insulating substrate 3 on the upper surface of the heat radiating plate 2. However, the metallized layer (not shown) on the lower surface of the insulating substrate 3 The plate 2 is also soldered by the solder 9 as described above.
[0004]
In this case, when the insulating substrate 3 made of a ceramic substrate such as Al2O3 or AlN and the heat radiating plate 2 made of copper are soldered, warpage occurs due to the difference in thermal expansion between the two. As shown in FIG. 5, the warp is generated in such a manner that the central portion of the lower surface of the heat radiating plate 2 is concave (convex upward).
[0005]
The composite semiconductor device 1 shown in FIG. 3 is assembled in the above state. And when it attaches to another member, for example, a radiation fin, using the mounting hole which illustration of the heat sink 3 was abbreviate | omitted, a clearance gap will be formed between the heat sink 3 and a radiation fin, and the heat dissipation effect will worsen.
[0006]
In order to improve the above point, conventionally, when the heat radiating plate 2 is manufactured, as shown in FIG. 4, the center portion 2a of the lower surface is made convex in advance to control the warpage amount S1.
Furthermore, the warpage amount S2 (see FIG. 5) immediately after the insulating substrate 3 is soldered to the heat sink 2 is reduced if left for several days, and finally, as shown in FIG. The central portion 2a of the heat radiating plate 2 changes to a convex shape and is stabilized at the warp amount S3. Considering this, conventionally, the amount of warpage S1 in the reverse direction is first determined and set when manufacturing the heat sink 2 so that the amount of warpage S3 of the heat sink 2 in the finished product is minimized.
[0007]
[Problems to be solved by the invention]
However, the above treatment has the following problems.
That is, after soldering the insulating substrate 3 to the heat sink 2, warping of 100 μm or more is reversed and added. There is a first inversion at the time of basing from the initial state of the convex shape below the heat sink 2, a concave shape at the bottom, and a second inversion that warps downward due to changes over time. Due to this inversion, mechanical stress is applied to the insulating substrate 3, which may adversely affect the semiconductor pellet 4 on the insulating substrate 3 and may deteriorate the characteristics of the composite semiconductor device 1.
[0008]
OBJECT OF THE INVENTION
The present invention has been made to solve the above-described problems. The final warpage amount S3 of the heat sink is reduced, and the change amount of the warpage is relatively reduced so that cracks in the insulating substrate and semiconductor pellets are obtained. An object of the present invention is to provide a composite semiconductor device in which the adverse effects of the above are prevented.
[0009]
[Means for Solving the Problems]
The composite semiconductor device of the present invention is a composite semiconductor device having an insulating substrate on which electronic components such as semiconductor pellets are placed by soldering on a heat sink.
The heat radiating plate is provided with a slit or the like for reducing the amount of warpage of the heat radiating plate itself.
[0010]
[Action]
In the composite semiconductor device of the present invention, since the slit is formed at the adjacent position where the insulating substrate of the heat sink is placed and fixed, the stress applied at the time of basing and change with time is relieved by the slit, and until the initial state is restored. The amount of change in warpage is reduced. For this reason, adverse effects such as cracking of the insulating substrate and mechanical stress applied to the semiconductor pellet can be minimized.
[0011]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view of a heat sink used in the composite semiconductor device of the present invention, and FIG. 2 is a vertical cross-sectional view of a state in which an insulating substrate is placed and fixed on the heat sink.
In these figures, 12 is a heat sink made of a copper material.
In this example, a plate having a thickness of 5 mm and dimensions of 186 mm × 93 mm was used.
[0012]
As seen in FIGS. 1 and 2, the slits 20 at a plurality of positions of the heat radiating plate 12, provided so as to penetrate through the heat radiating plate 12 at about the width dimension of the insulating substrate 13. The position of the slit 20 is between the insulating substrates 13 and 13 adjacent to each other. In this example, the dimension of the slit 20 was 5 mm × 70 mm. The dimension of the insulating substrate 13 was 50 mm × 70 mm. A plurality of mounting holes 21 for mounting to an external member such as a heat radiating fin are provided on the outer peripheral portion of the heat radiating plate 12.
[0013]
Next, the heat radiating plate 12 is subjected to pre-bending with a press machine or the like so as to have a downward convex shape of S1 (see FIG. 4) = 100 μm.
Next, the insulating substrate 13 is placed on and fixed to the heat radiating plate 12 via the solder 9, and the semiconductor pellet 4 is fixed to the insulating substrate 13 by soldering in the same manner as in FIG. By this basing process, the heat sink 12 warps downwardly in a concave shape as shown in FIG.
[0014]
However, the warpage amount S2 is alleviated by the formation of the slit 20, and in the case of the above embodiment, S2 is about 1 mm.
Thereafter, the heat radiating plate 12 was allowed to stand in a natural environment for 48 hours, and a change with time was observed. As a result, it was warped downward like FIG. 6, but S3 = about 0.3 mm.
[0015]
When the above phenomenon is analyzed, the outline is as follows.
That is, the heat sink 12 after the basing process is recessed downward, and at that time, residual stress exists in the solder layer that is the connection portion between the insulating substrate 13 and the heat sink 12. The residual stress is erased with time due to the sliding phenomenon of the solder, and finally returns to the shape at the time of pre-bending and warps downward, but by forming the slit 20, the stress at the time of the first basing, and thereafter It is considered that the stress at the time of the change with time is alleviated and the amount of warpage decreases.
[0016]
The heat radiating plate 12 is fixed to one opening end of the insulating case 10 having both end openings shown in FIG. In this case, when the inside of the insulating case 10 is filled with a gel-like substance or the like, a sealing member (not shown) that closes the slit 20 formed in the heat radiating plate 12 is provided to the outside of the insulating case 10. It is possible to prevent the spilled material and the like from flowing out.
[0017]
【The invention's effect】
As described above, according to the present invention, since the slit penetrating the heat sink having the width of the insulating substrate is provided at a predetermined position of the heat sink, the amount of warp of the heat sink generated in the manufacturing process of the composite semiconductor device is insulated. It can be made relatively small corresponding to the width of the substrate. Therefore, there is an effect that it is possible to effectively reduce cracking of the insulating substrate placed / fixed on the heat sink and mechanical stress applied to the semiconductor pellet placed / fixed on the insulating substrate.
[Brief description of the drawings]
FIG. 1 is a plan view of a heat sink used in a composite semiconductor device of the present invention.
FIG. 2 is a longitudinal sectional view of the heat radiating plate.
FIG. 3 is a longitudinal sectional view showing a schematic structure of a conventional composite semiconductor device.
FIG. 4 is a side view of a pre-bended insulating plate used in the composite semiconductor device.
FIG. 5 is a side view of the insulating substrate after a basing process in which the insulating substrate is placed and fixed.
FIG. 6 is a side view of the insulating substrate after change with time.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Composite semiconductor device 9 Solder 12 Heat sink 13 Insulating substrate 20 Slit 21 Mounting hole

Claims (3)

放熱板上に半田付けにより半導体ペレット等の電子部品が載置される絶縁基板を有する複合半導体装置において、上記放熱板に、放熱板自体の反り量を小さくするためのスリットを、上記絶縁基板の巾寸法程度で放熱板を貫通するよう、互いに隣接する絶縁基板の間に設けたことを特徴とする複合半導体装置。In the composite semiconductor device having an insulating substrate on which an electronic component such as a semiconductor pellet is mounted by soldering to the heat radiating plate, to the heat radiating plate, a slit for reducing the warpage amount of the heat sink itself, of the insulating substrate A composite semiconductor device characterized in that it is provided between insulating substrates adjacent to each other so as to penetrate a heat sink with a width of about. 上記スリットが、上記絶縁基板が配置される領域を挟んで放熱板の複数箇所に形成されていることを特徴とする請求項1に記載の複合半導体装置。  2. The composite semiconductor device according to claim 1, wherein the slit is formed at a plurality of locations of the heat sink across a region where the insulating substrate is disposed. 上記スリットを塞ぐ閉塞用部材を有することを特徴とする請求項1又は請求項2に記載の複合半導体装置。  The composite semiconductor device according to claim 1, further comprising a closing member that closes the slit.
JP2000381029A 2000-12-14 2000-12-14 Composite semiconductor device Expired - Lifetime JP4678941B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000381029A JP4678941B2 (en) 2000-12-14 2000-12-14 Composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000381029A JP4678941B2 (en) 2000-12-14 2000-12-14 Composite semiconductor device

Publications (2)

Publication Number Publication Date
JP2002184914A JP2002184914A (en) 2002-06-28
JP4678941B2 true JP4678941B2 (en) 2011-04-27

Family

ID=18849115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000381029A Expired - Lifetime JP4678941B2 (en) 2000-12-14 2000-12-14 Composite semiconductor device

Country Status (1)

Country Link
JP (1) JP4678941B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031738A (en) * 2001-07-18 2003-01-31 Fuji Electric Co Ltd Semiconductor device
JP4467380B2 (en) 2004-08-10 2010-05-26 富士通株式会社 Semiconductor package, printed circuit board on which semiconductor package is mounted, and electronic apparatus having such printed circuit board
DE102011016566A1 (en) 2011-03-07 2012-09-13 Osram Opto Semiconductors Gmbh Lead frame for optoelectronic components and method for producing optoelectronic components
US9129932B2 (en) * 2011-06-27 2015-09-08 Rohm Co., Ltd. Semiconductor module
JP6146732B2 (en) * 2013-01-18 2017-06-14 Shマテリアル株式会社 Semiconductor device mounting substrate and manufacturing method thereof
DE102015100025A1 (en) 2015-01-05 2016-07-07 Osram Opto Semiconductors Gmbh leadframe

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61203700A (en) * 1985-03-07 1986-09-09 キヤノン株式会社 Electronic circuit apparatus
JPH0563053U (en) * 1992-01-31 1993-08-20 太陽誘電株式会社 Hybrid integrated circuit board
JPH0770651B2 (en) * 1992-11-30 1995-07-31 日本電気株式会社 Semiconductor package
JP3094768B2 (en) * 1994-01-11 2000-10-03 富士電機株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2002184914A (en) 2002-06-28

Similar Documents

Publication Publication Date Title
CN100438007C (en) Interconnecting substrate and semiconductor device
JP3353508B2 (en) Printed wiring board and electronic device using the same
JP2003051568A (en) Semiconductor device
JP4678941B2 (en) Composite semiconductor device
US5760466A (en) Semiconductor device having improved heat resistance
US20060138654A1 (en) Semiconductor device
JP2009252894A (en) Semiconductor device
JP3807639B2 (en) Heat sink and composite semiconductor device using the same
JP2007103853A (en) Semiconductor device
KR102107034B1 (en) Printed circuit board, semiconductor package having the same and method for manufacturing the same
JP5381175B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2001326429A (en) Printed wiring board
US11166368B2 (en) Printed circuit board and semiconductor package including the same
WO2017032334A1 (en) Method for soldering chip on metallic-ceramic composite board and metallic-ceramic composite board for soldering chip thereon
KR100691057B1 (en) Packaging for semiconductor components and method for producing the same
JPH10107176A (en) Method and structure for connecting electronic part and substrate, and solder bump forming method in them
JP2000183108A (en) Semiconductor integrated circuit device and its manufacture
JP2558574B2 (en) Semiconductor device
KR100714620B1 (en) Printed circuit board having means for preventing warpage
JPH10270830A (en) Board for electronic part
JP2002033555A (en) Multiple-piece ceramic substrate
US8383954B2 (en) Warpage preventing substrates
JPS58157147A (en) Hybrid integrated circuit substrate
JPS6139554A (en) Resin sealed type semiconductor device
KR20070052044A (en) Substrate formed protect layer with difference of thickness and semiconductor package using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070723

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091215

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20100107

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100309

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100428

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110201

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110201

R150 Certificate of patent or registration of utility model

Ref document number: 4678941

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140210

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term