JPH0563053U - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPH0563053U JPH0563053U JP1047692U JP1047692U JPH0563053U JP H0563053 U JPH0563053 U JP H0563053U JP 1047692 U JP1047692 U JP 1047692U JP 1047692 U JP1047692 U JP 1047692U JP H0563053 U JPH0563053 U JP H0563053U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- integrated circuit
- heat dissipation
- hybrid integrated
- dissipation plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
(57)【要約】 (修正有)
【目的】 絶縁基板に放熱板を張り合わせた混成集積回
路基板において、絶縁基板の熱応力による破損を防止す
る。
【構成】 回路配線が形成された絶縁基板1に金属製の
放熱板9を張り合わせ、絶縁基板1の回路配線に接続さ
れた半導体部品2の外装面を放熱板9に接合する。この
放熱板9の幅方向にスリット11が設けられているた
め、温度上昇により、放熱板9が膨張しようとすると
き、張り合わせた絶縁基板1との長手方向の熱膨張の違
いが前記スリット11で吸収される。このため、絶縁基
板1に生じる熱応力が緩和され、絶縁基板1に大きな熱
応力が生じない。
(57) [Summary] (Corrected) [Purpose] To prevent damage to the insulating substrate due to thermal stress in a hybrid integrated circuit substrate in which a heat sink is attached to the insulating substrate. [Structure] A heat sink 9 made of metal is attached to an insulating substrate 1 on which circuit wiring is formed, and the exterior surface of a semiconductor component 2 connected to the circuit wiring of the insulating substrate 1 is bonded to the heat sink 9. Since the slits 11 are provided in the width direction of the heat dissipation plate 9, when the heat dissipation plate 9 tries to expand due to a temperature rise, the difference in thermal expansion in the longitudinal direction from the insulating substrate 1 bonded together is due to the slit 11. Be absorbed. Therefore, the thermal stress generated in the insulating substrate 1 is relaxed, and a large thermal stress does not occur in the insulating substrate 1.
Description
【0001】[0001]
本考案は、パワートランジスタやFET等の半導体部品を用いた高周波電力増 幅器等において、前記半導体部品を冷却するための放熱板を具備した混成集積回 路基板に関する。 The present invention relates to a high frequency power amplifier using semiconductor components such as power transistors and FETs and the like, and to a hybrid integrated circuit board provided with a heat dissipation plate for cooling the semiconductor components.
【0002】[0002]
従来、放熱量の多い半導体部品を搭載した混成集積回路基板は、発熱によって 回路機能に支障を来す恐れを軽減する為に、前記半導体部品の外装体を放熱板に 接触させて、放熱し易くしている。例えば、パワ−トランジスタ等発熱量の多い 半導体部品は、その半導体部品の外装に放熱効果を助ける放熱板が接合される。 Conventionally, a hybrid integrated circuit board that mounts a semiconductor component with a large amount of heat dissipation has been designed to reduce the risk of heat generation impairing the circuit function, by allowing the outer casing of the semiconductor component to come into contact with a heat dissipation plate to facilitate heat dissipation. is doing. For example, in a semiconductor component such as a power transistor that generates a large amount of heat, a heat dissipation plate that helps the heat dissipation effect is joined to the exterior of the semiconductor component.
【0003】 これらの発熱し易い半導体部品を搭載した混成集積回路基板は、例えば従来例 を示す図3と図4に示すようなものが知られている。すなわち、図3と図4で示 された混成集積回路基板には、発熱量の多いパワ−トランジスタ等の半導体部品 2、2…が2個用いられ、これらの半導体部品2、2…が搭載される絶縁基板1 としては、例えばアルミナ基板やガラスエポキシ樹脂基板等が用いられ、その前 記半導体部品2、2…の搭載位置に予め貫通孔3’、3’が形成されている。ま た、絶縁基板1の一方の主面には導電体パターン等により回路配線20が形成さ れ、他方の主面には一面に導体膜5が形成されている。As the hybrid integrated circuit board on which these semiconductor components that easily generate heat are mounted, for example, those shown in FIGS. 3 and 4 showing a conventional example are known. That is, in the hybrid integrated circuit board shown in FIGS. 3 and 4, two semiconductor components 2, 2, ... Such as power transistors that generate a large amount of heat are used, and these semiconductor components 2, 2 ,. As the insulating substrate 1, for example, an alumina substrate or a glass epoxy resin substrate is used, and through holes 3 ', 3'are formed in advance at the mounting positions of the semiconductor components 2, 2 ,. In addition, the circuit wiring 20 is formed by a conductor pattern or the like on one main surface of the insulating substrate 1, and the conductor film 5 is formed on one surface of the other main surface.
【0004】 前記半導体部品2、2…は、前記絶縁基板1の貫通孔3’、3’に収納されて おり、他の電子部品4、4…は、絶縁基板1の一方の主面に搭載されている。絶 縁基板1の一方の辺には、リードランド8、8…が形成され、各々のリードラン ド8、8…にリ−ド端子7、7…の一端が半田付けされ、絶縁基板1の側方に導 出されている。The semiconductor components 2, 2, ... Are housed in the through holes 3 ′, 3 ′ of the insulating substrate 1, and the other electronic components 4, 4, ... Are mounted on one main surface of the insulating substrate 1. Has been done. The lead lands 8, 8 ... Are formed on one side of the insulating substrate 1, and one end of the lead terminals 7, 7 ... Is soldered to each of the lead lands 8, 8 ,. Have been guided to.
【0005】 金属製の放熱板9’は、前記基板とほぼ同一幅寸法の略矩形状のもので、長さ は基板より少し長めに形成されている。その両端部は、筐体等にねじ止めする為 の凹部を有する固定端部10、10となっている。このような放熱板9’が前記 絶縁基板1の他方の主面の一面に形成された導体膜5と重ねて半田付けされると 共に、貫通孔3’、3’に収納された半導体部品2、2の外装体が放熱板9’に 接合される。この後、絶縁基板1上の所定の部分に外部接続用のリード端子を接 続して、混成集積回路装置として用いられる。The metal heat dissipation plate 9'has a substantially rectangular shape having substantially the same width dimension as the substrate, and is formed to have a length slightly longer than the substrate. Both ends thereof are fixed ends 10 and 10 having recesses for screwing to a housing or the like. Such a heat dissipation plate 9'is soldered over the conductor film 5 formed on one surface of the other main surface of the insulating substrate 1, and at the same time, the semiconductor component 2 housed in the through holes 3 ', 3'. The two outer casings are joined to the heat dissipation plate 9 '. After that, lead terminals for external connection are connected to predetermined portions on the insulating substrate 1 to be used as a hybrid integrated circuit device.
【0006】[0006]
しかしながら、このような前記放熱板9’は熱伝導性の良好な金属製であり、 また絶縁基板1はアルミナ基板やガラスエポキシ樹脂基板であるため、それらの 熱膨張係数の違いが大きい。このため、図4に二点鎖線で示すように、前記放熱 板9’が温度上昇すると膨張し、熱膨張係数の低い絶縁基板1側に反ろうとする ため、放熱板9’と絶縁基板1とに熱応力が生じる。このため、脆い絶縁基板1 にクラックが入り、回路の断線や絶縁性の低下等をもたらし、回路の故障等のト ラブルを招く。 本考案の目的は、前記従来の混成集積回路装置の課題に鑑み、絶縁基板に熱応 力が生じない混成集積回路基板を提供する事にある。 However, since the heat dissipation plate 9'is made of metal having good thermal conductivity, and the insulating substrate 1 is an alumina substrate or a glass epoxy resin substrate, the difference in thermal expansion coefficient between them is large. Therefore, as shown by the chain double-dashed line in FIG. 4, when the heat radiation plate 9 ′ rises in temperature, the heat radiation plate 9 ′ expands and tends to warp to the side of the insulating substrate 1 having a low coefficient of thermal expansion. Thermal stress occurs in the. As a result, the brittle insulating substrate 1 is cracked, which leads to disconnection of the circuit, deterioration of insulation, and the like, which leads to trouble such as circuit failure. An object of the present invention is to provide a hybrid integrated circuit board in which the insulating substrate does not generate thermal response in view of the problems of the conventional hybrid integrated circuit device.
【0007】[0007]
すなわち本発明では、前記目的を達成するため、回路配線が形成された絶縁基 板1と、該絶縁基板1の回路配線に接続された半導体部品2と、前記絶縁基板1 に張り合わせられると共に、前記半導体部品2の外装面が接合された放熱板9と を有する混成集積回路基板において、該放熱板9の幅方向にスリット11を設け たことを特徴とする混成集積回路基板を提供する。 That is, in the present invention, in order to achieve the above-mentioned object, an insulating substrate 1 on which circuit wiring is formed, a semiconductor component 2 connected to the circuit wiring of the insulating substrate 1, and the insulating substrate 1 are bonded together, and Provided is a hybrid integrated circuit board having a heat dissipation plate 9 to which the exterior surface of the semiconductor component 2 is joined, wherein a slit 11 is provided in the width direction of the heat dissipation plate 9.
【0008】[0008]
本考案による混成集積回路基板では、放熱板9の幅方向にスリット11が設け られているため、温度上昇により、放熱板9が膨張しようとするとき、張り合わ せた絶縁基板1との長手方向の熱膨張の違いが前記スリット11で吸収される。 このため、絶縁基板1に生じる熱応力が緩和され、絶縁基板1に大きな熱応力が 生じない。 In the hybrid integrated circuit board according to the present invention, since the slits 11 are provided in the width direction of the heat dissipation plate 9, when the heat dissipation plate 9 is about to expand due to temperature rise, The difference in thermal expansion is absorbed by the slit 11. For this reason, the thermal stress generated in the insulating substrate 1 is relaxed, and a large thermal stress is not generated in the insulating substrate 1.
【0009】[0009]
次に、図面を参照しながら、本考案の実施例について具体的に説明する。 図1及び図2に示す混成集積回路基板は、既に従来例として示した図3及び図 4の混成集積回路基板と基本的に共通しており、同じ部分は同じ符号で示してあ る。すなわち、絶縁基板1としては、例えばアルミナ基板やガラスエポキシ樹脂 基板等が用いられ、同絶縁基板1の半導体部品2、2…が搭載される位置に予め 貫通孔3’、3’が形成されている。また、絶縁基板1の一方の主面には導電体 パターン等により回路配線20が形成され、他方の主面には一面に導体膜5が形 成されている。 Next, an embodiment of the present invention will be specifically described with reference to the drawings. The hybrid integrated circuit boards shown in FIGS. 1 and 2 are basically common to the hybrid integrated circuit boards of FIGS. 3 and 4 already shown as a conventional example, and the same portions are denoted by the same reference numerals. That is, as the insulating substrate 1, for example, an alumina substrate or a glass epoxy resin substrate is used, and the through holes 3 ′, 3 ′ are formed in advance on the insulating substrate 1 at the positions where the semiconductor components 2, 2, ... Are mounted. There is. Also, the circuit wiring 20 is formed on one main surface of the insulating substrate 1 by a conductor pattern or the like, and the conductor film 5 is formed on one surface of the other main surface.
【0010】 前記半導体部品2、2…は、前記絶縁基板1の貫通孔3’、3’に収納されお り、他の電子部品4、4…は、絶縁基板1の一方の主面に搭載されている。絶縁 基板1の一方の辺には、リードランド8、8…が形成され、各々のリードランド 8、8…にリ−ド端子7、7…の一端が半田付けされ、絶縁基板1の側方に導出 されている。The semiconductor components 2, 2, ... Are housed in the through holes 3 ′, 3 ′ of the insulating substrate 1, and the other electronic components 4, 4, ... Are mounted on one main surface of the insulating substrate 1. Has been done. The lead lands 8, 8 ... Are formed on one side of the insulating substrate 1, and one end of the lead terminals 7, 7 ... Is soldered to each of the lead lands 8, 8 ... Have been derived from.
【0011】 金属製の放熱板9は、前記基板とほぼ同一幅寸法の略矩形状のもので、長さは 基板より少し長めに形成されている。その両端部は、筐体等にねじ止めする為の 凹部を有する固定端部10、10となっている。また、この放熱板9の前記固定 端部10、10より中央部側に3本のスリット11、11…が設けられている。 これらスリットは、放熱板の両辺側からその幅方向に亙って交互に切り込まれて おり、その切込み深さは放熱板9の幅の半分より僅かに長い。The metal heat dissipation plate 9 has a substantially rectangular shape with a width dimension substantially the same as that of the substrate, and is formed to be a little longer than the substrate. Both ends thereof are fixed ends 10 and 10 having recesses for screwing to a housing or the like. Further, three slits 11, 11, ... Are provided on the central portion side of the fixed ends 10, 10 of the heat dissipation plate 9. These slits are alternately cut from both sides of the heat sink in the width direction, and the depth of the slit is slightly longer than half the width of the heat sink 9.
【0012】 このような放熱板9が前記絶縁基板1の他方の主面の一面に形成された導体膜 5と重ねて半田付けされると共に、貫通孔3’、3’に収納された半導体部品2 、2の外装体が放熱板9に接合される。この場合、前記スリット11、11…が 形成されたエリアは、絶縁基板1と接合される。この後、絶縁基板1上の所定の 部分に外部接続用のリード端子が接続され、混成集積回路装置が完成する。 なお、前記実施例では、放熱板9にその幅の約半分の切込み深さのスリット1 1、11…を3本設けたが、その本数や切込み深さは、放熱板9のサイズや予想 される温度上昇により適宜選択すべきであり、必ず1本以上あればよい。The heat dissipation plate 9 is soldered to the conductor film 5 formed on one surface of the other main surface of the insulating substrate 1 so as to be overlaid and soldered, and the semiconductor parts housed in the through holes 3 ′, 3 ′. The outer casings 2 and 2 are joined to the heat dissipation plate 9. In this case, the area where the slits 11, 11 ... Are formed is bonded to the insulating substrate 1. After that, lead terminals for external connection are connected to predetermined portions on the insulating substrate 1 to complete the hybrid integrated circuit device. In the above-described embodiment, the heat sink 9 is provided with three slits 11, 11, ... With a depth of cut that is about half the width of the heat sink 9. However, the number and depth of the slits are the size of the heat sink 9 and the expected depth. It should be appropriately selected depending on the temperature rise, and it is sufficient that there is at least one.
【0013】[0013]
以上説明した通り、本考案によれば、放熱板9が温度上昇したときでも、絶縁 基板1に大きな熱応力が生じないため、絶縁基板1にクラックが生じるのを防止 できる。よって、放熱板9の温度上昇に伴う回路の故障等が未然に防止できる信 頼性の高い投影面積の小さな混成集積回路基板が提供できる効果が得られる。 As described above, according to the present invention, even when the temperature of the heat dissipation plate 9 rises, a large thermal stress does not occur in the insulating substrate 1, so that the insulating substrate 1 can be prevented from cracking. Therefore, it is possible to provide a highly reliable hybrid integrated circuit board having a small projected area and capable of preventing circuit failure or the like due to the temperature rise of the heat sink 9.
【図1】本考案の実施例を示す混成集積回路基板の斜視
図である。FIG. 1 is a perspective view of a hybrid integrated circuit board showing an embodiment of the present invention.
【図2】同実施例を示す混成集積回路基板の底面図であ
る。FIG. 2 is a bottom view of the hybrid integrated circuit board showing the embodiment.
【図3】従来例を示す混成集積回路基板の斜視図であ
る。FIG. 3 is a perspective view of a hybrid integrated circuit board showing a conventional example.
【図4】同混成集積回路基板の縦断側面図である。FIG. 4 is a vertical sectional side view of the hybrid integrated circuit board.
1 絶縁基板 2 発熱性の半導体部品 3 貫通孔 4 一般の電子部品 9 放熱板 11 スリット DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Heat-generating semiconductor component 3 Through hole 4 General electronic component 9 Heat sink 11 Slit
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【手続補正書】[Procedure amendment]
【提出日】平成4年11月26日[Submission date] November 26, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】全図[Correction target item name] All drawings
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図1】 [Figure 1]
【図2】 [Fig. 2]
【図3】 [Figure 3]
【図4】 [Figure 4]
Claims (1)
と、該絶縁基板(1)の回路配線に接続された半導体部
品(2)と、前記絶縁基板(1)に張り合わせられると
共に、前記半導体部品2の外装面が接合された放熱板
(9)とを有する混成集積回路基板において、該放熱板
(9)の幅方向にスリット(11)を設けたことを特徴
とする混成集積回路基板。1. An insulating substrate (1) on which circuit wiring is formed
A semiconductor component (2) connected to the circuit wiring of the insulating substrate (1), and a heat dissipation plate (9) bonded to the insulating substrate (1) and having an exterior surface of the semiconductor component 2 bonded thereto. A hybrid integrated circuit board having a slit (11) in the width direction of the heat dissipation plate (9).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1047692U JPH0563053U (en) | 1992-01-31 | 1992-01-31 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1047692U JPH0563053U (en) | 1992-01-31 | 1992-01-31 | Hybrid integrated circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0563053U true JPH0563053U (en) | 1993-08-20 |
Family
ID=11751208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1047692U Pending JPH0563053U (en) | 1992-01-31 | 1992-01-31 | Hybrid integrated circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0563053U (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08330486A (en) * | 1995-05-31 | 1996-12-13 | Nec Yamagata Ltd | Semiconductor device, and its manufacture |
JP2002184914A (en) * | 2000-12-14 | 2002-06-28 | Nippon Inter Electronics Corp | Compound semiconductor device |
JP2012033596A (en) * | 2010-07-29 | 2012-02-16 | Kyocera Corp | Substrate for semiconductor device and semiconductor device equipped with the same |
JP2012529853A (en) * | 2009-06-08 | 2012-11-22 | パワーウェーブ テクノロジーズ インコーポレーテッド | Amplitude and phase compensated multi-element antenna array with adaptive predistortion for wireless networks |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61203700A (en) * | 1985-03-07 | 1986-09-09 | キヤノン株式会社 | Electronic circuit apparatus |
JPH0278255A (en) * | 1988-09-14 | 1990-03-19 | Hitachi Ltd | Resin-sealed semiconductor device |
-
1992
- 1992-01-31 JP JP1047692U patent/JPH0563053U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61203700A (en) * | 1985-03-07 | 1986-09-09 | キヤノン株式会社 | Electronic circuit apparatus |
JPH0278255A (en) * | 1988-09-14 | 1990-03-19 | Hitachi Ltd | Resin-sealed semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08330486A (en) * | 1995-05-31 | 1996-12-13 | Nec Yamagata Ltd | Semiconductor device, and its manufacture |
JP2002184914A (en) * | 2000-12-14 | 2002-06-28 | Nippon Inter Electronics Corp | Compound semiconductor device |
JP2012529853A (en) * | 2009-06-08 | 2012-11-22 | パワーウェーブ テクノロジーズ インコーポレーテッド | Amplitude and phase compensated multi-element antenna array with adaptive predistortion for wireless networks |
JP2012033596A (en) * | 2010-07-29 | 2012-02-16 | Kyocera Corp | Substrate for semiconductor device and semiconductor device equipped with the same |
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Legal Events
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Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980414 |