JP2003031738A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003031738A
JP2003031738A JP2001218590A JP2001218590A JP2003031738A JP 2003031738 A JP2003031738 A JP 2003031738A JP 2001218590 A JP2001218590 A JP 2001218590A JP 2001218590 A JP2001218590 A JP 2001218590A JP 2003031738 A JP2003031738 A JP 2003031738A
Authority
JP
Japan
Prior art keywords
metal base
semiconductor device
unit module
base
slit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001218590A
Other languages
Japanese (ja)
Inventor
Takatoshi Kobayashi
孝敏 小林
Sohiko Betsuda
惣彦 別田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001218590A priority Critical patent/JP2003031738A/en
Publication of JP2003031738A publication Critical patent/JP2003031738A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

PROBLEM TO BE SOLVED: To reduce the mutual interference between a plurality of metallic bases to an ignorable degree and, in addition, to make the metallic bases deformable to such a degree that the bases can be adhered closely to a cooling body, in a large-capacity semiconductor device in which unit modules constituted by mounting semiconductor chips on circuit boards are bonded to the surfaces of the metallic bases. SOLUTION: In each metallic base 5, for example, slits 7 having widths which are almost equal to the thickness of the base 5 are provided among three unit modules 1, 2, and 3 respectively constituting the U-, V- and W-phases of a three-phase bridge and fixed on the base 5. Then the projecting sections 45 of a resin-made encapsulating case frame 4 are inserted into the slits 7 and, at the same time, the frame 4 is bonded to the base 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、スイッチング電源
装置、定電圧定周波数制御装置(CVCF)または可変
電圧可変周波数電源装置(VVVF)等のコンバータや
インバータに用いられるパワートランジスタモジュール
と称される半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor called a power transistor module used for a converter or an inverter of a switching power supply device, a constant voltage constant frequency control device (CVCF) or a variable voltage variable frequency power supply device (VVVF). Regarding the device.

【0002】[0002]

【従来の技術】一般に、パワートランジスタモジュール
は、回路基板上に半導体チップを搭載し、それを金属ベ
ース上に接合したものに、樹脂製の外装ケース枠を取り
付けた構成となっている。金属ベースのサイズ、および
金属ベース上に搭載される回路基板のサイズや枚数は、
定格電圧、電流、回路構成、チップ搭載面積および発熱
量等により決定される。この金属ベースは、パワートラ
ンジスタモジュールを各種装置に実装する際にその装置
の冷却体に密接させられる。
2. Description of the Related Art In general, a power transistor module has a structure in which a semiconductor chip is mounted on a circuit board, which is joined to a metal base, and a resin outer case frame is attached. The size of the metal base, and the size and number of circuit boards mounted on the metal base are
It is determined by the rated voltage, current, circuit configuration, chip mounting area and heat generation amount. This metal base is brought into close contact with the cooling body of the device when the power transistor module is mounted on the device.

【0003】[0003]

【発明が解決しようとする課題】近時、パワートランジ
スタモジュールの大容量化に伴い、金属ベース上に搭載
される回路基板の数が増えている。そのため、各回路基
板およびそれが固定されている各金属ベース部分の間
で、製造工程において、応力、熱、および反りやうねり
などの変形の相互干渉が起こるので、設計検証が複雑に
なり、時間がかかるという問題点がある。また、回路基
板数の増大に合わせて金属ベースのサイズが大きくなる
ため、金属ベースを装置の冷却体に密接させる際に、冷
却体の反りなどに合わせて金属ベースを変形させたり、
あるいは変形させないようにするなどの制御が困難にな
るという問題点もある。
Recently, as the capacity of the power transistor module is increased, the number of circuit boards mounted on the metal base is increasing. Therefore, mutual interference of stress, heat, and deformation such as warpage and undulation occurs in the manufacturing process between each circuit board and each metal base part to which it is fixed, which complicates design verification and reduces time. There is a problem that it costs. In addition, since the size of the metal base increases as the number of circuit boards increases, when the metal base is brought into close contact with the cooling body of the device, the metal base may be deformed according to the warp of the cooling body, or the like.
There is also a problem that it is difficult to control such as not to deform.

【0004】本発明は、上記問題点に鑑みてなされたも
のであって、回路基板上に半導体チップを搭載した単位
モジュールを複数、金属ベース上に接合した構成の半導
体装置において、各単位モジュールが固定されている金
属ベース部分の間の相互干渉を無視し得る程度とし、か
つ冷却体に金属ベースを密着させることが可能な程度に
変形させることができる半導体装置を提供することを目
的とする。
The present invention has been made in view of the above problems, and in a semiconductor device having a structure in which a plurality of unit modules each having a semiconductor chip mounted on a circuit board are bonded to a metal base, each unit module is It is an object of the present invention to provide a semiconductor device in which mutual interference between fixed metal base portions can be ignored and the metal base can be deformed to such an extent that the metal base can be brought into close contact with the cooling body.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明にかかる半導体装置は、たとえば3相ブリッ
ジのU相、V相およびW相をそれぞれ構成する3個の単
位モジュールを固定した金属ベースの、隣り合う単位モ
ジュール同士の間に金属ベースの厚さと同程度のスリッ
トを設け、そのスリット内に樹脂製の外装ケース枠の突
起部を挿入するとともに、外装ケース枠と金属ベースと
を接着したものである。
In order to achieve the above object, a semiconductor device according to the present invention is a metal device in which three unit modules respectively constituting U-phase, V-phase and W-phase of a three-phase bridge are fixed. A slit having the same thickness as the metal base is provided between adjacent unit modules of the base, and the protrusion of the resin-made outer case frame is inserted into the slit and the outer case frame and the metal base are bonded together. It was done.

【0006】この発明によれば、金属ベースにスリット
が設けられていることによって、スリットを挟む両側の
金属ベース部分において、応力、熱、反りやうねりなど
の変形の相互干渉を無視して考えることができる。ま
た、冷却体に金属ベースを密着させるために、冷却体の
反りに合わせて変形させることができる。
According to the present invention, since the metal base is provided with the slits, the mutual interference of deformations such as stress, heat, warpage and undulation can be ignored in the metal base portions on both sides of the slit. You can Further, in order to bring the metal base into close contact with the cooling body, it can be deformed according to the warp of the cooling body.

【0007】[0007]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて図面を参照しつつ詳細に説明する。図1は、本発明
にかかる半導体装置の一例を示す平面図であり、図2
は、その部分断面図である。この半導体装置は、シック
ス・イン・ワン(6in1)と呼ばれる3相ブリッジで
あり、U相の単位モジュール1の隣にV相の単位モジュ
ール2が配置され、その隣にW相の単位モジュール3が
配置された構成となっている。ここで、単位モジュール
とは、半導体装置が、同一もしくは同様の構成または機
能を有する複数のブロックで構成される場合の個々のブ
ロックのことである。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. 1 is a plan view showing an example of a semiconductor device according to the present invention.
FIG. 4 is a partial cross-sectional view thereof. This semiconductor device is a three-phase bridge called six-in-one (6in1), in which a V-phase unit module 2 is arranged next to a U-phase unit module 1 and a W-phase unit module 3 is adjacent to it. It is arranged. Here, the unit module is an individual block when the semiconductor device is composed of a plurality of blocks having the same or similar configuration or function.

【0008】各単位モジュール1,2,3の外周は樹脂
製の外装ケース枠4により囲まれている。U相単位モジ
ュール1とV相単位モジュール2との間、およびV相単
位モジュール2とW相単位モジュール3との間は、それ
ぞれ外装ケース枠4の仕切り部41により仕切られてい
る。図1および図2において、符号42は図示しないプ
リント回路基板との電気的な接続に供される接続ピン
(制御端子)であり、符号43は図示しない装置との電
気的な接続に供される外部端子(主端子)であり、符号
44はこの半導体装置を図示しない装置にねじ止めする
ための孔である。
The outer periphery of each unit module 1, 2 and 3 is surrounded by an outer case frame 4 made of resin. The U-phase unit module 1 and the V-phase unit module 2 are separated from each other, and the V-phase unit module 2 and the W-phase unit module 3 are separated from each other by a partition portion 41 of the outer case frame 4. 1 and 2, reference numeral 42 is a connection pin (control terminal) for electrical connection with a printed circuit board (not shown), and reference numeral 43 is for electrical connection with a device (not shown). External terminals (main terminals), reference numeral 44 is a hole for screwing this semiconductor device to a device (not shown).

【0009】図3は、図1に示す半導体装置の金属ベー
ス5上に3個の単位モジュール1,2,3が設けられて
いる様子を示す平面図である。各モジュール1,2,3
はそれぞれ2枚の回路基板61,62により構成されて
いる。各回路基板61,62には配線パターン63が形
成されており、それぞれ並列接続となる3個のIGBT
チップ64および並列接続となる3個のFWDチップ
(ダイオード)65が搭載されている。
FIG. 3 is a plan view showing a state in which three unit modules 1, 2 and 3 are provided on the metal base 5 of the semiconductor device shown in FIG. Each module 1, 2, 3
Is composed of two circuit boards 61 and 62, respectively. A wiring pattern 63 is formed on each of the circuit boards 61 and 62, and each of the three IGBTs is connected in parallel.
A chip 64 and three FWD chips (diodes) 65 that are connected in parallel are mounted.

【0010】U相単位モジュール1の2枚の回路基板6
1,62とV相単位モジュール2の2枚の回路基板6
1,62との間、およびV相単位モジュール2の2枚の
回路基板61,62とW相単位モジュール3の2枚の回
路基板61,62との間には、それぞれ金属ベース5を
表裏に貫通するスリット7が設けられている。つまり、
図3に二点鎖線で示すように、金属ベース5をU相単位
モジュール1に該当する部分51とV相単位モジュール
2に該当する部分52とW相単位モジュール3に該当す
る部分53に分けて考えると、U相単位モジュール該当
部分51とV相単位モジュール該当部分52、およびV
相単位モジュール該当部分52とW相単位モジュール該
当部分53は、それぞれ金属ベース5の縁部分(図3に
おいて上側の縁と下側の縁)でのみ互いに連結されたよ
うな構成となっている。
Two circuit boards 6 of the U-phase unit module 1
Two circuit boards 6 of 1, 62 and V-phase unit module 2
1 and 62, and between the two circuit boards 61 and 62 of the V-phase unit module 2 and the two circuit boards 61 and 62 of the W-phase unit module 3, the metal base 5 is arranged on both sides. A slit 7 penetrating therethrough is provided. That is,
As shown by a chain double-dashed line in FIG. 3, the metal base 5 is divided into a portion 51 corresponding to the U-phase unit module 1, a portion 52 corresponding to the V-phase unit module 2 and a portion 53 corresponding to the W-phase unit module 3. Considering this, the U-phase unit module corresponding portion 51, the V-phase unit module corresponding portion 52, and V
The phase unit module corresponding portion 52 and the W phase unit module corresponding portion 53 are configured to be connected to each other only at the edge portions (the upper edge and the lower edge in FIG. 3) of the metal base 5.

【0011】図4は、図1に示す半導体装置の要部を拡
大して示す部分拡大断面図である。外装ケース枠4の仕
切り部41の下端には下向きに突出する突起部45が設
けられている。この突起部45はスリット7内に挿入さ
れており、それによってスリット7の見かけ上の幅が狭
くなっている。
FIG. 4 is a partially enlarged cross-sectional view showing an enlarged main part of the semiconductor device shown in FIG. A projecting portion 45 protruding downward is provided at the lower end of the partition portion 41 of the outer case frame 4. The protrusion 45 is inserted into the slit 7, whereby the apparent width of the slit 7 is narrowed.

【0012】また、仕切り部41の、突起部45の周辺
部分は、金属ベース5の、スリット7の周辺部分に接着
剤8により接着されている。この接着剤8は、金属ベー
ス5、外装ケース枠4および蓋体91により閉塞される
空間に充填されるシリコーンゲル等の充填材92がスリ
ット7から漏出するのを防ぐ。
The peripheral portion of the projection 45 of the partition portion 41 is adhered to the peripheral portion of the slit 7 of the metal base 5 with an adhesive 8. The adhesive 8 prevents the filler 92 such as silicone gel filling the space closed by the metal base 5, the outer case frame 4 and the lid 91 from leaking out from the slit 7.

【0013】また、接着剤8の、スリット7の内周面と
突起部45との間の隙間にはみ出した部分には表面張力
が生じる。その表面張力によって、スリット7から接着
剤8が垂れるのを防ぐ。この隙間にはみ出した接着剤8
には、外装ケース枠4と金属ベース5との接着面積を増
やし、接着強度を高めるという役割もある。
Further, a surface tension is generated in the portion of the adhesive 8 that protrudes into the gap between the inner peripheral surface of the slit 7 and the protrusion 45. The surface tension prevents the adhesive 8 from dripping from the slit 7. Adhesive 8 protruding into this gap
Also has a role of increasing the bonding area between the outer case frame 4 and the metal base 5 and increasing the bonding strength.

【0014】ここで、図4に示すように、各回路基板6
1,62は、金属ベース5への半田付けに供されるCu
などの金属層66上に、アルミナや窒化アルミニウムや
窒化ケイ素などのセラミック層67が積層され、さらに
その上に回路パターンに成形されたCuなどの金属パタ
ーン層68が積層された構成となっている。なお、図4
において符号69はボンディングワイヤである。
Here, as shown in FIG. 4, each circuit board 6
1 and 62 are Cu used for soldering to the metal base 5.
A ceramic layer 67 such as alumina, aluminum nitride, or silicon nitride is laminated on the metal layer 66 such as, and a metal pattern layer 68 such as Cu formed into a circuit pattern is further laminated thereon. . Note that FIG.
Reference numeral 69 is a bonding wire.

【0015】つぎに、上述した構成の半導体装置の各部
の寸法は以下のとおりである。なお、以下に記載する寸
法は一例であり、本発明にかかる半導体装置は以下の寸
法に限定されるものではない。たとえば金属ベース5の
サイズは122mm×162mmであり、その厚さは3
mmである。また、回路基板61,62は、たとえばセ
ラミック層67となる厚さ0.32mmのアルミナ基板
の表面に、金属パターン層68として0.25tのCu
板よりなる回路パターンを形成するとともに、アルミナ
基板の裏面に半田付け用の金属層66となる0.2tの
Cu板を貼りつけたものである。
Next, the dimensions of each part of the semiconductor device having the above-mentioned structure are as follows. Note that the dimensions described below are examples, and the semiconductor device according to the present invention is not limited to the following dimensions. For example, the size of the metal base 5 is 122 mm × 162 mm, and its thickness is 3
mm. Further, the circuit boards 61 and 62 are, for example, 0.25 t of Cu as the metal pattern layer 68 on the surface of an alumina substrate having a thickness of 0.32 mm which becomes the ceramic layer 67.
A circuit pattern made of a plate is formed, and a Cu plate of 0.2 t serving as a metal layer 66 for soldering is attached to the back surface of the alumina substrate.

【0016】また、金属ベース5と回路基板61,62
との半田接合には、たとえばPb60/Sn40の半田
が用いられる。また、スリット7の幅は熱伝導や接着剤
8の漏出という観点から狭い程よいが、一般に、プレス
加工による打ち抜き幅は板厚以上であるという制約条件
があるため、ここではスリット7の幅は金属ベース5の
板厚(3mm)以上、たとえば4mmである。スリット
7の長さはたとえば84.4mmである。また、たとえ
ば外装ケース枠4の突起部45の幅は3.6mmであ
り、高さすなわち突出量は1.7mmである。
Further, the metal base 5 and the circuit boards 61, 62
For example, Pb60 / Sn40 solder is used for soldering with In addition, the width of the slit 7 is preferably as narrow as possible from the viewpoint of heat conduction and leakage of the adhesive agent 8. However, in general, there is a constraint condition that the punching width by press working is equal to or more than the plate thickness. It is equal to or larger than the plate thickness (3 mm) of the base 5, for example, 4 mm. The length of the slit 7 is, for example, 84.4 mm. Further, for example, the width of the protrusion 45 of the outer case frame 4 is 3.6 mm, and the height, that is, the protrusion amount is 1.7 mm.

【0017】上述した実施の形態によれば、金属ベース
5にスリット7が設けられていることによって、金属ベ
ース5が、U相単位モジュール該当部分51、V相単位
モジュール該当部分52およびW相単位モジュール該当
部分53の3つの部分におおよそ独立しているとみなす
ことができるので、U相単位モジュール該当部分51と
V相単位モジュール該当部分52とW相単位モジュール
該当部分53との間の、応力、熱、および反りやうねり
などの変形の相互干渉を無視して考えることができる。
したがって、半導体装置の設計および試験が容易になる
という効果が得られる。
According to the above-described embodiment, since the metal base 5 is provided with the slits 7, the metal base 5 has the U-phase unit module corresponding portion 51, the V-phase unit module corresponding portion 52, and the W-phase unit. Since it can be considered that the three parts of the module corresponding part 53 are almost independent, the stress between the U phase unit module corresponding part 51, the V phase unit module corresponding part 52 and the W phase unit module corresponding part 53 is Mutual interference of heat, heat, and deformation such as warpage and swell can be ignored.
Therefore, the effect of facilitating the design and test of the semiconductor device is obtained.

【0018】また、U相単位モジュール該当部分51、
V相単位モジュール該当部分52およびW相単位モジュ
ール該当部分53は金属ベース5の縁部分でのみ連結さ
れているのと同じであるため、冷却体へねじ止めする際
に、その部分に応力が集中して、冷却体の反りにならっ
て変形し易くなる。したがって、装置の冷却対と金属ベ
ース5を容易に密着させることができるという効果が得
られる。
The U-phase unit module corresponding part 51,
Since the V-phase unit module corresponding portion 52 and the W-phase unit module corresponding portion 53 are the same as being connected only at the edge portion of the metal base 5, stress is concentrated on that portion when screwed to the cooling body. As a result, the cooling body is easily bent and deformed. Therefore, the effect that the cooling pair of the apparatus and the metal base 5 can be easily brought into close contact with each other can be obtained.

【0019】また、このとき、各相の変形に対する強度
は、各相の金属ベース幅において冷却体の反りに対する
強度を確保するようにすればよい。従来のようにスリッ
トがない場合は、金属ベースの全体幅とそれに対する冷
却体の反りが関係してくるため、特定の単位モジュール
に応力が集中することもありうる。
At this time, the strength against deformation of each phase may be ensured against the warp of the cooling body in the metal base width of each phase. If there is no slit as in the conventional case, the entire width of the metal base and the warp of the cooling body with respect to it are related, so that stress may be concentrated on a specific unit module.

【0020】また、上述した実施の形態によれば、装置
の冷却体に半導体装置を取り付ける際にそれらの間にコ
ンパウンドが塗布されるが、スリット7に余分なコンパ
ウンドが流れ込んだり、コンパウンドの膜の中に残る気
泡や空気の溜まりがスリット7により吸収されるので、
コンパウンドが冷却体と金属ベース5との接合面全面に
均一に拡がり易くなるという効果が得られる。
Further, according to the above-mentioned embodiment, when the semiconductor device is attached to the cooling body of the device, the compound is applied between them, but the excess compound flows into the slit 7 or the film of the compound is formed. Since air bubbles and air pools that remain inside are absorbed by the slit 7,
It is possible to obtain the effect that the compound easily spreads uniformly over the entire joint surface between the cooling body and the metal base 5.

【0021】以上において本発明は種々変更可能であ
る。また、本発明は3相ブリッジ以外の装置、たとえ
ば、Hブリッジなどの装置にも適用することができる。
The present invention can be variously modified in the above. Further, the present invention can be applied to a device other than the three-phase bridge, for example, a device such as an H bridge.

【0022】[0022]

【発明の効果】本発明によれば、金属ベースにスリット
が設けられていることによって、スリットを挟む両側の
金属ベース部分において、応力、熱、反りやうねりなど
の変形の相互干渉を無視して考えることができるので、
半導体装置の設計および試験が容易になる。また、スリ
ットがあることによって、冷却体に金属ベースを密着さ
せるために、冷却体の反りに合わせて変形させることが
できるので、金属ベースを装置の冷却体に密接させる際
に、冷却体の反りなどに合わせて金属ベースを容易に変
形させることができる。
According to the present invention, since the metal base is provided with the slits, mutual interference of deformation such as stress, heat, warpage and undulation is neglected in the metal base portions on both sides of the slit. Because I can think
The semiconductor device can be easily designed and tested. In addition, the presence of the slit allows the metal base to be in close contact with the cooling body, so that the metal base can be deformed in accordance with the warp of the cooling body. The metal base can be easily deformed according to such circumstances.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる半導体装置の一例を示す平面図
である。
FIG. 1 is a plan view showing an example of a semiconductor device according to the present invention.

【図2】本発明にかかる半導体装置の一例を示す部分断
面図である。
FIG. 2 is a partial cross-sectional view showing an example of a semiconductor device according to the present invention.

【図3】図1に示す半導体装置の金属ベース上に3個の
単位モジュールが設けられている様子を示す平面図であ
る。
FIG. 3 is a plan view showing a state in which three unit modules are provided on the metal base of the semiconductor device shown in FIG.

【図4】本発明にかかる半導体装置の要部を拡大して示
す部分拡大断面図である。
FIG. 4 is a partial enlarged cross-sectional view showing an enlarged main part of a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1,2,3 単位モジュール 4 ケース枠 5 金属ベース 7 スリット 8 接着剤 41 仕切り部 42 接続ピン 43 外部端子 44 (ねじ止めするための)孔 45 突起部 61,62 回路基板 63 配線パターン 64 IGBTチップ 65 FWDチップ 66 金属層 67 セラミック層 68 金属パターン層 69 ボンディングワイヤ 91 蓋体 92 充填材 1, 2, 3 unit module 4 case frames 5 metal base 7 slits 8 adhesive 41 partition 42 Connection pin 43 External terminal 44 hole (for screwing) 45 Projection 61,62 Circuit board 63 wiring pattern 64 IGBT chip 65 FWD chip 66 metal layer 67 Ceramic layer 68 Metal pattern layer 69 Bonding wire 91 Lid 92 Filling material

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 金属ベース上に、複数の単位モジュール
が固定された半導体装置であって、 前記金属ベースの、前記単位モジュール同士の間に金属
ベースの表裏に貫通するスリットが設けられていること
を特徴とする半導体装置。
1. A semiconductor device having a plurality of unit modules fixed on a metal base, wherein slits penetrating the front and back of the metal base are provided between the unit modules of the metal base. A semiconductor device characterized by:
【請求項2】 前記スリットの幅は前記金属ベースの厚
さと同じ寸法かまたはそれ以上であることを特徴とする
請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the width of the slit is equal to or larger than the thickness of the metal base.
【請求項3】 前記金属ベースには、前記スリットに挿
入される突起部を備えた樹脂ケース枠が固着されてお
り、前記突起部は前記スリットに挿入されていることを
特徴とする請求項1または2に記載の半導体装置。
3. A resin case frame having a protrusion inserted into the slit is fixed to the metal base, and the protrusion is inserted into the slit. Alternatively, the semiconductor device according to item 2.
JP2001218590A 2001-07-18 2001-07-18 Semiconductor device Pending JP2003031738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001218590A JP2003031738A (en) 2001-07-18 2001-07-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001218590A JP2003031738A (en) 2001-07-18 2001-07-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2003031738A true JP2003031738A (en) 2003-01-31

Family

ID=19052752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001218590A Pending JP2003031738A (en) 2001-07-18 2001-07-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2003031738A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059902A (en) * 2005-08-24 2007-03-08 Semikron Elektronik Gmbh & Co Kg Power semiconductor modules having fixation devices
KR101145640B1 (en) 2010-12-06 2012-05-23 기아자동차주식회사 Power module for invertor
CN105374811A (en) * 2015-11-23 2016-03-02 扬州国扬电子有限公司 Power module

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61203700A (en) * 1985-03-07 1986-09-09 キヤノン株式会社 Electronic circuit apparatus
JPH1093016A (en) * 1996-09-19 1998-04-10 Hitachi Ltd Power semiconductor device
JP2002184914A (en) * 2000-12-14 2002-06-28 Nippon Inter Electronics Corp Compound semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61203700A (en) * 1985-03-07 1986-09-09 キヤノン株式会社 Electronic circuit apparatus
JPH1093016A (en) * 1996-09-19 1998-04-10 Hitachi Ltd Power semiconductor device
JP2002184914A (en) * 2000-12-14 2002-06-28 Nippon Inter Electronics Corp Compound semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007059902A (en) * 2005-08-24 2007-03-08 Semikron Elektronik Gmbh & Co Kg Power semiconductor modules having fixation devices
KR101145640B1 (en) 2010-12-06 2012-05-23 기아자동차주식회사 Power module for invertor
CN105374811A (en) * 2015-11-23 2016-03-02 扬州国扬电子有限公司 Power module

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