JP4673893B2 - 不揮発性記憶素子 - Google Patents

不揮発性記憶素子 Download PDF

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Publication number
JP4673893B2
JP4673893B2 JP2007532804A JP2007532804A JP4673893B2 JP 4673893 B2 JP4673893 B2 JP 4673893B2 JP 2007532804 A JP2007532804 A JP 2007532804A JP 2007532804 A JP2007532804 A JP 2007532804A JP 4673893 B2 JP4673893 B2 JP 4673893B2
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JP
Japan
Prior art keywords
terminal
data
mos transistor
transistor
gate
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Expired - Fee Related
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JP2007532804A
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English (en)
Japanese (ja)
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JP2008515122A (ja
Inventor
シャッツベルガー、グレーゴル
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オーストリアマイクロシステムス アーゲー
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
JP2007532804A 2004-09-27 2005-09-14 不揮発性記憶素子 Expired - Fee Related JP4673893B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004046793A DE102004046793B3 (de) 2004-09-27 2004-09-27 Nicht-flüchtiges Speicherelement
PCT/EP2005/009881 WO2006034782A1 (de) 2004-09-27 2005-09-14 Nicht-flüchtiges speicherelement

Publications (2)

Publication Number Publication Date
JP2008515122A JP2008515122A (ja) 2008-05-08
JP4673893B2 true JP4673893B2 (ja) 2011-04-20

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ID=35276175

Family Applications (1)

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JP2007532804A Expired - Fee Related JP4673893B2 (ja) 2004-09-27 2005-09-14 不揮発性記憶素子

Country Status (6)

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US (1) US7602640B2 (enExample)
EP (1) EP1794758B1 (enExample)
JP (1) JP4673893B2 (enExample)
DE (2) DE102004046793B3 (enExample)
TW (1) TWI281162B (enExample)
WO (1) WO2006034782A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080019162A1 (en) * 2006-07-21 2008-01-24 Taku Ogura Non-volatile semiconductor storage device
US8189328B2 (en) * 2006-10-23 2012-05-29 Virident Systems, Inc. Methods and apparatus of dual inline memory modules for flash memory
DE102007030842B4 (de) 2007-07-03 2015-05-21 Austriamicrosystems Ag Speicheranordnung und Verfahren zum Speichern
US7916539B2 (en) * 2009-01-23 2011-03-29 Analog Devices, Inc. Differential, level-shifted EEPROM structures
JP5556873B2 (ja) * 2012-10-19 2014-07-23 株式会社フローディア 不揮発性半導体記憶装置
US12218598B2 (en) * 2022-05-31 2025-02-04 Texas Instruments Incorporated Quasi-resonant isolated voltage converter

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit
US4348745A (en) * 1980-10-27 1982-09-07 Hughes Aircraft Company Non-volatile random access memory having non-inverted storage
JPH0562487A (ja) * 1991-09-06 1993-03-12 Toshiba Corp プログラマブル初期動作モード設定回路
JP3450896B2 (ja) * 1994-04-01 2003-09-29 三菱電機株式会社 不揮発性メモリ装置
US5523971A (en) * 1995-03-16 1996-06-04 Xilinx, Inc. Non-volatile memory cell for programmable logic device
US5648930A (en) * 1996-06-28 1997-07-15 Symbios Logic Inc. Non-volatile memory which is programmable from a power source
US6097242A (en) * 1998-02-26 2000-08-01 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US6411545B1 (en) * 1999-11-19 2002-06-25 John Millard And Pamela Ann Caywood 1989 Revokable Living Trust Non-volatile latch
WO2004112047A1 (en) * 2003-06-17 2004-12-23 Koninklijke Philips Electronics N.V. Non-volatile static memory cell

Also Published As

Publication number Publication date
TWI281162B (en) 2007-05-11
DE102004046793B3 (de) 2006-05-11
TW200614248A (enExample) 2006-05-01
EP1794758A1 (de) 2007-06-13
DE502005005969D1 (de) 2008-12-24
WO2006034782A1 (de) 2006-04-06
US20080165583A1 (en) 2008-07-10
EP1794758B1 (de) 2008-11-12
US7602640B2 (en) 2009-10-13
JP2008515122A (ja) 2008-05-08

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