JP4667786B2 - トレンチを形成する方法 - Google Patents
トレンチを形成する方法 Download PDFInfo
- Publication number
- JP4667786B2 JP4667786B2 JP2004225216A JP2004225216A JP4667786B2 JP 4667786 B2 JP4667786 B2 JP 4667786B2 JP 2004225216 A JP2004225216 A JP 2004225216A JP 2004225216 A JP2004225216 A JP 2004225216A JP 4667786 B2 JP4667786 B2 JP 4667786B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- etch stop
- patterning
- photomask
- etch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 30
- 239000000758 substrate Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 11
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 238000000295 emission spectrum Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 10
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012804 iterative process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00547—Etching processes not provided for in groups B81C1/00531 - B81C1/00539
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/946—Step and repeat
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Diffracting Gratings Or Hologram Optical Elements (AREA)
- Weting (AREA)
Description
FILM2 第二の層
ETCHSTOP エッチストップ層
Claims (10)
- c−Si基板である第一の層上にエッチストップ層を形成するステップと、
該エッチストップ層上に第二の層を形成するステップと、
該第二の層上に第一のフォトマスク層を形成するステップと、
該第一のフォトマスク層をパターニングするステップと、
前記第二の層を、前記第一のフォトマスク層をマスクにしてパターニングするステップと、
前記エッチストップ層を、前記第一のフォトマスク層をマスクにしてパターニングするステップと、
前記第一のフォトマスク層の一部を除去することにより前記第二の層の一部を露出するステップと、
前記第一の層を、前記第一のフォトマスク層をマスクにして、前記第二の層の一部を除去して前記エッチストップ層が露出するまでパターニングし、第一のトレンチを形成するステップとを行った後に、
露出した前記エッチストップ層の縁部を形成する前記第二の層上にある前記第一のフォトマスク層の一部をパターニングするステップと、
前記第二の層の一部を、前記第一のフォトマスク層の一部をマスクにしてパターニングするステップと、
前記第一のフォトマスク層の一部をマスクにして、前記第二の層の一部を除去して前記エッチストップ層が露出するまで前記第一の層をエッチングすることにより、前記第一のトレンチとともに段差を形成する追加トレンチを画定するステップと
を含んでなり、前記追加トレンチが前記第一のトレンチよりも深さが浅いものである、トレンチを形成する方法。 - 前記エッチストップ層が酸化物である請求項1に記載の方法。
- 前記第一の層がc−Si基板であり、前記第二の層がアモルファス・シリコンである請求項1に記載の方法。
- 前記アモルファス・シリコンをパターニングするステップが、塩素系のエッチング化学反応によりエッチングするステップを有するものである請求項3に記載の方法。
- 前記第一の層がc−Si基板であり、前記第二の層がエピタキシャル・シリコンである請求項3に記載の方法。
- 前記エッチストップ層をパターニングするステップが、ウエットエッチング化学反応によりパターニングするステップを有するものである請求項1に記載の方法。
- 前記エッチストップ層をパターニングするステップが、ドライエッチング化学反応によりパターニングするステップを有するものである請求項1に記載の方法。
- 前記第二の層をパターニングするステップが、光学式エンドポイント検出法を用いてエッチング処理のエッチストップへの到達を判定することを含むものである請求項1に記載の方法。
- 前記光学式エンドポイント検出ステップが、光放射スペクトルの適用を含むものである請求項8に記載の方法。
- 前記光学式エンドポイント検出ステップが、干渉計の利用を含むものである請求項8に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/633,149 US20050023631A1 (en) | 2003-07-31 | 2003-07-31 | Controlled dry etch of a film |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005057287A JP2005057287A (ja) | 2005-03-03 |
JP4667786B2 true JP4667786B2 (ja) | 2011-04-13 |
Family
ID=32962817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004225216A Expired - Fee Related JP4667786B2 (ja) | 2003-07-31 | 2004-08-02 | トレンチを形成する方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20050023631A1 (ja) |
JP (1) | JP4667786B2 (ja) |
GB (1) | GB2404786B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7119010B2 (en) * | 2002-04-23 | 2006-10-10 | Chartered Semiconductor Manfacturing Ltd. | Integrated circuit with self-aligned line and via and manufacturing method therefor |
US20070020794A1 (en) * | 2005-07-22 | 2007-01-25 | Debar Michael J | Method of strengthening a microscale chamber formed over a sacrificial layer |
CN102249179A (zh) * | 2010-05-20 | 2011-11-23 | 上海华虹Nec电子有限公司 | 改善微机电系统传感薄膜空腔侧壁坡度的干法刻蚀方法 |
CN104425351A (zh) * | 2013-09-11 | 2015-03-18 | 中国科学院微电子研究所 | 沟槽形成方法和半导体器件制造方法 |
CN104465379B (zh) * | 2013-09-18 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及形成方法 |
US10186623B2 (en) | 2016-02-05 | 2019-01-22 | Texas Instruments Incorporated | Integrated photodetector |
KR20220030368A (ko) | 2020-08-28 | 2022-03-11 | 삼성디스플레이 주식회사 | 절연막의 식각 방법, 이를 이용한 표시 장치의 제조 방법 및 표시 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0864579A (ja) * | 1994-08-23 | 1996-03-08 | Toshiba Corp | 半導体装置の製造方法 |
JPH10199968A (ja) * | 1997-01-10 | 1998-07-31 | Sony Corp | 半導体装置及び半導体装置の素子間分離溝の形成方法 |
JP2003086766A (ja) * | 2001-06-28 | 2003-03-20 | Toshiba Corp | 半導体装置及びその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4791073A (en) * | 1987-11-17 | 1988-12-13 | Motorola Inc. | Trench isolation method for semiconductor devices |
US5651855A (en) * | 1992-07-28 | 1997-07-29 | Micron Technology, Inc. | Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits |
US6228277B1 (en) * | 1998-10-14 | 2001-05-08 | Lucent Technologies Inc. | Etch endpoint detection |
KR100322531B1 (ko) * | 1999-01-11 | 2002-03-18 | 윤종용 | 파임방지막을 이용하는 반도체소자의 트랜치 소자분리방법 및이를 이용한 반도체소자 |
US6140206A (en) * | 1999-06-14 | 2000-10-31 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures |
US6180508B1 (en) * | 1999-09-02 | 2001-01-30 | Micron Technology, Inc. | Methods of fabricating buried digit lines and semiconductor devices including same |
US6583047B2 (en) * | 2000-12-26 | 2003-06-24 | Honeywell International, Inc. | Method for eliminating reaction between photoresist and OSG |
US6440842B1 (en) * | 2001-02-02 | 2002-08-27 | Macronix International Co. Ltd. | Method of forming a dual damascene structure by patterning a sacrificial layer to define the plug portions of the structure |
US6973712B2 (en) * | 2002-03-07 | 2005-12-13 | Headway Technologies, Inc. | Lead plating method for GMR head manufacture |
US6934032B1 (en) * | 2002-09-30 | 2005-08-23 | Advanced Micro Devices, Inc. | Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process |
-
2003
- 2003-07-31 US US10/633,149 patent/US20050023631A1/en not_active Abandoned
-
2004
- 2004-07-30 GB GB0417098A patent/GB2404786B/en not_active Expired - Fee Related
- 2004-08-02 JP JP2004225216A patent/JP4667786B2/ja not_active Expired - Fee Related
-
2005
- 2005-01-26 US US11/044,393 patent/US7288476B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0864579A (ja) * | 1994-08-23 | 1996-03-08 | Toshiba Corp | 半導体装置の製造方法 |
JPH10199968A (ja) * | 1997-01-10 | 1998-07-31 | Sony Corp | 半導体装置及び半導体装置の素子間分離溝の形成方法 |
JP2003086766A (ja) * | 2001-06-28 | 2003-03-20 | Toshiba Corp | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB2404786A (en) | 2005-02-09 |
GB0417098D0 (en) | 2004-09-01 |
US20050023631A1 (en) | 2005-02-03 |
US7288476B2 (en) | 2007-10-30 |
JP2005057287A (ja) | 2005-03-03 |
US20050130409A1 (en) | 2005-06-16 |
GB2404786B (en) | 2006-06-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070042563A1 (en) | Single crystal based through the wafer connections technical field | |
US20160152465A1 (en) | Mems capacitive pressure sensors | |
JPH05121379A (ja) | 半導体装置の製造方法 | |
KR100574999B1 (ko) | 반도체소자의 패턴 형성방법 | |
US7288476B2 (en) | Controlled dry etch of a film | |
KR100741876B1 (ko) | 디보트가 방지된 트렌치 소자분리막이 형성된 반도체 소자의 제조 방법 | |
JP5916105B2 (ja) | 半導体装置の製造方法 | |
JP2015138971A (ja) | 埋め込み絶縁領域を備えた半導体基板上のサーモパイル・ピクセルの形成のためのcmos集積方法 | |
US7160751B2 (en) | Method of making a SOI silicon structure | |
KR20090063131A (ko) | 반도체 장치의 제조 방법 | |
US6465357B1 (en) | Fabricating structures using chemo-mechanical polishing and chemically-selective endpoint detection | |
KR100917812B1 (ko) | 듀얼 다마신을 갖는 반도체 장치의 제조 방법 | |
US6642154B2 (en) | Method and apparatus for fabricating structures using chemically selective endpoint detection | |
KR100576415B1 (ko) | 섀로우 트랜치 형성 방법 | |
KR100561972B1 (ko) | 반도체 소자분리 방법 | |
TW508727B (en) | Method to form shallow trench isolation structure | |
KR980006052A (ko) | 반도체장치의 소자분리 방법 | |
KR100191709B1 (ko) | 미세 콘택홀의 형성방법 | |
KR20070069956A (ko) | 미세 패턴 형성 방법 | |
JP2006013089A (ja) | 半導体装置及びその製造方法 | |
JPH11135404A (ja) | 半導体装置の製造方法 | |
JPH0496225A (ja) | 半導体装置の製造方法 | |
JPH1126572A (ja) | 半導体装置の製造方法 | |
JPH11224898A (ja) | レジストを用いた溝穴形成方法 | |
JPS63131537A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060629 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20060808 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20060808 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061129 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070611 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100701 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100706 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101001 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101105 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101210 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110106 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110112 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140121 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |