JP4664131B2 - 複数のデジタルクロックの高速同期化方法およびシステム - Google Patents
複数のデジタルクロックの高速同期化方法およびシステム Download PDFInfo
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- JP4664131B2 JP4664131B2 JP2005182172A JP2005182172A JP4664131B2 JP 4664131 B2 JP4664131 B2 JP 4664131B2 JP 2005182172 A JP2005182172 A JP 2005182172A JP 2005182172 A JP2005182172 A JP 2005182172A JP 4664131 B2 JP4664131 B2 JP 4664131B2
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- clock
- synchronization signal
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- 238000000034 method Methods 0.000 title claims description 12
- 230000004044 response Effects 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 230000000873 masking effect Effects 0.000 claims 2
- 230000002194 synthesizing effect Effects 0.000 claims 2
- 238000012360 testing method Methods 0.000 description 26
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Tests Of Electronic Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
12:中央クロック発生器
22:第1の(M)除算手段
24:PLL
26:位相検出器
28:低域通過フィルタ
30:電圧制御発振器
32:第3の(N)除算手段
34:第1の(D)カウンタ手段
36:第2の(S)カウンタ手段
38:第2の(P)除算手段
40:クロック分配腺
50a〜50c:カード
50:カードケージ
Claims (10)
- 複数のデジタルクロックを同期信号に同期させる方法であって、
中央で基準クロックを生成するステップと、
クロック乗算手段を使用して、前記基準クロックから前記デジタルクロックをそれぞれ合成するステップと、
前記同期信号に応答して前記クロック乗算手段をリセットするステップと、
前記クロック乗算手段の整定時間中、該クロック乗算手段の出力信号をマスキングするステップと、
を含む方法。 - 前記同期信号を前記基準クロックに同期させることを特徴とする、請求項1に記載の方法。
- 前記同期信号が、中央で前記基準クロックに同期され、前記同期信号と前記基準クロックとが、前記複数のデジタルクロックのうちの1つを合成する複数の電気回路にそれぞれ分配されることを特徴とする、請求項2に記載の方法。
- 前記クロック乗算手段が、位相ロックループを備えていることを特徴とする、請求項1から3のいずれか1項に記載の方法。
- 前記クロック乗算手段が、前記位相ロックループに直列に追加された第1の(M)除算器手段をさらに備えていることを特徴とする、請求項4に記載の方法。
- 前記第1の(M)除算器手段が、前記同期信号に応答してリセットされることを特徴とする、請求項5に記載の方法。
- 前記第1の(M)除算器手段の出力信号または前記基準クロックが、前記同期信号に応答して、第1の(D)カウンタ手段によってカウントされ、該第1の(D)カウンタ手段は少なくとも前記クロック乗算手段の整定時間の長さである第1の遅延時間を提供し、該第1の遅延時間を使用して前記クロック乗算手段の前記出力信号をマスキングすることを特徴とする、請求項5または6に記載の方法。
- 前記位相ロックループの出力が、前記第1の(D)カウンタ手段の出力信号に応答してカウントを開始する第2の(S)カウンタ手段によってカウントされ、該第2の(S)カウンタ手段は、異なるクロック乗算手段によって合成された複数のデジタルクロックのうちの少なくともいくつかの共通同期のための第2の遅延時間を提供することを特徴とする、請求項7に記載の方法。
- コンピュータなどのデータ処理システム上で実行したときに請求項1から8のいずれか1項に記載の方法を実行する、好ましくはデータキャリアに記憶されたソフトウェアプログラム。
- 複数のデジタルクロックを同期信号に同期させるシステムであって、中央で基準クロックを生成する手段と、クロック乗算手段を使用して前記基準クロックから前記デジタルクロックをそれぞれ合成する手段と、前記同期信号に応答して前記クロック乗算手段をリセットする手段と、前記クロック乗算手段の整定時間中、該クロック乗算手段の出力信号をマスキングする手段と、を備えていることを特徴とするシステム。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04102923A EP1610204B1 (en) | 2004-06-24 | 2004-06-24 | Fast synchronization of a number of digital clocks |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006014326A JP2006014326A (ja) | 2006-01-12 |
JP4664131B2 true JP4664131B2 (ja) | 2011-04-06 |
Family
ID=34929239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005182172A Active JP4664131B2 (ja) | 2004-06-24 | 2005-06-22 | 複数のデジタルクロックの高速同期化方法およびシステム |
Country Status (4)
Country | Link |
---|---|
US (1) | US7366937B2 (ja) |
EP (1) | EP1610204B1 (ja) |
JP (1) | JP4664131B2 (ja) |
DE (1) | DE602004017440D1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008286660A (ja) * | 2007-05-18 | 2008-11-27 | Yokogawa Electric Corp | 半導体試験装置 |
JP6313085B2 (ja) | 2014-03-27 | 2018-04-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
DE102018200395A1 (de) * | 2018-01-11 | 2019-07-11 | Robert Bosch Gmbh | Radarsystem mit in einer zentralen Steuereinheit integriertem Taktgeber |
US11019585B1 (en) * | 2018-07-24 | 2021-05-25 | Sprint Communications Company L.P. | Network generated precision time |
US11153067B2 (en) | 2019-05-14 | 2021-10-19 | Space Exploration Technologies Corp. | Chip to chip time synchronization |
US11133806B1 (en) * | 2019-05-14 | 2021-09-28 | Space Exploration Technologies Corp. | Phase lock loop (PLL) synchronization |
US11392165B2 (en) * | 2019-07-31 | 2022-07-19 | Texas Instruments Incorporated | Synchronization of a clock generator divider setting and multiple independent component clock divider settings |
US20240097689A1 (en) * | 2022-09-19 | 2024-03-21 | Qualcomm Incorporated | Synchronizing multiple phase-locked loop circuits |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62144433A (ja) * | 1985-12-19 | 1987-06-27 | Nec Corp | デ−タクロツク再生回路 |
JPH07321773A (ja) * | 1994-05-20 | 1995-12-08 | Fujitsu General Ltd | 位相同期回路 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5406590A (en) * | 1992-10-23 | 1995-04-11 | Compaq Computer Corporation | Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits |
US5537582A (en) * | 1993-05-21 | 1996-07-16 | Draeger; Jeffrey S. | Bus interface circuitry for synchronizing central processors running at multiple clock frequencies to other computer system circuitry |
DE69700149T2 (de) | 1997-05-22 | 1999-07-01 | Hewlett Packard Co | Dekompressionsschaltkreis |
EP0886214B1 (en) | 1997-05-30 | 1999-10-20 | Hewlett-Packard Company | Multi-channel architecture with channel independent clock signals |
DE69700328T2 (de) | 1997-09-13 | 1999-11-04 | Hewlett Packard Co | Ausgleich von Latenzzeit in einem Speicher |
EP0859318B1 (en) | 1997-09-13 | 1999-07-14 | Hewlett-Packard Company | Optimized memory organization in a multi-channel computer architecture |
JP3110377B2 (ja) * | 1998-04-28 | 2000-11-20 | 日本電気アイシーマイコンシステム株式会社 | 逓倍回路 |
TW460769B (en) * | 1999-08-24 | 2001-10-21 | Via Tech Inc | Apparatus and method for generating clock |
EP1092983B1 (en) | 2000-06-16 | 2003-01-22 | Agilent Technologies, Inc. (a Delaware corporation) | Integrated circuit tester with multi-port testing functionality |
US6611159B1 (en) * | 2002-02-19 | 2003-08-26 | International Business Machines Corporation | Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency |
JP4392153B2 (ja) * | 2002-07-17 | 2009-12-24 | パナソニック株式会社 | 波形等化装置 |
US6756827B2 (en) * | 2002-09-11 | 2004-06-29 | Broadcom Corporation | Clock multiplier using masked control of clock pulses |
-
2004
- 2004-06-24 EP EP04102923A patent/EP1610204B1/en not_active Expired - Fee Related
- 2004-06-24 DE DE602004017440T patent/DE602004017440D1/de not_active Expired - Lifetime
-
2005
- 2005-06-22 JP JP2005182172A patent/JP4664131B2/ja active Active
- 2005-06-22 US US11/158,645 patent/US7366937B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62144433A (ja) * | 1985-12-19 | 1987-06-27 | Nec Corp | デ−タクロツク再生回路 |
JPH07321773A (ja) * | 1994-05-20 | 1995-12-08 | Fujitsu General Ltd | 位相同期回路 |
Also Published As
Publication number | Publication date |
---|---|
EP1610204B1 (en) | 2008-10-29 |
US20050289405A1 (en) | 2005-12-29 |
DE602004017440D1 (de) | 2008-12-11 |
US7366937B2 (en) | 2008-04-29 |
EP1610204A1 (en) | 2005-12-28 |
JP2006014326A (ja) | 2006-01-12 |
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