JP4586811B2 - 電気光学装置および電気光学装置用基板 - Google Patents
電気光学装置および電気光学装置用基板 Download PDFInfo
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- JP4586811B2 JP4586811B2 JP2007059766A JP2007059766A JP4586811B2 JP 4586811 B2 JP4586811 B2 JP 4586811B2 JP 2007059766 A JP2007059766 A JP 2007059766A JP 2007059766 A JP2007059766 A JP 2007059766A JP 4586811 B2 JP4586811 B2 JP 4586811B2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
Claims (4)
- 走査線と、前記走査線に交差する表示信号線と、前記走査線と前記表示信号線の交差に対応して設けられる画素トランジスタと、前記画素トランジスタが接続される画素電極と、前記画素トランジスタと画素電極が配置される画素と、前記画素に設けられる保持容量と、前記保持容量に接続される保持容量線と、前記保持容量線に電位を印加する電位印加部と、前記電位印加部に前記電位を出力する出力端を備える駆動ICと、を備え、
前記電位印加部は、前記保持容量線に接続される配線と、互いに並列接続された複数の電位印加経路を含み、
前記互いに並列接続された複数の電位印加経路は、前記保持容量線に接続される配線と前記駆動ICの出力端とを接続し、
前記互いに並列接続された複数の電位印加経路の各配線幅が、前記保持容量線に接続される配線の配線幅よりも細く形成され、
前記互いに並列接続された複数の電位印加経路の一つは、検査パッドを通る経路を含むことを特徴とする電気光学装置。 - 請求項1に記載の電気光学装置であって、
前記保持容量線にHighレベルの電位を印加するHighレベル電位印加部と、前記保持容量線にLowレベルの電位を印加するLowレベル電位印加部と、前記Highレベル電位印加部とLowレベル電位印加部のいずれかを選択的に前記保持容量線に接続するスイッチング素子を備え、
前記Highレベル電位印加部と前記Lowレベル電位印加部は、各々一端が前記スイッチング素子に接続されたHighレベル電位印加経路とLowレベル電位印加電経路を有し、前記Highレベル電位印加経路と前記Lowレベル電位印加電経路は、各々その一部に、互いに並列接続された複数の電位印加経路を備え、前記複数の電位印加経路の一つに、各々検査パッドを通る経路を含むことを特徴とする電気光学装置。 - 請求項1または請求項2に記載の電気光学装置であって、
前記保持容量線の両端が前記電位印加部に接続されていることを特徴とする電気光学装置。 - 走査線と、前記走査線に交差する表示信号線と、前記走査線と前記表示信号線の交差に対応して設けられる画素トランジスタと、前記画素トランジスタが接続される画素電極と、前記画素トランジスタと画素電極が配置される画素と、前記画素に設けられる保持容量と、前記保持容量に接続される保持容量線と、前記保持容量線に電位を印加する電位印加部と、前記電位印加部に前記電位を出力する出力端を備える駆動ICと、を備え、
前記電位印加部は、前記保持容量線に接続される配線と、互いに並列接続された複数の電位印加経路を含み、
前記互いに並列接続された複数の電位印加経路は、前記保持容量線に接続される配線と前記駆動ICの出力端とを接続し、
前記互いに並列接続された複数の電位印加経路の各配線幅が、前記保持容量線に接続される配線の配線幅よりも細く形成され、
前記互いに並列接続された複数の電位印加経路の一つは、検査パッドを通る経路を含むことを特徴とする電気光学装置用基板。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007059766A JP4586811B2 (ja) | 2007-03-09 | 2007-03-09 | 電気光学装置および電気光学装置用基板 |
US12/068,808 US20080218651A1 (en) | 2007-03-09 | 2008-02-12 | Electro-optical device and substrate for electro-optical device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007059766A JP4586811B2 (ja) | 2007-03-09 | 2007-03-09 | 電気光学装置および電気光学装置用基板 |
Publications (2)
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JP2008224810A JP2008224810A (ja) | 2008-09-25 |
JP4586811B2 true JP4586811B2 (ja) | 2010-11-24 |
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JP2007059766A Expired - Fee Related JP4586811B2 (ja) | 2007-03-09 | 2007-03-09 | 電気光学装置および電気光学装置用基板 |
Country Status (2)
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US (1) | US20080218651A1 (ja) |
JP (1) | JP4586811B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0372321A (ja) * | 1989-08-14 | 1991-03-27 | Sharp Corp | アクティブマトリクス表示装置 |
JPH05224239A (ja) * | 1992-02-18 | 1993-09-03 | Nec Corp | アクティブマトリクス液晶表示ディスプレイ |
JP2000206548A (ja) * | 1999-01-08 | 2000-07-28 | Matsushita Electric Ind Co Ltd | 液晶表示装置およびその製造方法 |
JP2002176056A (ja) * | 2000-12-06 | 2002-06-21 | Fujitsu Ltd | 外部接続端子及びそれを備えた液晶表示装置及びその製造方法 |
JP2002196358A (ja) * | 2000-12-22 | 2002-07-12 | Seiko Epson Corp | 液晶表示装置、駆動回路、駆動方法および電子機器 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW527513B (en) * | 2000-03-06 | 2003-04-11 | Hitachi Ltd | Liquid crystal display device and manufacturing method thereof |
KR100733879B1 (ko) * | 2000-12-30 | 2007-07-02 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 |
US7209192B2 (en) * | 2001-09-26 | 2007-04-24 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for liquid crystal display and method for manufacturing the same |
JP4262521B2 (ja) * | 2003-05-28 | 2009-05-13 | シャープ株式会社 | 表示装置及びその検査方法 |
US7161389B2 (en) * | 2004-06-30 | 2007-01-09 | Intel Corporation | Ratioed logic circuits with contention interrupt |
KR100828792B1 (ko) * | 2005-06-30 | 2008-05-09 | 세이코 엡슨 가부시키가이샤 | 집적 회로 장치 및 전자 기기 |
-
2007
- 2007-03-09 JP JP2007059766A patent/JP4586811B2/ja not_active Expired - Fee Related
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2008
- 2008-02-12 US US12/068,808 patent/US20080218651A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0372321A (ja) * | 1989-08-14 | 1991-03-27 | Sharp Corp | アクティブマトリクス表示装置 |
JPH05224239A (ja) * | 1992-02-18 | 1993-09-03 | Nec Corp | アクティブマトリクス液晶表示ディスプレイ |
JP2000206548A (ja) * | 1999-01-08 | 2000-07-28 | Matsushita Electric Ind Co Ltd | 液晶表示装置およびその製造方法 |
JP2002176056A (ja) * | 2000-12-06 | 2002-06-21 | Fujitsu Ltd | 外部接続端子及びそれを備えた液晶表示装置及びその製造方法 |
JP2002196358A (ja) * | 2000-12-22 | 2002-07-12 | Seiko Epson Corp | 液晶表示装置、駆動回路、駆動方法および電子機器 |
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JP2008224810A (ja) | 2008-09-25 |
US20080218651A1 (en) | 2008-09-11 |
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