JP4562403B2 - 表示装置の製造方法 - Google Patents
表示装置の製造方法 Download PDFInfo
- Publication number
- JP4562403B2 JP4562403B2 JP2004052536A JP2004052536A JP4562403B2 JP 4562403 B2 JP4562403 B2 JP 4562403B2 JP 2004052536 A JP2004052536 A JP 2004052536A JP 2004052536 A JP2004052536 A JP 2004052536A JP 4562403 B2 JP4562403 B2 JP 4562403B2
- Authority
- JP
- Japan
- Prior art keywords
- resin film
- protective resin
- display cell
- liquid crystal
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Liquid Crystal (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
2・・・回路基板
3・・・支持平板
4・・・第1のワイヤ(出力側ワイヤ)
5・・・間隙
6・・・保護樹脂膜
61・・・第1の保護樹脂膜
62・・・第2の保護樹脂膜
Claims (3)
- 端部に端子が形成された表示セルと、前記表示セルに間隙を介して並設され、駆動回路が形成された回路基板と、前記表示セルの端部に形成された端子と前記回路基板に形成された駆動回路とを前記間隙を跨いで電気的に接続するワイヤと、前記表示セルおよび前記回路基板を支持する支持板と、を備えた表示装置の製造方法であって、
前記ワイヤが設けられた前記表示セルの端部に、前記間隙を跨らないようにして第1保護樹脂膜を形成する第1樹脂膜形成工程と、
前記回路基板に、前記第1樹脂膜形成工程にて形成された第1保護樹脂膜に接触させるようにして第2保護樹脂膜を形成することにより、前記間隙に前記第1保護樹脂膜および前記第2保護樹脂膜が充填される第2樹脂膜形成工程と、
前記第1樹脂膜工程にて形成された第1保護樹脂膜、および前記第2樹脂膜工程にて形成された第2保護樹脂膜を硬化する硬化工程と、を有する表示装置の製造方法。 - 前記駆動回路は、表面に電極パッドが形成された駆動用ICチップであり、
前記ワイヤの一端が前記駆動用ICチップの前記電極パッドに、前記ワイヤの他端が前記表示セルの端部に形成された端子にそれぞれ接続されている、請求項1に記載の表示装置の製造方法。 - 前記表示セルは、液晶表示セルである、請求項1または2に記載の表示装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004052536A JP4562403B2 (ja) | 2004-02-26 | 2004-02-26 | 表示装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004052536A JP4562403B2 (ja) | 2004-02-26 | 2004-02-26 | 表示装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005242032A JP2005242032A (ja) | 2005-09-08 |
JP4562403B2 true JP4562403B2 (ja) | 2010-10-13 |
Family
ID=35023822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004052536A Expired - Fee Related JP4562403B2 (ja) | 2004-02-26 | 2004-02-26 | 表示装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4562403B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5044252B2 (ja) * | 2007-03-23 | 2012-10-10 | セイコーインスツル株式会社 | 表示装置の製造方法 |
JP5814521B2 (ja) * | 2010-08-09 | 2015-11-17 | シチズンファインデバイス株式会社 | 電子機器の製造方法 |
JP6905377B2 (ja) * | 2017-03-31 | 2021-07-21 | シチズンファインデバイス株式会社 | 画像表示装置及びその製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261916A (ja) * | 1990-03-13 | 1991-11-21 | Semiconductor Energy Lab Co Ltd | 液晶電気光学装置の作製方法 |
JPH04111366A (ja) * | 1990-08-30 | 1992-04-13 | Kyocera Corp | 画像装置 |
JPH05144875A (ja) * | 1991-11-18 | 1993-06-11 | Sharp Corp | 配線基板の実装方法 |
JPH0943621A (ja) * | 1995-07-28 | 1997-02-14 | Kyocera Corp | 液晶表示装置の製法 |
JPH1050742A (ja) * | 1996-07-29 | 1998-02-20 | Matsushita Electric Ind Co Ltd | チップ封止用樹脂の塗布方法 |
JPH10288948A (ja) * | 1997-04-16 | 1998-10-27 | Sharp Corp | 表示装置 |
JP2000306932A (ja) * | 1999-04-21 | 2000-11-02 | Denso Corp | 半導体装置の製造方法 |
-
2004
- 2004-02-26 JP JP2004052536A patent/JP4562403B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03261916A (ja) * | 1990-03-13 | 1991-11-21 | Semiconductor Energy Lab Co Ltd | 液晶電気光学装置の作製方法 |
JPH04111366A (ja) * | 1990-08-30 | 1992-04-13 | Kyocera Corp | 画像装置 |
JPH05144875A (ja) * | 1991-11-18 | 1993-06-11 | Sharp Corp | 配線基板の実装方法 |
JPH0943621A (ja) * | 1995-07-28 | 1997-02-14 | Kyocera Corp | 液晶表示装置の製法 |
JPH1050742A (ja) * | 1996-07-29 | 1998-02-20 | Matsushita Electric Ind Co Ltd | チップ封止用樹脂の塗布方法 |
JPH10288948A (ja) * | 1997-04-16 | 1998-10-27 | Sharp Corp | 表示装置 |
JP2000306932A (ja) * | 1999-04-21 | 2000-11-02 | Denso Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2005242032A (ja) | 2005-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5528403A (en) | Flat type display device having flexible wiring board and common wiring board bonded to display panel | |
KR100676156B1 (ko) | 전자 소자의 실장 방법, 전자 장치의 제조 방법, 회로 기판및 전자 기기 | |
CN100359369C (zh) | 显示装置 | |
JPH11204552A (ja) | 半導体装置のパッケージ方法および半導体装置 | |
US7422974B2 (en) | Method of manufacturing electronic component mounting body, electronic component mounting body, and electro-optical device | |
US20130242243A1 (en) | Methods and apparatus for connecting electrically conductive glass to a substrate in a liquid crystal panel | |
JP4562403B2 (ja) | 表示装置の製造方法 | |
JP2001210755A (ja) | 半導体装置用基板および半導体装置の製造方法 | |
JP4631742B2 (ja) | 電気光学装置、実装構造体、電気光学装置の製造方法及び電子機器 | |
JP2005286284A (ja) | 機能素子実装モジュール並びに光機能素子実装モジュール及びその製造方法 | |
JP3340779B2 (ja) | 半導体装置 | |
JP3404446B2 (ja) | テープキャリアパッケージ及びそのテープキャリアパッケージを備えた液晶表示装置 | |
US6498636B1 (en) | Apparatus and method for substantially stress-free electrical connection to a liquid crystal display | |
JP5648266B2 (ja) | 電気泳動表示装置の製造方法 | |
JPH0933940A (ja) | 表示パネル駆動用半導体チップの実装構造 | |
JP2010199410A (ja) | 半導体装置およびその製造方法 | |
JP6868937B2 (ja) | 液晶表示装置の製造方法 | |
JP2004087805A (ja) | 半導体装置、半導体装置の製造方法、回路基板、回路基板の製造方法、電気光学装置、電気光学装置の製造方法、電子機器及び接続構造 | |
JPH11258618A (ja) | 液晶表示素子およびその製法 | |
JP2007329321A (ja) | 電子部品実装基板、表示パネル、表示装置及び表示装置の製造方法 | |
JP2009272382A (ja) | 半導体装置、配線基板およびその製造方法 | |
JP2014071341A (ja) | 表示素子及び製造方法 | |
JP2022019337A (ja) | 液体吐出ヘッドおよびその製造方法 | |
KR100239781B1 (ko) | 액정표시장치 | |
JP5044252B2 (ja) | 表示装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070119 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100121 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100309 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100415 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100629 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100727 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130806 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |