JP4555143B2 - 基板の処理方法 - Google Patents

基板の処理方法 Download PDF

Info

Publication number
JP4555143B2
JP4555143B2 JP2005130914A JP2005130914A JP4555143B2 JP 4555143 B2 JP4555143 B2 JP 4555143B2 JP 2005130914 A JP2005130914 A JP 2005130914A JP 2005130914 A JP2005130914 A JP 2005130914A JP 4555143 B2 JP4555143 B2 JP 4555143B2
Authority
JP
Japan
Prior art keywords
insulating film
substrate
plasma
gas supply
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005130914A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005354041A5 (enrdf_load_stackoverflow
JP2005354041A (ja
Inventor
保男 小林
剛平 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2005130914A priority Critical patent/JP4555143B2/ja
Publication of JP2005354041A publication Critical patent/JP2005354041A/ja
Publication of JP2005354041A5 publication Critical patent/JP2005354041A5/ja
Application granted granted Critical
Publication of JP4555143B2 publication Critical patent/JP4555143B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31058After-treatment of organic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)
JP2005130914A 2004-05-11 2005-04-28 基板の処理方法 Expired - Fee Related JP4555143B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005130914A JP4555143B2 (ja) 2004-05-11 2005-04-28 基板の処理方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004141022 2004-05-11
JP2005130914A JP4555143B2 (ja) 2004-05-11 2005-04-28 基板の処理方法

Publications (3)

Publication Number Publication Date
JP2005354041A JP2005354041A (ja) 2005-12-22
JP2005354041A5 JP2005354041A5 (enrdf_load_stackoverflow) 2008-04-10
JP4555143B2 true JP4555143B2 (ja) 2010-09-29

Family

ID=35320470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005130914A Expired - Fee Related JP4555143B2 (ja) 2004-05-11 2005-04-28 基板の処理方法

Country Status (4)

Country Link
JP (1) JP4555143B2 (enrdf_load_stackoverflow)
KR (1) KR100887439B1 (enrdf_load_stackoverflow)
CN (1) CN100485884C (enrdf_load_stackoverflow)
WO (1) WO2005109483A1 (enrdf_load_stackoverflow)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101185757B1 (ko) * 2005-06-20 2012-09-25 고에키자이단호진 고쿠사이카가쿠 신고우자이단 층간 절연막 및 배선 구조와 그것들의 제조 방법
JP5119606B2 (ja) * 2006-03-31 2013-01-16 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
JP5194393B2 (ja) * 2006-06-23 2013-05-08 東京エレクトロン株式会社 半導体装置の製造方法
JP2008270706A (ja) * 2007-03-26 2008-11-06 Tokyo Electron Ltd 窒化珪素膜および不揮発性半導体メモリ装置
JPWO2008117798A1 (ja) * 2007-03-26 2010-07-15 東京エレクトロン株式会社 窒化珪素膜の形成方法、不揮発性半導体メモリ装置の製造方法、不揮発性半導体メモリ装置およびプラズマ処理装置
US8021975B2 (en) * 2007-07-24 2011-09-20 Tokyo Electron Limited Plasma processing method for forming a film and an electronic component manufactured by the method
US8197913B2 (en) * 2007-07-25 2012-06-12 Tokyo Electron Limited Film forming method for a semiconductor
JP2009088267A (ja) * 2007-09-28 2009-04-23 Tokyo Electron Ltd 成膜方法、成膜装置、記憶媒体及び半導体装置
TW201044462A (en) 2009-01-22 2010-12-16 Tokyo Electron Ltd A method for manufacturing semiconductor devices
JP5600885B2 (ja) * 2009-03-19 2014-10-08 凸版印刷株式会社 有機el用乾燥装置
JP5304759B2 (ja) * 2010-09-15 2013-10-02 東京エレクトロン株式会社 成膜方法及び半導体装置
JP5700513B2 (ja) * 2010-10-08 2015-04-15 国立大学法人東北大学 半導体装置の製造方法および半導体装置
JP2012164922A (ja) * 2011-02-09 2012-08-30 Yuutekku:Kk 圧電体の製造方法、圧電体及び電子装置
JP5364765B2 (ja) * 2011-09-07 2013-12-11 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
JP6559087B2 (ja) * 2016-03-31 2019-08-14 東京エレクトロン株式会社 基板処理装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3409984B2 (ja) * 1996-11-14 2003-05-26 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
JP3469761B2 (ja) * 1997-10-30 2003-11-25 東京エレクトロン株式会社 半導体デバイスの製造方法
JP3429171B2 (ja) * 1997-11-20 2003-07-22 東京エレクトロン株式会社 プラズマ処理方法及び半導体デバイスの製造方法
JP4355039B2 (ja) * 1998-05-07 2009-10-28 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
JP3921917B2 (ja) * 2000-03-31 2007-05-30 セイコーエプソン株式会社 微細構造体の製造方法
WO2002058130A1 (en) * 2001-01-22 2002-07-25 Tokyo Electron Limited Method for producing material of electronic device
JP4413556B2 (ja) * 2003-08-15 2010-02-10 東京エレクトロン株式会社 成膜方法、半導体装置の製造方法
JP4194521B2 (ja) * 2004-04-07 2008-12-10 東京エレクトロン株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
CN100485884C (zh) 2009-05-06
JP2005354041A (ja) 2005-12-22
KR100887439B1 (ko) 2009-03-10
WO2005109483A1 (ja) 2005-11-17
CN1943021A (zh) 2007-04-04
KR20070011463A (ko) 2007-01-24

Similar Documents

Publication Publication Date Title
JP4853857B2 (ja) 基板の処理方法,コンピュータ読み取り可能な記録媒体及び基板処理装置
JP4555143B2 (ja) 基板の処理方法
KR102576634B1 (ko) 에칭 방법 및 에칭 장치
KR100789007B1 (ko) 기판 처리 장치, 기판 처리 방법 및 기억 매체
JP4695697B2 (ja) プラズマ装置
JP4256763B2 (ja) プラズマ処理方法及びプラズマ処理装置
US20050257890A1 (en) Method of cleaning an interior of a remote plasma generating tube and appartus and method for processing a substrate using the same
JP4716370B2 (ja) 低誘電率膜のダメージ修復方法及び半導体製造装置
TWI749109B (zh) 基板處理裝置及隔熱板
JP2005093737A (ja) プラズマ成膜装置,プラズマ成膜方法,半導体装置の製造方法,液晶表示装置の製造方法及び有機el素子の製造方法
JP4924245B2 (ja) 半導体製造装置、半導体装置の製造方法及び記憶媒体
KR20010031586A (ko) 플라즈마 처리 방법
US7776736B2 (en) Substrate for electronic device capable of suppressing fluorine atoms exposed at the surface of insulating film from reacting with water and method for processing same
WO2024029320A1 (ja) 成膜方法および成膜装置
US20090266711A1 (en) Substrate processing apparatus
JPH1079377A (ja) 成膜・改質集合装置
JP2008159763A (ja) プラズマ処理装置
KR101384590B1 (ko) 반도체 디바이스 제조 방법 및 반도체 디바이스 제조 장치
JP4262126B2 (ja) 絶縁膜の形成方法
TW202238664A (zh) 電漿處理裝置、及電漿處理方法
JP2013191494A (ja) 有機電子デバイス、有機電子デバイスの製造方法、プラズマ処理装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080227

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080227

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091127

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100215

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100330

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100713

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100715

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130723

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees