JP4550786B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4550786B2 JP4550786B2 JP2006224318A JP2006224318A JP4550786B2 JP 4550786 B2 JP4550786 B2 JP 4550786B2 JP 2006224318 A JP2006224318 A JP 2006224318A JP 2006224318 A JP2006224318 A JP 2006224318A JP 4550786 B2 JP4550786 B2 JP 4550786B2
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- JP
- Japan
- Prior art keywords
- insulating film
- inorganic insulating
- gas
- organic insulating
- plasma treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Description
圧力:25mTorr
高周波:100MHz
高周波パワー:2400W
低周波:13.56MHz
低周波パワー:200W
ガス流量比(O2/CH4):0.5〜1.0
総ガス流量:200〜400sccm
とする。
14…下層無機絶縁膜 15…上層無機絶縁膜
16…有機絶縁膜 17…無機絶縁膜
21…貫通穴 22…溝
Claims (5)
- 銅配線を覆う第1の無機絶縁膜と、前記第1の無機絶縁膜上に形成され且つ穴パターンを有する有機絶縁膜と、前記有機絶縁膜上に形成され且つ溝パターンを有する第2の無機絶縁膜とを含んだ所定構造を形成する工程と、
前記穴パターンを有する有機絶縁膜をマスクとして用いて前記第1の無機絶縁膜をフルオロカーボン系ガスを含んだエッチングガスによってドライエッチングして、前記銅配線に達する貫通穴を形成する工程と、
酸素ガスと炭化水素ガスとの混合ガスを用いてプラズマ処理を行うことで、前記貫通穴によって露出した前記銅配線の表面に残存するフッ素を除去するとともに、前記溝パターンを有する第2の無機絶縁膜をマスクとして用いて前記有機絶縁膜をドライエッチングすることにより配線溝を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記第1の無機絶縁膜は下層部及び上層部を有し、
前記所定構造における前記第1の無機絶縁膜の上層部は、前記有機絶縁膜の穴パターンに対応した穴パターンを有し、
前記第1の無機絶縁膜をドライエッチングする際に、前記第1の無機絶縁膜の下層部がドライエッチングされる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記第1の無機絶縁膜をドライエッチングする際に、前記溝パターンを有する第2の無機絶縁膜をマスクとして用いて前記有機絶縁膜の上部分がドライエッチングされる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記プラズマ処理によって前記有機絶縁膜をドライエッチングする際に、前記有機絶縁膜は異方性エッチングされる
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記貫通穴を有する構造は、前記貫通穴を形成する工程の後から前記プラズマ処理を行う工程の前まで大気に晒されない
ことを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006224318A JP4550786B2 (ja) | 2006-08-21 | 2006-08-21 | 半導体装置の製造方法 |
US11/889,865 US7538037B2 (en) | 2006-08-21 | 2007-08-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006224318A JP4550786B2 (ja) | 2006-08-21 | 2006-08-21 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008047821A JP2008047821A (ja) | 2008-02-28 |
JP4550786B2 true JP4550786B2 (ja) | 2010-09-22 |
Family
ID=39101878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006224318A Expired - Fee Related JP4550786B2 (ja) | 2006-08-21 | 2006-08-21 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7538037B2 (ja) |
JP (1) | JP4550786B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4550786B2 (ja) * | 2006-08-21 | 2010-09-22 | 株式会社東芝 | 半導体装置の製造方法 |
FR2941560A1 (fr) * | 2009-01-28 | 2010-07-30 | Commissariat Energie Atomique | Procede pour empecher la formation de residus sur une couche a base d'un metal apres exposition de cette couche a un plasma contenant du fluor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150519A (ja) * | 1998-08-31 | 2000-05-30 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2000299376A (ja) * | 1999-04-14 | 2000-10-24 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2001144090A (ja) * | 1999-11-11 | 2001-05-25 | Nec Corp | 半導体装置の製造方法 |
JP2004247675A (ja) * | 2003-02-17 | 2004-09-02 | Renesas Technology Corp | 半導体装置の製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6372636B1 (en) * | 2000-06-05 | 2002-04-16 | Chartered Semiconductor Manufacturing Ltd. | Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene |
US7132369B2 (en) * | 2002-12-31 | 2006-11-07 | Applied Materials, Inc. | Method of forming a low-K dual damascene interconnect structure |
JP3715626B2 (ja) * | 2003-01-17 | 2005-11-09 | 株式会社東芝 | 半導体装置の製造方法および半導体装置 |
JP2005116801A (ja) * | 2003-10-08 | 2005-04-28 | Toshiba Corp | 半導体装置の製造方法 |
JP2006210508A (ja) * | 2005-01-26 | 2006-08-10 | Sony Corp | 半導体装置およびその製造方法 |
JP4550786B2 (ja) * | 2006-08-21 | 2010-09-22 | 株式会社東芝 | 半導体装置の製造方法 |
-
2006
- 2006-08-21 JP JP2006224318A patent/JP4550786B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-17 US US11/889,865 patent/US7538037B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150519A (ja) * | 1998-08-31 | 2000-05-30 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2000299376A (ja) * | 1999-04-14 | 2000-10-24 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2001144090A (ja) * | 1999-11-11 | 2001-05-25 | Nec Corp | 半導体装置の製造方法 |
JP2004247675A (ja) * | 2003-02-17 | 2004-09-02 | Renesas Technology Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20080045024A1 (en) | 2008-02-21 |
JP2008047821A (ja) | 2008-02-28 |
US7538037B2 (en) | 2009-05-26 |
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