JP4544902B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP4544902B2
JP4544902B2 JP2004129256A JP2004129256A JP4544902B2 JP 4544902 B2 JP4544902 B2 JP 4544902B2 JP 2004129256 A JP2004129256 A JP 2004129256A JP 2004129256 A JP2004129256 A JP 2004129256A JP 4544902 B2 JP4544902 B2 JP 4544902B2
Authority
JP
Japan
Prior art keywords
main surface
via hole
wiring layer
semiconductor chip
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004129256A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005311215A5 (zh
JP2005311215A (ja
Inventor
工次郎 亀山
彰 鈴木
芳央 岡山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2004129256A priority Critical patent/JP4544902B2/ja
Publication of JP2005311215A publication Critical patent/JP2005311215A/ja
Publication of JP2005311215A5 publication Critical patent/JP2005311215A5/ja
Application granted granted Critical
Publication of JP4544902B2 publication Critical patent/JP4544902B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004129256A 2004-04-26 2004-04-26 半導体装置及びその製造方法 Expired - Fee Related JP4544902B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004129256A JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004129256A JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2005311215A JP2005311215A (ja) 2005-11-04
JP2005311215A5 JP2005311215A5 (zh) 2007-06-07
JP4544902B2 true JP4544902B2 (ja) 2010-09-15

Family

ID=35439596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004129256A Expired - Fee Related JP4544902B2 (ja) 2004-04-26 2004-04-26 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JP4544902B2 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5194537B2 (ja) * 2007-04-23 2013-05-08 株式会社デンソー 半導体装置およびその製造方法
TWI394260B (zh) * 2007-10-31 2013-04-21 Adl Engineering Inc 具有多晶粒之半導體元件封裝結構及其方法
JP2009295676A (ja) * 2008-06-03 2009-12-17 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
JP2010245292A (ja) * 2009-04-06 2010-10-28 Panasonic Corp 光学デバイス、電子機器、及びその製造方法
US8853072B2 (en) * 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects
JP6012998B2 (ja) * 2012-03-29 2016-10-25 芝浦メカトロニクス株式会社 プラズマ処理方法
WO2024124532A1 (zh) * 2022-12-16 2024-06-20 京东方科技集团股份有限公司 功能基板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196397A (ja) * 2000-01-11 2001-07-19 Fujitsu Ltd 半導体装置及びその実装方法
JP2002348697A (ja) * 2001-05-21 2002-12-04 Shinko Electric Ind Co Ltd 配線基板の製造方法、半導体装置及びめっき装置
JP2003309221A (ja) * 2002-04-15 2003-10-31 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2003347471A (ja) * 2002-05-24 2003-12-05 Fujikura Ltd 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001196397A (ja) * 2000-01-11 2001-07-19 Fujitsu Ltd 半導体装置及びその実装方法
JP2002348697A (ja) * 2001-05-21 2002-12-04 Shinko Electric Ind Co Ltd 配線基板の製造方法、半導体装置及びめっき装置
JP2003309221A (ja) * 2002-04-15 2003-10-31 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2003347471A (ja) * 2002-05-24 2003-12-05 Fujikura Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2005311215A (ja) 2005-11-04

Similar Documents

Publication Publication Date Title
JP4307284B2 (ja) 半導体装置の製造方法
JP4130158B2 (ja) 半導体装置の製造方法、半導体装置
JP4850392B2 (ja) 半導体装置の製造方法
US7670955B2 (en) Semiconductor device and manufacturing method of the same
KR100608184B1 (ko) 반도체 장치 및 그 제조 방법
EP1482553A2 (en) Semiconductor device and manufacturing method thereof
JP2005101268A (ja) 半導体装置の製造方法
JP4828261B2 (ja) 半導体装置及びその製造方法
JP3970210B2 (ja) 半導体装置の製造方法
JP3970211B2 (ja) 半導体装置及びその製造方法
JP4544902B2 (ja) 半導体装置及びその製造方法
JP4307296B2 (ja) 半導体装置の製造方法
JP4282514B2 (ja) 半導体装置の製造方法
JP4511148B2 (ja) 半導体装置の製造方法
JP4845986B2 (ja) 半導体装置
JP4769926B2 (ja) 半導体装置及びその製造方法
JP2005260080A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070416

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070416

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071001

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100319

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100512

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100531

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100629

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130709

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130709

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees