JP2005311215A5 - - Google Patents
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- Publication number
- JP2005311215A5 JP2005311215A5 JP2004129256A JP2004129256A JP2005311215A5 JP 2005311215 A5 JP2005311215 A5 JP 2005311215A5 JP 2004129256 A JP2004129256 A JP 2004129256A JP 2004129256 A JP2004129256 A JP 2004129256A JP 2005311215 A5 JP2005311215 A5 JP 2005311215A5
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- via hole
- forming
- pad electrode
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004129256A JP4544902B2 (ja) | 2004-04-26 | 2004-04-26 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004129256A JP4544902B2 (ja) | 2004-04-26 | 2004-04-26 | 半導体装置及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005311215A JP2005311215A (ja) | 2005-11-04 |
JP2005311215A5 true JP2005311215A5 (zh) | 2007-06-07 |
JP4544902B2 JP4544902B2 (ja) | 2010-09-15 |
Family
ID=35439596
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004129256A Expired - Fee Related JP4544902B2 (ja) | 2004-04-26 | 2004-04-26 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4544902B2 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5194537B2 (ja) * | 2007-04-23 | 2013-05-08 | 株式会社デンソー | 半導体装置およびその製造方法 |
TWI394260B (zh) * | 2007-10-31 | 2013-04-21 | Adl Engineering Inc | 具有多晶粒之半導體元件封裝結構及其方法 |
JP2009295676A (ja) * | 2008-06-03 | 2009-12-17 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
JP2010245292A (ja) * | 2009-04-06 | 2010-10-28 | Panasonic Corp | 光学デバイス、電子機器、及びその製造方法 |
US8853072B2 (en) * | 2011-06-06 | 2014-10-07 | Micron Technology, Inc. | Methods of forming through-substrate interconnects |
JP6012998B2 (ja) * | 2012-03-29 | 2016-10-25 | 芝浦メカトロニクス株式会社 | プラズマ処理方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3494100B2 (ja) * | 2000-01-11 | 2004-02-03 | 富士通株式会社 | 半導体装置及びその実装方法 |
JP3530149B2 (ja) * | 2001-05-21 | 2004-05-24 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置 |
JP4212293B2 (ja) * | 2002-04-15 | 2009-01-21 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2003347471A (ja) * | 2002-05-24 | 2003-12-05 | Fujikura Ltd | 半導体装置及びその製造方法 |
-
2004
- 2004-04-26 JP JP2004129256A patent/JP4544902B2/ja not_active Expired - Fee Related
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