JP4516638B2 - Substrate for liquid crystal display device, liquid crystal display device and method for manufacturing the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate for a liquid crystal display device, a liquid crystal display device, and a manufacturing method thereof, and more particularly to an antistatic circuit for a liquid crystal display device and a manufacturing method thereof.
[0002]
[Prior art]
A liquid crystal display device, which is a kind of flat panel display device, has liquid crystal injected between two substrates on which electrodes are formed, and adjusts the amount of light transmitted by adjusting the strength of the voltage applied to the liquid crystal. .
[0003]
On the thin film transistor substrate of the liquid crystal display device, n gate lines and m data lines are formed which intersect with each other and define unit pixels in an n × m matrix form. Each pixel is provided with a pixel electrode that performs a display operation. The pixel electrode is connected to a gate line and a data line through a switching element such as a thin film transistor. At this time, the thin film transistor controls an image signal transmitted via the data line through a scanning signal applied via the gate line.
[0004]
Most of the manufacturing process of such a liquid crystal display device is performed on a glass substrate. Since the glass substrate is a non-conductor, the electric charge generated instantaneously is not dispersed below the substrate and is very sensitive to static electricity. Therefore, an insulating film, a TFT (thin film transistor) or the like formed on the glass substrate can be damaged by static electricity.
[0005]
In the manufacturing process of a liquid crystal display device, static electricity generated after bonding a TFT substrate and a color filter substrate to form a liquid crystal display panel has characteristics that the voltage is very high but the amount of charge is very low. The substrate is degraded. Static electricity is generated mainly when the substrate is cut, and most of the static electricity flows through the pad portions of the gate lines and data lines. Accordingly, the TFT channel near the gate and data line pads is likely to be deteriorated by static electricity.
[0006]
FIG. 1 is a configuration diagram of a liquid crystal display panel that exhibits an electrostatic phenomenon in a conventional liquid crystal display device.
[0007]
As shown in FIG. 1, the liquid crystal display panel is formed of a TFT substrate 10 and a color filter substrate 20. In FIG. 1, a pad portion 30 in which pads for connecting each wiring of the TFT substrate 10 and a driving circuit are formed and an active region 40 for displaying an actual image on a liquid crystal panel are displayed separately.
[0008]
A line 50 partially shown in the active region 40 indicates a pixel in which a defect appears due to a TFT deteriorated by static electricity. This is a phenomenon in which when static electricity generated from the pad portion 30 is transmitted to the active region 40, the channel of the TFT located near the pad portion 30 deteriorates, and thus an image appears without being accurately transmitted to the pixel. .
[0009]
FIG. 2 shows in detail the TFT in which the channel deterioration has occurred.
[0010]
As shown in FIG. 2, the gate line 60 and the data line 80 are overlapped with each other so that the end of the gate electrode 61 extended from the gate line 60 is a source electrode 81 extended from the data line 80. The drain electrode 82 is superimposed on the end of the gate electrode 61 on the opposite side of the source electrode 81 with respect to the gate electrode 61. At this time, the semiconductor film 70 is formed between the gate electrode 61 and the source electrode 81 and drain electrode 82.
[0011]
As described above, when static electricity flows into the TFT formed of the semiconductor film 70, the source electrode 81, the drain electrode 82, the gate electrode 61, and the like, a spark is generated between the source electrode 81 and the drain electrode 82, and the semiconductor film Damage 90 occurs in the channel region 70, and the TFT characteristics deteriorate.
[0012]
In order to reduce such defects of the liquid crystal display device due to static electricity, a method of making all the metal wirings one by one using a shot bar located at the edge of the substrate is widely used.
[0013]
However, if the amount of static electricity is large, the shot bar alone cannot completely prevent the damage caused by the static electricity, and the static electricity generated after the shot bar is removed cannot be blocked from flowing into the substrate. .
[0014]
Further, in the manufacturing process of the liquid crystal panel having such a structure, first, a test signal is applied to the shot bar in the state where the shot bar is present, and a screen display inspection of the liquid crystal substrate is performed. Thereafter, the substrate is cut to separate the individual liquid crystal substrates and the liquid crystal material is injected, and then the injection port is sealed. The shot bar is also cut when the substrate is cut. Next, after performing a screen display inspection in which different test signals are applied to individual pads using probes that directly contact each pad, a drive circuit is attached to the liquid crystal panel.
[0015]
[Problems to be solved by the invention]
As described above, in the conventional manufacturing process, since the shot bar is also removed when the substrate is cut, it is difficult to protect the substrate from static electricity generated when the substrate is cut. In addition, since the liquid crystal substrate is selected and the polarizing plate is attached only by a simple defect inspection in a state where there is a shot bar, the probability that the polarizing plate can be attached to a defective liquid crystal substrate is high. If such a defective liquid crystal panel is found in an inspection performed after the shot bar is removed, an expensive polarizing plate must be disposed of together, which may be costly.
[0016]
An object of the present invention is to protect a liquid crystal display substrate from static electricity regardless of the amount of electrostatic charge.
[0017]
Another object of the present invention is to minimize pixel defects by blocking static electricity from flowing into the substrate after the shot bar removing step and thereafter.
[0018]
Another object of the present invention is to reduce the manufacturing cost by preventing static electricity generated during the process by changing the manufacturing process of the liquid crystal substrate.
[0019]
[Means for Solving the Problems]
To achieve the above object, the present invention provides a transparent insulating first substrate having a plurality of pixel electrodes for displaying an image and a semiconductor element, and the semiconductor element formed on the first substrate. A gate line connected and intersecting the data line; A plurality of thin film transistors connected in series between two adjacent gate lines or between the data lines, each gate electrode being connected to each other, and one terminal connected to the gate electrode, the two adjacent gate lines Or having a plurality of capacitors connected to the other terminals of the data lines, A plurality of spark induction circuits for consuming static electricity generated from the first substrate.
[0020]
This Are connected in parallel between two adjacent wirings. When static electricity is generated in a wiring, a spark is first generated in the TFT in the spark induction circuit, and the source electrode and the drain electrode are connected. A strong current is induced. At this time, the surge current is converted into Joule heat and energy is lost. Therefore, the TFT in the active region can be protected from static electricity. It is also possible to distribute static electricity generated in the wiring to adjacent wiring.
[0023]
On the other hand, a resistor and a capacitor are connected in series between the data line and the dummy gate line, and a different resistor is connected between another data line and the capacitor adjacent to the data line to disperse static electricity. It can also be used as an electrostatic protection element.
[0024]
The electrostatic charging circuit is formed inside a region surrounded by a first electrostatic charging circuit formed outside a region surrounded by a seal that stitches the TFT substrate with a counter substrate that is bonded to the TFT substrate to form a liquid crystal substrate. The second electrostatic charging circuit is divided.
[0025]
The first electrostatic charging circuit is a circuit in which two capacitors are connected in series between adjacent wirings, and a large number of such circuits are connected in parallel between the adjacent wirings.
[0026]
The second electrostatic charging circuit is for finally removing static electricity flowing into the active region, and includes a capacitor formed between each wiring and the common electrode. This capacitor consists of a separate counter electrode plate and wiring connected to a common electrode. The counter electrode plate facing the gate line in the wiring is made of a source / drain metal of the thin film transistor, and the counter electrode plate facing the data line in the wiring is made of a gate metal.
[0027]
The first electrostatic charging circuit and the second electrostatic charging circuit can store and eliminate static electricity generated in the wiring in the capacitor.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 3 is a plan view schematically showing a liquid crystal display substrate according to the present invention. As shown in FIG. 3, a large number of gate lines 100 are formed in the horizontal direction on the transparent insulating substrate 10, and a gate pad 101 is formed at one end of the gate line 100. In addition, a large number of data lines 200 are formed in the vertical direction so as to intersect the gate line 100, and a data pad 201 is formed at one end of the data line 200, and the data line 200 and the gate line 100 intersect. A TFT as a switching element is formed in the pixel region PX defined as described above. Such an area composed of a large number of pixel areas PX becomes an active area 41 in which an image is embodied.
[0039]
Shot bars 102 and 202 are formed inside the periphery of the substrate 10 at the end portions of the gate line 100 and the data line 200 so as to make it difficult for the gate line 100 and the data line 200, respectively. , 202 are connected to each other. As a result, since all the gate lines 100 and the data lines 200 are connected together, when static electricity is generated in the gate pads and the data pads 101 and 201, the static electricity is discharged through the shot bars 102 and 202 as a route. The
[0040]
On the other hand, when the generated static electricity has a relatively large charge amount, static electricity can flow into the active region 41 even if the shot bars 102 and 202 exist. Further, when static electricity is generated after the manufacture of the TFT substrate 10 is completed and the shot bars 102 and 202 are removed along the cutting line 11, the static electricity easily flows into the active region 41. In order to discharge such static electricity more effectively, a guard ring or dummy gate wiring that surrounds the periphery of the active region between the portion A of the substrate 10, that is, between the pads 101 and 201 and the active region 41. An electrostatic discharge circuit connected to a dummy wiring 110 configured by electrically connecting 111 and the dummy data wiring 112 is placed. On the other hand, the cutting line 11 can be positioned outside the shot bars 102 and 202.
[0041]
4 is an enlarged plan view of the portion A of FIG. 3 according to the first embodiment of the present invention. For convenience, only the TFT substrate and the seal 90 are shown, and the color filter substrate is not shown. A cutting line 11 for cutting the shot bar 102 formed along the edge of 10, a line 21 corresponding to the edge of the color filter substrate 20, and a line 41 for dividing the active region are indicated by dotted lines.
[0042]
As shown in FIG. 4, the shot bar 102 is positioned inside the cutting line 11, and the pad 101 connected to the shot bar 102 is connected to the cutting line 11 and the line 21 corresponding to the edge of the color filter substrate 20. A wiring 100 located between them and extending from the pad 101 extends toward the active region 41. Inside the line 21 corresponding to the edge of the color filter substrate 20, a seal 90 for bonding the TFT substrate 10 and the color filter substrate 20 is formed between the two substrates 10, 20. A metal guard ring or dummy wiring 110 is formed on the outer peripheral edge, and an electrostatic protection circuit such as an electrostatic protection diode 120, a spark induction circuit, and an electrostatic charging circuit is formed between each wiring 100 and the dummy line 110. Has been.
[0043]
First, the electrostatic protection diode shown in FIG. 5 will be described. As shown in FIG. 5, the electrostatic protection diode 120 is connected to the wiring 100 outside the active region 41.
[0044]
The gate terminal and the drain terminal of the TFT are connected to the dummy line 110, the first diode D1 is formed in such a manner that the source terminal is connected to the wiring 100, and the gate terminal and the drain terminal are connected to the wiring 100. The second diode D2 is formed in such a manner that the source terminal is connected to the dummy line 110. That is, the first and second diodes D1 and D2 are connected in antiparallel between the dummy line 110 and the wiring 100.
[0045]
The diode 120 used in such an electrostatic protection circuit is usually made of high-resistance amorphous silicon, whereas the wiring 100 is made of a low-resistance material. Therefore, the amount of static electricity flowing into the active region 41 along the wiring 100 having a low resistance may be larger than the amount of static electricity flowing through the diode 120 to the dummy line 110. Therefore, it is difficult to completely protect the liquid crystal display substrate from static electricity having a large charge amount only with such an electrostatic protection circuit.
[0046]
The electrostatic discharge function is enhanced by a spark induction circuit and an electrostatic charging circuit.
[0047]
The spark induction circuit ST130 and the first electrostatic charging circuit FC140 described above with reference to FIG. 4 are connected to the wiring 100 between the seal 90 and the pad 101, and the second electrostatic charging is performed between the seal 90 and the active region 41. A circuit 150 is connected. Therefore, static electricity is effectively discharged.
However, when the spark induction circuit 130 and the electrostatic charging circuits 140 and 150 are connected to the wiring 100 outside the seal 90 as described above, the circuits 130, 140, and 150 are exposed to the outside, and therefore, due to corrosion and impact by air. Circuit damage can occur.
[0048]
FIG. 6 is an enlarged plan view of the portion A of FIG. 3 according to the second embodiment of the present invention, in which a circuit for preventing static electricity is located inside the seal. As shown in FIG. 6, the spark induction circuit ST130 is connected to the wiring 100 between the active region 41 and the seal 90, and the electrostatic protection diode 120 is located outside the active region 41 in the same manner as in the previous embodiment. It is connected to the wiring 100.
[0049]
Although not shown, the first electrostatic charging circuit 140 and the second electrostatic charging circuit 150 may be formed inside the seal 90.
[0050]
The spark induction circuit ST can be configured in various forms, and will be described by dividing it into first to fourth spark induction circuits ST1, ST2, ST3, ST4 with reference to FIGS.
[0051]
First, the first spark induction circuit ST1 is shown in FIG. As shown in FIG. 7, the first spark induction circuit ST1 includes a number of TFTs connected in series between two adjacent wirings 100 and capacitors C1 and C2. That is, the gate electrodes of a large number of TFTs are connected together between the two wirings 100, and the source and drain electrodes of the TFT are connected to the drain and source electrodes of adjacent TFTs. Capacitors C <b> 1 and C <b> 2 are connected to the adjacent wiring 100, respectively. A number of such first spark induction circuits ST1 are connected in parallel between the adjacent wirings 100 to protect the substrate from static electricity.
[0052]
The operation of the first spark induction circuit ST1 is specifically as follows.
[0053]
When the static electricity generated from the pad 101 flows into the first spark induction circuit ST1, the TFT of the first spark induction circuit ST1 first generates a spark so that the static electricity is consumed, thereby protecting the TFT in the active region from the static electricity. Can do. On the other hand, in the case of static electricity generated in the wiring 100, the capacitors C1 and C2 are charged to turn on the TFT, so that the static electricity can be discharged to the entire wiring 100. When there are a large number of TFTs connected in series in the first spark induction circuit ST1, an increase in current flowing between the wirings 100 can be effectively suppressed.
[0054]
Next, the second spark induction circuit ST2 is shown in FIG.
[0055]
As shown in FIG. 8, the second spark induction circuit ST2 includes a TFT and a capacitor having one terminal connected to the gate electrode of the TFT. The gate electrode and drain electrode of each TFT are electrically connected to each other, and a capacitor C3 is formed between the common electrode formed on the gate electrode and the upper color filter substrate (not shown). A large number of such second spark induction circuits ST2 are connected to each wiring 100. The second spark induction circuit ST2 is formed to be similar to the TFT formed in each pixel, and can easily increase the capacitor value as compared with the first spark induction circuit ST1, and simultaneously from two or more wirings. A spark can be easily induced even when static electricity flows. Although the common electrode is used as the storage capacitor electrode here, a separate electrode can be formed in addition to the common electrode.
[0056]
Next, the third spark induction circuit ST3 shown in FIG. 9 is different from the case where a large number of capacitors C3 are used in the second spark induction circuit ST2, and one terminal of one capacitor C4 is shared by all TFTs. It is connected. The function of the third spark induction circuit ST3 is almost the same as the function of the second spark induction circuit ST2. Here, the common electrode is used as the holding electrode as in the second spark circuit, but a separate common electrode may be used. Such first to third spark induction circuits ST1, ST2, and ST3 may be formed inside the seal 90.
[0057]
Finally, the fourth spark induction circuit ST4 is shown in FIG.
[0058]
As shown in FIG. 10, a dummy wiring or a guard ring including a dummy gate line 111 and a dummy data line 112 electrically connected to the dummy gate line 111 is formed, and a TFT element is formed on the dummy gate line 111. Is formed. The source electrode of the TFT is connected to the data line 200, and the drain electrode is connected to one electrode of the capacitor C5 so as to face the dummy gate line 111.
[0059]
In such a fourth spark induction circuit, when a part of static electricity is transmitted to the dummy wiring, the static electricity is charged in the capacitor C5 and the TFT is turned on, and static electricity generated from the dummy gate line and the data lines 111 and 112 is generated. Are distributed throughout the dummy wiring and the data wiring 200. In addition, when the amount of static electricity generated from the data line 200 is large, a spark may occur in the TFT and the static electricity may be consumed while the TFT is destroyed.
[0060]
Eventually, such spark induction circuits ST1, ST2, ST3, ST4 all convert electrostatic energy into Joule heat by burning the TFT. Therefore, static electricity can disappear without affecting the circuits in the active region.
[0061]
Next, the first electrostatic charging circuit FC is shown in FIG.
[0062]
As shown in FIG. 11, the first electrostatic charging circuit FC is a circuit in which capacitors C <b> 6 and C <b> 7 are connected in series, and a large number of such circuits are connected in parallel between adjacent wirings 100. Similarly to the spark induction circuit ST, the first electrostatic charging circuit FC can also be formed outside the seal 90. Such a first electrostatic charging circuit FC has a function of storing and extinguishing static electricity generated in the wiring 100.
[0063]
A second electrostatic charging circuit formed between the seal 90 and the active region 41 is shown in FIG. The second electrostatic charging circuit is for finally removing static electricity flowing into the active region 41, and is connected between each wiring 100 and a separately formed common electrode Vcom as shown in FIG. Capacitor C8. Such an electrostatic charging circuit also has a function of storing and eliminating static electricity in the capacitor C8.
[0064]
Next, referring to FIGS. 13 to 15, the plane and cross-sectional structure of the fourth spark induction circuit shown as the circuit diagram in FIG. 10 will be described in more detail.
[0065]
FIG. 13 is a layout diagram of the fourth spark induction circuit, and FIG. 14 is a cross-sectional view taken along line XIV-XIV ′ of FIG. As shown in FIGS. 13 and 14, the fourth spark induction circuit includes a plurality of dummy gate lines 111, a gate insulating film 3, a semiconductor pattern 700 formed on the upper gate insulating film 3 of the dummy gate lines 111, a semiconductor A TFT pattern composed of a data line 200 and a metal pattern 103 that overlaps both ends of the pattern 700, respectively, and a dummy gate line 111 that is connected to the metal pattern 103 and overlaps the interlayer insulating film 4 and the gate insulating film 3 therebetween. And a transparent conductive pattern 6 forming a storage capacitor. In addition, dummy data lines 112 are formed in the vertical direction outside the fourth spark induction circuit, and the dummy data lines 112 are connected to all the dummy data lines 111 through the connection pattern 5.
[0066]
More specifically, the dummy gate line 111 is formed in the lateral direction on the substrate 10, and the gate insulating film 3 is covered on the dummy gate line 111. On the gate insulating film 3 above the dummy gate line 111. A semiconductor pattern 700 is formed. A data line 200 is formed in the vertical direction on the gate insulating film 3 so as to overlap with one end of the semiconductor pattern 700, and the semiconductor pattern 700 is formed on the opposite side of the data line 200 with respect to the semiconductor pattern 700. A metal pattern 103 overlapping the other end is formed, and an ohmic contact layer 710 for improving electrical contact characteristics is formed on a surface where the semiconductor pattern 700, the data line 200, and the metal pattern 103 are in contact with each other. Yes. The interlayer insulating film 4 covers the data lines 200, the dummy data lines 112, and the semiconductor 700, and the contact hole C <b> 3 is opened in the interlayer insulating film 4 so as to expose the metal pattern 103. A transparent conductive pattern 6 for a capacitor that overlaps with the gate line 111 is formed, and this pattern 6 is connected to the metal pattern 103 through the contact opening C3.
[0067]
Here, the interval between the dummy gate lines 111 is arranged so as to be narrower than the gate line of the active region so that the wiring does not occupy a large area in a portion other than the active region.
[0068]
As shown in FIG. 14, the contact C1 opened in the interlayer insulating film 4 with the dummy gate line 112 exposed, and the interlayer insulating film 4 and the gate insulating film 3 opened with the dummy gate line 111 exposed. The transparent connection pattern 5 connects the dummy data line 112 and the dummy gate line 111 through the contact hole C2. That is, the dummy data line 112 and the dummy gate line 111 provided with the spark induction circuit are electrically connected.
[0069]
In the spark induction circuit having the thin film transistor and the capacitor structure, when static electricity flows from the data line 200 or the dummy data line 112, the static electricity is charged between the transparent conductive pattern 700 for the capacitor and the dummy gate line 111 and is consumed. To do. Alternatively, the static electricity generated from the dummy data line 112 may cause a spark in the TFT, and the TFT may burn, so that the static electricity is consumed in a form in which the electrostatic energy is converted into Joule heat.
[0070]
15 and 16 are another layout diagram of the fourth spark induction circuit and a cross-sectional view of XVI-XVI 'of FIG. 15, and the capacitor transparent conductive pattern (reference numeral 6 in FIG. 14) is not separately provided. Instead, since the metal pattern 104 is extended so as to overlap with the dummy gate line 111 by a certain area, a sufficient storage capacity is formed between the metal pattern 104 and the dummy gate line 111.
[0071]
The principle that static electricity is consumed is the same as the above-described structure.
[0072]
In order to prevent static electricity from flowing into the active region, a dummy pixel having a structure similar to each pixel in the active region can be placed outside the active region. The structure of such a dummy pixel is shown in FIG.
[0073]
17 is a layout view showing a first electrostatic discharge dummy pixel according to the present invention, and FIG. 18 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG. As shown in FIGS. 17 and 18, gate lines or dummy gate lines 100 are formed on the first substrate 10 in the lateral direction. At this time, a part of the gate line or the dummy gate line 100 becomes a dummy gate electrode.
[0074]
A gate insulating film 3 is covered on the dummy gate line 100, and a dummy amorphous silicon layer 700 is formed on the gate insulating film 3 on the upper part of the portion to be a dummy gate electrode.
[0075]
On the gate insulating film 3, dummy data lines 110 are formed in the vertical direction. A region where the dummy data line 110 and the dummy gate line 100 intersect becomes a dummy pixel DP. The dummy pixel DP may be defined by intersecting a gate line and a dummy data line or a dummy gate line and a data line.
[0076]
A dummy source electrode 113 that is a branch of the dummy gate line 110 overlaps with one end portion of the doped amorphous silicon layer 700, and a dummy drain electrode 114 overlaps with an end portion on the opposite side of the dummy source electrode 113. is doing. The surface where the dummy source / drain electrodes 113 and 114 and the dummy amorphous silicon layer 700 are in contact with each other is n ⁺ An amorphous silicon layer 710 doped with impurities at a high concentration is formed.
[0077]
The width DW of the dummy source and drain electrodes 113 and 114 is the width of the channel formed in the dummy amorphous silicon layer 700 serving as the semiconductor layer, and the distance DL between the dummy source electrode 113 and the dummy drain electrode 114 is the channel. It becomes the length. Here, the width DW of the dummy source and drain electrodes 113 and 114 is different from the width of the source and drain electrodes formed in the pixel region in the display region, and is between the dummy source electrode 113 and the dummy drain electrode 114. The distance DL is different from the distance between the source and drain electrodes formed in the pixel region. At this time, as described above, in order to allow static electricity to easily flow into the dummy pixel, the ratio between the channel width and the channel length in the dummy pixel is equal to the channel width and the channel length in the pixel in the display area. It is preferable that the ratio is larger than the ratio and more than twice.
[0078]
A protective film 4 is formed on the dummy data line 110 and the dummy amorphous silicon layer 700, and a contact hole C4 for exposing the dummy drain electrode 114 is formed in the protective film 4. On the protective film 4, a pixel electrode 300 connected to the dummy drain electrode 114 through the contact hole C4 is formed of an ITO film. At this time, a part of the pixel electrode 300 overlaps with a part of the adjacent dummy gate line 100.
[0079]
An alignment film 7 that covers the protective film 4 is formed on the entire surface of the first substrate 10.
[0080]
On the other hand, a black matrix 400 having an opening in the dummy pixel region DP is formed on the second substrate 11 on the surface facing the first substrate 10, and an edge portion overlaps with the black matrix 400 in the pixel region DP. The color filter 500 is formed. A common electrode 600 and an alignment film 8 made of a transparent conductive film are sequentially formed on the color filter 500 and the black matrix 400.
[0081]
In such a liquid crystal display device according to the present invention, the black matrix 400 is formed on the second substrate 11, but it can also be formed on the first substrate 10.
[0082]
In this way, it is possible to prevent static electricity flowing into the display area by adding dummy gate lines and dummy data lines outside the display area.
[0083]
Further, as described above, one or more dummy TFTs of the dummy pixel can be formed. This will be described in detail.
FIG. 19 is a layout view illustrating a second electrostatic discharge dummy pixel according to the present invention. As shown in FIG. 19, most of the structure is similar to the structure of FIG. 17, but the dummy gate electrode 101 connected to the dummy gate line 100 is extended long. Further, three dummy source electrodes 115, 116, 117 are connected to the dummy data line 110, and dummy drain electrodes 125, 126, 127 facing the dummy source electrodes 115, 116, 117 are formed. Each is connected to one dummy pixel electrode 301 through contact holes C5 and C6C7.
[0084]
At this time, the width DW1 of the first dummy source and drain electrodes 115 and 125 is smaller than the width DW2 of the second dummy source and drain electrodes 116 and 126, and the width DW2 of the second dummy source and drain electrodes 116 and 126 is third. The dummy source and drain electrodes 117 and 127 are smaller than the width DW3. Here, the distances DL between the dummy source electrodes 115, 116, 117 and the dummy drain electrodes 125, 126, 127 are all constant, but may be formed different from each other.
[0085]
In this manner, by causing static electricity generated by changing the structure of the dummy thin film transistor to quickly flow into the dummy pixel, pixel defects due to static electricity can be removed in the display region.
[0086]
Next, another discharge pattern for preventing static electricity from flowing into the display area will be described.
[0087]
20 is a plan view showing a first electrostatic discharge pattern according to the present invention, FIG. 21 is a cross-sectional view taken along line XXI-XXI ′ of FIG. 20, and FIG. 22 is an end view of the electrostatic discharge pattern. It is a perspective view which shows the electrical storage device formed. A data line or a dummy data line 110 is formed on the gate insulating film 3 on the substrate 10, and a discharge amorphous silicon pattern 704 is formed on the gate insulating film 3. A portion of the data line or dummy data line 110 extending partly becomes the first electrode pattern 118. The first electrode pattern 118 is formed so as to overlap with one end of the amorphous silicon pattern 704, The second electrode pattern 128 is superimposed on the opposite side. At this time, the end portions of the first and second electrode patterns 118 and 128 are formed in a sharp shape, and ohmic contact is made at a portion where the first and second electrode patterns 118 and 128 and the amorphous silicon pattern 704 are in contact with each other. N which is the contact layer ⁺ An amorphous silicon pattern 710 is formed. A protective film 4 is formed on the dummy data line 110 and the first and second electrode patterns 118 and 128, and a contact hole C8 that exposes the second electrode pattern 128 is formed on the protective film 4. A capacitor ITO pattern 302 is formed on the protective film 4 so as to overlap the second electrode pattern 128. The capacitor ITO pattern 302 is connected to the second electrode pattern 128 through the contact C8.
[0088]
That is, the discharge pattern includes an amorphous silicon pattern 704, a capacitor ITO pattern 302 for storing static electricity, and first and second electrodes that electrically connect the two patterns 704 and 302 to the dummy data line 110. Patterns 118 and 128 are included.
[0089]
When static electricity is generated, tunneling occurs in the amorphous silicon pattern 704 faster than the breakdown, and the static electricity moves to the capacitor ITO pattern 302 via the second electrode pattern 128. As described above, the reason why the tunneling effect is larger than the breakdown is that the ends of the first and second electrode patterns 118 and 128 are formed in a sharp shape, and electric charges concentrate on the ends.
[0090]
As shown in FIG. 22, the ITO pattern 302 of such a discharge pattern corresponds to face the common electrode 600 of the upper substrate, and the liquid crystal material LC exists between the ITO pattern 302 and the common electrode 600. Therefore, the storage capacitor C at the end of the discharge pattern _ST Is formed. Therefore, the static electricity moved to the capacitor ITO pattern 302 is stored in the holding capacitor, and thus does not affect the TFT in the active region A / A.
[0091]
FIG. 23 is a plan view showing a second electrostatic discharge pattern according to the present invention. The second electrostatic discharge pattern is based on the first electrostatic discharge pattern described above. However, two or more discharge elements are connected in parallel to the capacitor ITO pattern 302 and the dummy data line 110.
[0092]
As shown in FIGS. 21 and 23, the first discharge element D1 including the first amorphous silicon pattern 704 and the first and second electrode patterns 118 and 128 on the gate insulating film 3, and the second amorphous silicon. A second discharge element D2 including the pattern 705 and the third and fourth electrode patterns 119 and 129 is formed. The first and second discharge elements are connected to the dummy data line 110 in parallel. Contact holes C8 and C9 exposing the second and fourth electrode patterns 128 and 129 are formed in the protective film 4, and the second and fourth electrode patterns 128 and 129 pass through the contact holes C8 and C9 and the capacitor ITO. It is in contact with the pattern 302.
[0093]
Like the first electrostatic discharge pattern described above, the first to fourth electrode patterns 118, 128, 119, and 129 have sharp ends, and the first and third electrode patterns 118 and 119 are formed. The second and fourth electrode patterns 128 and 129 are paired to face the first and second amorphous silicon patterns 704 and 705, and the static electricity flowing along the dummy data lines 110 is pointed. It is easily discharged and stored in the capacitor ITO pattern 302 through the portion.
[0094]
The number of discharge elements D1 and D2 connected in parallel can be increased as necessary.
[0095]
FIG. 24 is a plan view showing a third pattern for electrostatic discharge according to the present invention. As shown in FIG. 24, the discharge pattern according to the third embodiment has a configuration in which two or more discharge elements are connected in parallel to two adjacent dummy data lines or two data lines or dummy data lines and data lines. It is.
[0096]
As shown in FIG. 24, the second and fourth electrode patterns 128 and 129 of the first and second discharge elements D1 and D2 having a structure like the second electrostatic discharge pattern are connected to the adjacent data line 120. .
[0097]
Even in this case, the number of discharge elements can be increased as necessary.
[0098]
In the first to third electrostatic discharge patterns described above, since the capacitor is formed after the upper and lower substrates for the liquid crystal display device are assembled, static electricity generated during the substrate assembly process, the liquid crystal injection process, or the defect inspection process. It is a structure suitable for discharging.
[0099]
Hereinafter, the fourth electrostatic discharge pattern will be described with reference to FIG.
[0100]
FIG. 25 is a plan view showing a fourth electrostatic discharge pattern. As shown in FIG. 25, it has the same structure as the first electrostatic discharge pattern except that a dummy metal line 130 is formed on the substrate 10 in the lateral direction. At this time, since the dummy metal line 130 is grounded and the gate insulating film and the protective film are overlapped with the ITO pattern 302 for the capacitor, a tunnel ring is generated in the amorphous silicon pattern 704 and static electricity is generated. When moving from the first electrode pattern 118 into the second electrode pattern 128 and the capacitor ITO pattern 302, the capacitor ITO pattern 302 and the dummy metal line 130 form a capacitor.
[0101]
The structure such as the fourth pattern for electrostatic discharge can discharge static electricity more effectively because another capacitor structure is constructed in the process of forming the wiring in the substrate.
[0102]
Hereinafter, a method for manufacturing an electrostatic discharge pattern according to the present invention will be described with reference to FIGS. 21, 25, and 26 to 31.
[0103]
First, as shown in FIG. 26, a metal layer is stacked on the substrate 10 and patterned to form gate lines and dummy gate lines 100 inside and outside the display region, respectively. In the case of the fourth electrostatic discharge pattern structure, the dummy metal line 130 can be formed outside the display region in parallel with the gate line and the dummy gate line 100 in this process.
[0104]
Next, as shown in FIG. 27, a gate insulating film 3 is laminated with silicon nitride or silicon oxide, and amorphous silicon and doped amorphous silicon are sequentially laminated thereon, followed by patterning, and discharging. An amorphous silicon pattern 704 and a doped amorphous silicon layer 710 are formed outside the display region.
[0105]
Next, as shown in FIG. 28, a metal layer is deposited and patterned to form data lines and dummy data lines 110, first and second electrode patterns 118 and 128, and the like. When two or more discharge elements D are formed, a number of pairs of electrode patterns 119 and 129 are formed in this process. Next, n exposed to the outside ⁺ Amorphous silicon material is removed.
[0106]
Next, as shown in FIG. 29, the protective film 4 is deposited thereon, and as shown in FIG. 30, the gate insulating film 3 and the protective film 4 are patterned to expose the second and fourth electrode patterns 128 and 129. Contact holes C8 and C9 are formed.
[0107]
Next, as shown in FIG. 31, an ITO material is deposited and patterned to form an IOT pattern 302 for a capacitor.
[0108]
Next, another form of electrostatic protection circuit for protecting a substrate from static electricity will be described with reference to FIG.
[0109]
FIG. 32 is an electrical equivalent circuit diagram showing still another electrostatic protection circuit connected to part A of FIG. As shown in FIG. 32, the first resistor R1 and the capacitor C1 are connected in series between the data line 200 and the dummy gate wiring 111, and the data line 200 adjacent to the capacitor C1 is connected by the second resistor R2. They are connected in series. The dummy gate line is electrically connected to the dummy data line 112 formed outside the data line 200.
[0110]
Static electricity generated from the data line 200 is instantaneously dispersed while passing through the resistors R1 and R2. Static electricity generated from the dummy data line 112 spreads along the dummy gate line 111 and is stored in the capacitor C 1 between the data line 200 and the dummy gate line 111.
[0111]
This will be further described with reference to FIGS.
[0112]
FIG. 33 is a plan view showing such an electrostatic protection circuit pattern, and FIG. 34 is a sectional view taken along line XXXIV-XXXIV ′ of FIG.
[0113]
In general, since the electrostatic protection element must be formed in a narrow region between the active region and the pad, there is a limit in minimizing the electrostatic capacitance by increasing the capacitance of the capacitor. Uses a semiconductor pattern, that is, a resistor, that connects each capacitor to an adjacent data line, thereby improving electrostatic dispersibility.
[0114]
As shown in FIGS. 33 and 34, a large number of gate lines (not shown) are formed in the horizontal direction on the transparent insulating substrate 10, and dummy gate wirings 111 are formed in the horizontal direction outside the gate lines. The gate line and the dummy gate wiring 111 are covered with the gate insulating film 3.
[0115]
A large number of semiconductor patterns 707 and 708 are formed of amorphous silicon or the like near the dummy gate wiring 111 on the gate insulating film 3, and a large number of data lines 200 are formed. At this time, two or more semiconductor patterns 707 and 708 are positioned between two adjacent data lines 200. When one of the semiconductor patterns 707 is a first semiconductor pattern 707 and the other pattern is a second semiconductor pattern 708, the semiconductor pattern 707 faces the first electrode 12 and the first electrode 12 connected to the data line 200. Thus, the corresponding second electrodes 13 are formed so as to overlap with both ends of the first semiconductor pattern 707. In addition, the third electrode 15 connected to another adjacent data line 200 and the corresponding fourth electrode 14 are formed so as to be opposed to both ends of the second semiconductor pattern 708 so as to face the third electrode 15. Yes. An ohmic contact layer 717 for improving contact characteristics is provided on a surface where the first and second electrodes 12 and 13 and the first semiconductor pattern 707 are in contact with each other, and the third and fourth electrodes 15 and 14 and the second semiconductor pattern 708 are in contact with each other. Is formed.
[0116]
At least one dummy data line 112 is formed outside the data line 200 in parallel with the data line 200.
[0117]
The data line 200, the dummy data wiring 112, and the like are covered with the protective film 4, so that the dummy data wiring 112, end portions of the dummy gate wiring 111, and the second and fourth electrodes 13 and 14 are exposed in the protective film 4. The contact ports C1, C2, C3, C4 are formed in the contact holes C1, C2, and C4.
[0118]
On the protective film 4, a connection pattern 5 that connects the dummy data line 112 and the dummy gate line 111 is formed so as to overlap the dummy data line 112 and the dummy gate line 111, and the second electrode 13 and the fourth electrode are formed. 14 and the dummy gate wiring 111 are formed, and a capacitor pattern 9 is formed which is connected to the second and fourth electrodes 13 and 14 through contact holes C3 and C4. The connection pattern 5 and the capacitor pattern 9 may be formed of transparent ITO.
[0119]
As described above, since the dummy gate line 111 is connected to the dummy data line 112, static electricity generated from the dummy gate line 112 is transmitted to the dummy gate line 111, and the capacitor pattern 9 and the dummy gate line 111 overlapping each other are transmitted. Saved between. In addition, the static electricity generated from the data line 200 passes through the first or second semiconductor patterns 707 and 708 and is transmitted to the capacitor pattern 9 or destroys the first and second semiconductor patterns 707 and 708 itself. Exhausts energy.
[0120]
35 is a plan view showing an electrostatic protection circuit pattern connected to the portion A of FIG. 3 according to the fourth embodiment of the present invention, and FIG. 36 is a sectional view taken along line XXXVI-XXXVI 'of FIG.
[0121]
As shown in FIGS. 35 and 36, a fifth electrode 109 is formed below the first and second semiconductor patterns 707 and 708, respectively, and the first and second semiconductor patterns 707 and 708, the fifth electrode 109, Another capacitor is formed between the two. Other structures are the same as those of the third embodiment.
[0122]
FIG. 37 is a plan view showing the electrostatic protection circuit pattern connected to the portion A of FIG. 3 according to the fifth embodiment of the present invention. The dummy gate line does not intersect the data line and is centered on the data line. It consists of a number of divided patterns.
[0123]
As shown in FIG. 37, each pattern of the dummy gate line 111 is formed long along the data line 200 between the two data lines 200, and each pattern of the dummy gate line 111 is simultaneously with many capacitor patterns 9. A sufficient capacitance can be obtained by superimposing. In this case, the dummy gate line 111 is in an electrically floating state.
[0124]
Hereinafter, a method for manufacturing a liquid crystal display device that minimizes damage from static electricity generated during the manufacturing process will be described with reference to FIGS.
[0125]
FIG. 38 is a schematic view of a liquid crystal display device, and FIG. 39 is a flowchart showing a method for manufacturing the liquid crystal display device. As shown in FIGS. 38 and 39, in the first step (STEP 1), a large number of wirings 100 are formed on one surface of the transparent insulating substrate 10, and pads that are in contact with the outer driving IC are formed outside the wirings 100. A shot bar 102 is formed which makes it difficult for one 101 and one wiring 100. In this process, the TFT substrate is formed by forming static patterns such as the diode, the spark induction circuit ST, the electrostatic charging circuit FC, and the discharging element described above. In addition, a color filter substrate having a color filter (not shown) and a common electrode (not shown) is manufactured.
[0126]
Next, in the second step (STEP 2), the TFT substrate 10 and the color filter substrate 11 are cut to form individual liquid crystal substrates, and the TFT substrate 10 and the color filter substrate 11 are made to correspond to each other and a liquid crystal material is injected therebetween. . Static electricity generated in the process of cutting the substrates 10 and 11 and the liquid crystal injection process is dispersed by the shot bar 102.
[0127]
Next, in the third step (STEP 3), the injection port of the liquid crystal material is sealed and the shot bar 102 is removed with an edge grinder.
[0128]
Next, in a fourth step (STEP 4), a test signal is applied to each wiring 100 to inspect the liquid crystal substrate for defects. A variety of pixel display inspections can be performed by applying different test signals for each wiring 100 using probes that contact each pad 101 on the substrate. The static electricity generated at this stage is consumed by the spark induction circuit ST, the electrostatic charging circuit FC, and the discharge pattern.
[0129]
After the defect inspection, the polarizing plates 1 and 2 are attached to the outer surface of the liquid crystal substrate having no defect in the next stage (STEP 5), and the drive circuit is connected in the sixth stage (STEP 6). Normally, static electricity is likely to be generated in the process of bonding the polarizing plates 1 and 2, but since the static electricity is effectively consumed by the spark induction circuit ST and the electrostatic protection circuit FC, the static electricity is prevented from flowing into the display active region. can do.
[0130]
Thus, unlike the conventional method of manufacturing a liquid crystal display device, the process of cutting the substrate, injecting the liquid crystal, and sealing the injection port proceeds in a state where the shot bar 102 is present. Can be protected. Further, since the expensive polarizing plates 1 and 2 are attached only to a good liquid crystal substrate that has passed the pixel display inspection, the cost can be reduced.
[0131]
【The invention's effect】
As described above, in the liquid crystal display device according to the present invention, dummy lines are added outside the display area, a large number of electrostatic discharge circuits are connected to the dummy lines, and the structure of the electrostatic dispersion circuit is suitable for discharging static electricity. By forming a simple structure, static electricity can be prevented from flowing into the display region.
[0132]
In addition, an electrostatic dispersion circuit exists after the shot bar is removed, and an expensive polarizing plate is attached after the pixel display inspection, so that damage to the liquid crystal display device due to static electricity can be minimized and manufacturing costs can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view showing a conventional liquid crystal substrate in which static electricity is generated.
FIG. 2 is an enlarged plan view of a TFT portion in FIG.
FIG. 3 is a plan view schematically showing a liquid crystal display substrate according to the present invention.
4 is an enlarged plan view of a portion A of FIG. 3 according to the first embodiment of the present invention.
FIG. 5 is an electrical equivalent circuit diagram showing an electrostatic discharge diode circuit;
FIG. 6 is a plan view showing an enlarged portion A of FIG. 3 according to a second embodiment of the present invention.
7 is an electrical equivalent circuit diagram showing the first spark induction circuit of FIGS. 5 and 6. FIG.
8 is an electrical equivalent circuit diagram showing the second spark induction circuit of FIGS. 5 and 6. FIG.
9 is an electrical equivalent circuit diagram showing the third spark induction circuit of FIGS. 5 and 6. FIG.
10 is an electrical equivalent circuit diagram showing the fourth spark induction circuit of FIGS. 5 and 6. FIG.
11 is an electrical equivalent circuit diagram showing the first electrostatic charging circuit of FIGS. 5 and 6. FIG.
12 is an electrical equivalent circuit diagram showing the second electrostatic charging circuit of FIGS. 5 and 6. FIG.
13 is a plan view showing a pattern constituting the fourth spark induction circuit of FIG. 10. FIG.
14 is a cross-sectional view taken along line XIV-XIV ′ of FIG.
15 is a plan view showing another pattern constituting the fourth spark induction circuit of FIG.
16 is a cross-sectional view taken along line XVI-XVI ′ of FIG.
FIG. 17 is a plan view showing a first electrostatic discharge dummy pixel according to the present invention;
18 is a cross-sectional view taken along line XVIII-XVIII ′ of FIG.
FIG. 19 is a plan view showing a second electrostatic discharge dummy pixel according to the present invention;
FIG. 20 is a plan view showing a first electrostatic discharge pattern according to the present invention.
21 is a cross-sectional view taken along line XXI-XXI ′ of FIG.
FIG. 22 is a perspective view showing a livestock device formed at an end portion of a first electrostatic discharge pattern.
FIG. 23 is a plan view showing a second electrostatic discharge pattern according to the present invention.
FIG. 24 is a plan view showing a third pattern for electrostatic discharge according to the present invention.
FIG. 25 is a plan view showing a fourth pattern for electrostatic discharge according to the present invention.
FIG. 26 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
FIG. 27 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
FIG. 28 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
FIG. 29 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
FIG. 30 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
FIG. 31 is a cross-sectional view showing a method of forming first to third electrostatic discharge patterns in the order of steps.
32 is an electrical equivalent circuit diagram showing an electrostatic protection circuit pattern connected to part A of FIG. 3 according to the third embodiment of the present invention.
33 is a plan view showing the electrostatic protection circuit pattern of FIG. 32. FIG.
34 is a cross-sectional view taken along the line XXXIV-XXXIV ′ of FIG. 33. FIG.
35 is a plan view showing an electrostatic protection circuit pattern connected to part A of FIG. 3 according to a fourth embodiment of the present invention.
36 is a sectional view taken along line XXXVI-XXXVI ′ of FIG. 35. FIG.
FIG. 37 is a plan view showing an electrostatic protection circuit pattern connected to part A of FIG. 3 according to a fifth embodiment of the present invention.
FIG. 38 is a perspective view of a liquid crystal display device in a state where a thin film transistor substrate and a color filter substrate are assembled.
FIG. 39 is a flowchart of a method for manufacturing a liquid crystal display device.
[Explanation of symbols]
3 Gate insulation film
4 Protective film
10 Substrate
41 Active region
110, 112 Dummy data line
111 dummy gate line
120 diode
130 Spark induction circuit
140, 150 electrostatic charging circuit
118, 128, 119, 129 First to fourth electrode patterns
C8, C9 contact port
302 ITO pattern
704, 705 first and second amorphous silicon patterns

Claims (13)

A transparent insulating first substrate having a large number of pixel electrodes for displaying an image and a semiconductor element;
A gate line formed on the first substrate and connected to the semiconductor element and intersecting the data line;
A plurality of thin film transistors connected in series between two adjacent gate lines or between the data lines, each gate electrode being connected to each other, and one terminal connected to the gate electrode, the two adjacent gate lines Alternatively, a substrate for a liquid crystal display device including a plurality of capacitors each having other terminals connected to the data line, and a plurality of spark induction circuits for consuming static electricity generated from the first substrate. The spark induction circuit includes:
The substrate for a liquid crystal display device according to claim 1, wherein the substrate is formed outside a seal line for stitching the second substrate facing the first substrate and the first substrate.   A transparent insulating first substrate having a large number of pixel electrodes for displaying an image and a semiconductor element;
  A gate line formed on the first substrate and connected to the semiconductor element and intersecting a data line;
  A plurality of thin film transistors connected in parallel to each gate line or each data line, each gate electrode being connected to each source electrode, and a common electrode facing the gate electrode and the pixel electrode of the thin film transistor And a spark induction circuit having a plurality of capacitors respectively provided between them.   A transparent insulating first substrate having a large number of pixel electrodes for displaying an image and a semiconductor element;
  A gate line formed on the first substrate and connected to the semiconductor element and intersecting a data line;
  A plurality of thin film transistors connected in parallel to each gate line or each data line, all gate electrodes and all source electrodes connected together, and facing the gate electrodes and the pixel electrodes A substrate for a liquid crystal display device including a spark induction circuit having a plurality of capacitors provided between the common electrode.   5. The first electrostatic charging circuit according to claim 1, further comprising a first electrostatic charging circuit that is connected between the two adjacent gate lines or between the data lines and that stores and extinguishes static electricity generated from the gate lines or the data lines. The substrate for liquid crystal display devices as described.   The substrate for a liquid crystal display device according to claim 5, wherein the first electrostatic charging circuit is formed of two capacitors connected in series.   The liquid crystal display substrate according to claim 6, wherein two or more first electrostatic charging circuits are connected in parallel between the two adjacent gate lines or between the data lines.   The liquid crystal display substrate according to claim 6, wherein the first electrostatic charging circuit is formed outside a seal for bonding the second substrate facing the first substrate and the first substrate.   The spark induction circuit includes:
  The substrate for a liquid crystal display device according to claim 1, wherein the substrate is formed inside a seal for joining the second substrate facing the first substrate and the first substrate.   The first electrostatic charging circuit includes:
  The substrate for a liquid crystal display device according to claim 5, wherein the substrate is formed of a capacitor including the gate line or the data line and a counter electrode facing the gate line or the data line.   6. The second electrostatic charging circuit according to claim 5, wherein the counter electrode facing the gate line is formed of a source and drain metal of the thin film transistor, and the counter electrode facing the data line is formed of a gate metal. The substrate for liquid crystal display devices as described.   The second electrostatic charging circuit includes:
  The substrate for a liquid crystal display device according to claim 11, wherein the substrate is formed inside the seal line for stitching the second substrate facing the first substrate and the first substrate.   The substrate for a liquid crystal display device according to claim 1, further comprising a shot bar formed by connecting all of the gate lines or the data lines and formed inside a cutting line of the substrate.

Images