JPH05232511A - Manufacture of active matrix type liquid crystal display device - Google Patents

Manufacture of active matrix type liquid crystal display device

Info

Publication number
JPH05232511A
JPH05232511A JP3752092A JP3752092A JPH05232511A JP H05232511 A JPH05232511 A JP H05232511A JP 3752092 A JP3752092 A JP 3752092A JP 3752092 A JP3752092 A JP 3752092A JP H05232511 A JPH05232511 A JP H05232511A
Authority
JP
Japan
Prior art keywords
short
glass substrate
liquid crystal
substrate
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3752092A
Other languages
Japanese (ja)
Inventor
Makoto Sato
良 佐藤
Masaaki Ozaki
正明 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP3752092A priority Critical patent/JPH05232511A/en
Publication of JPH05232511A publication Critical patent/JPH05232511A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To provide the manufacture of the active matrix type liquid crystal display device which excellently protects its internal TFTs against static electricity and effective prevents their dielectric breakdown and characteristic deterioration. CONSTITUTION:A short-circuit line 9 which short-circuits scanning wirings 2 and signal wirings 4 is arranged on the edge part of one glass substrate 1. Liquid crystal is charged between an array substrate 10 and an opposite substrate and then the peripheral edge part of the glass substrate is cut into a specific product shape so that the short circuit line 9 is left. Then driving ICs 11 are mounted on the edge parts of the glass substrate 1 and after the scanning wirings 2 and signal wirings 4 are connected to the driving ICs 11, the connection places of the short-circuit line 9, and the scanning wirings 2 and signal wirings 4 are disconnected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄膜トランジスタ(以
下TFTと略称する)を各画素毎に設置してスイッチン
グ動作させ、画像を表示するアクティブマトリックス型
液晶表示装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix type liquid crystal display device in which a thin film transistor (hereinafter abbreviated as TFT) is provided for each pixel and a switching operation is performed to display an image.

【0002】[0002]

【従来の技術】この種のアクティブマトリックス型液晶
表示装置は、基本的には、一方のガラス基板上に走査配
線と信号配線がマトリックス状に配設され、それらの交
差位置にTFT及び画素電極を設けてアレイ基板が形成
され、他方のガラス基板上に共通電極を形成した対向基
板が形成され、アレイ基板と対向基板の上面に配向膜を
形成し、間隙をおいて平行に貼り合わせたアレイ基板と
対向基板間に液晶を封入して形成される。
2. Description of the Related Art In this type of active matrix type liquid crystal display device, basically, scanning wirings and signal wirings are arranged in a matrix on one glass substrate, and TFTs and pixel electrodes are arranged at the intersections thereof. The array substrate is provided to form the array substrate, the counter substrate having the common electrode is formed on the other glass substrate, the alignment film is formed on the upper surfaces of the array substrate and the counter substrate, and the array substrate is bonded in parallel with a gap. It is formed by enclosing a liquid crystal between the counter substrate and the counter substrate.

【0003】このような液晶表示装置の製造工程では、
一般に、製造室内の空気流、作業者の衣服の摩擦、或は
配向膜のラビング処理などによって、多くの静電気が発
生する。液晶表示装置に内蔵されるTFTはこの種の静
電気に対し非常に弱く、特に多量の静電気が発生しその
電荷が走査配線や信号配線に印加された場合、各走査配
線や信号配線間等で高電圧が発生し、そこに接続された
TFT内部で絶縁破壊が発生し、TFTの特性が部分的
に或は全面的に劣化する問題が生じる。
In the manufacturing process of such a liquid crystal display device,
Generally, a large amount of static electricity is generated due to air flow in the manufacturing chamber, friction of workers' clothes, or rubbing treatment of the alignment film. The TFT incorporated in the liquid crystal display device is extremely weak against this kind of static electricity, and especially when a large amount of static electricity is generated and the electric charge is applied to the scanning wiring or the signal wiring, it is high between the scanning wiring and the signal wiring. A voltage is generated, a dielectric breakdown occurs inside the TFT connected thereto, and there arises a problem that the characteristics of the TFT are partially or entirely deteriorated.

【0004】そこで、従来では、アレイ基板の製造時
に、基板の周縁部上に短絡線を配設し、その短絡線に全
ての走査配線と信号配線を接続し、配向膜のラビング処
理時などに発生する静電気を短絡線を通して流し、TF
Tを保護するようにしていた。
Therefore, conventionally, at the time of manufacturing the array substrate, a short-circuit line is arranged on the peripheral portion of the substrate, and all the scanning wirings and the signal wirings are connected to the short-circuit line, and when the alignment film is rubbed. Pass the generated static electricity through the short-circuit line, and
I was trying to protect T.

【0005】しかし、このようなアレイ基板の製造時
に、走査配線と信号配線を短絡線に接続した状態では、
製造工程中におけるTFTなどの断線ショート検査、プ
ローブ検査等が行なえないため、ラビング処理の後、或
はアレイ基板と対向基板を貼り合せて液晶を封入して液
晶パネルを形成した後、各走査配線と信号配線を短絡線
から切り離していた。
However, at the time of manufacturing such an array substrate, when the scanning wiring and the signal wiring are connected to the short-circuit line,
Since it is not possible to perform a short circuit inspection such as TFT inspection and a probe inspection during the manufacturing process, after each rubbing process, or after bonding the array substrate and the counter substrate to enclose the liquid crystal and form the liquid crystal panel, each scanning wiring And the signal wiring was separated from the short circuit line.

【0006】このため、各走査配線と信号配線を短絡線
から切り離した後、駆動用ICを各走査配線と信号配線
に接続するまでの間、TFTは静電気から保護されない
状態となり、この間の製造工程中における製品の運搬時
や人体との接触により、静電気が発生した場合、上記の
ようなTFTの絶縁破壊や特性劣化が発生する問題があ
った。
Therefore, the TFT is not protected from static electricity until the driving IC is connected to the scanning wiring and the signal wiring after the scanning wiring and the signal wiring are separated from the short-circuit line, and the manufacturing process during this period. When static electricity is generated due to transportation of the product inside or contact with a human body, there is a problem in that the above-mentioned dielectric breakdown and characteristic deterioration of the TFT occur.

【0007】[0007]

【発明が解決しようとする課題】そこで、製造時におけ
る液晶パネル内のTFTの特性劣化や絶縁破壊を防止す
るために、従来では、アレイ基板の全面を絶縁膜により
被覆してTFTを保護する技術(特開昭64−3223
4号公報)、アレイ基板の周縁部に模擬電極を配設し、
その模擬電極に静電気の電荷を集めるようにして、内側
のTFTを保護する技術(特開昭64−59320号公
報、特開昭64−59321号公報)など各種の静電気
対策が提案されている。
Therefore, in order to prevent characteristic deterioration and dielectric breakdown of TFTs in a liquid crystal panel during manufacturing, conventionally, a technique of protecting the TFTs by covering the entire surface of the array substrate with an insulating film. (JP-A 64-3223
No. 4), arranging simulated electrodes on the periphery of the array substrate,
Various static electricity countermeasures have been proposed, such as a technique of protecting the inner TFT by collecting static electric charges in the simulated electrode (Japanese Patent Laid-Open Nos. 64-59320 and 64-59321).

【0008】しかし、これら何れの技術においても、T
FTの静電気からの保護において、充分な効果をあげる
ことができず、依然として製品の歩溜りを低下させる原
因となっていた。
However, in any of these techniques, T
In the protection of the FT from static electricity, it was not possible to exert a sufficient effect, and it was still a cause of lowering the yield of products.

【0009】本発明は、上記の課題を解決するためにな
されたもので、内蔵されたTFTを静電気から良好に保
護し、その絶縁破壊や特性劣化を効果的に防止し得るア
クティブマトリックス型液晶表示装置の製造方法を提供
することを目的とする。
The present invention has been made to solve the above problems, and an active matrix type liquid crystal display capable of effectively protecting a built-in TFT from static electricity and effectively preventing its dielectric breakdown and characteristic deterioration. An object is to provide a method for manufacturing a device.

【0010】[0010]

【課題を解決するための手段】このために、第一発明の
製造方法は、一方のガラス基板上に走査配線と信号配線
がマトリックス状に配設され、各配線の交差位置に薄膜
トランジスタを接続してアレイ基板が形成され、他方の
ガラス基板上に共通電極を形成した対向基板が形成さ
れ、アレイ基板と対向基板の上面に配向膜を形成し、間
隙をおいて平行に貼り合わせたアレイ基板と対向基板間
に液晶を封入してなるアクティブマトリックス型液晶表
示装置の製造方法において、一方のガラス基板の縁部上
に走査配線と信号配線とを短絡させる短絡線が配設さ
れ、アレイ基板と対向基板間に液晶を封入した後、ガラ
ス基板の周縁部を所定の製品形状に短絡線を残した状態
で切断し、ガラス基板の縁部上に駆動用集積回路を実装
し、走査配線及び信号配線を駆動用集積回路に接続した
後、短絡線と走査配線及び信号配線との接続箇所を切り
離すように構成される。
To this end, in the manufacturing method of the first invention, scanning lines and signal lines are arranged in a matrix on one glass substrate, and thin film transistors are connected at the intersections of the respective lines. To form an array substrate, a counter electrode having a common electrode formed on the other glass substrate, an alignment film formed on the upper surfaces of the array substrate and the counter substrate, and an array substrate bonded in parallel with a gap. In a method of manufacturing an active matrix liquid crystal display device in which liquid crystal is sealed between opposed substrates, a short-circuit line for short-circuiting a scanning wiring and a signal wiring is arranged on an edge portion of one glass substrate, and the short circuit line is opposed to the array substrate. After the liquid crystal is sealed between the substrates, the peripheral edge of the glass substrate is cut with a short-circuit wire left in a predetermined product shape, the driving integrated circuit is mounted on the edge of the glass substrate, the scanning wiring and the signal are connected. After connecting the line to the driving integrated circuit, configured to decouple the connecting portion between the scanning lines and the signal lines and the short-circuit line.

【0011】第二発明の製造方法は、一方のガラス基板
上に走査配線と信号配線がマトリックス状に配設され、
各配線の交差位置に薄膜トランジスタを接続してアレイ
基板が形成され、他方のガラス基板上に共通電極を形成
した対向基板が形成され、アレイ基板と対向基板の上面
に配向膜を形成し、間隙をおいて平行に貼り合わせた該
アレイ基板と対向基板間に液晶を封入してなるアクティ
ブマトリックス型液晶表示装置の製造方法において、一
方のガラス基板の縁部上に各走査配線と各信号配線に対
応して多数の保護用薄膜トランジスタを配設し、保護用
薄膜トランジスタの各ドレイン電極を短絡させるドレイ
ン短絡線をガラス基板の縁部に沿って配設し、保護用薄
膜トランジスタの各ゲート電極を短絡させるゲート短絡
線をガラス基板の縁部に沿って配設し、その後の製造工
程中、ドレイン短絡線を接地し、ゲート短絡線に一定電
圧を印加して保護用薄膜トランジスタを導通状態とする
ように構成される。
According to the manufacturing method of the second invention, the scanning wirings and the signal wirings are arranged in a matrix on one glass substrate,
An array substrate is formed by connecting thin film transistors at the intersections of the respective wirings, a counter substrate having a common electrode is formed on the other glass substrate, and an alignment film is formed on the upper surfaces of the array substrate and the counter substrate to form a gap. In the manufacturing method of the active matrix type liquid crystal display device in which liquid crystal is sealed between the array substrate and the counter substrate which are bonded in parallel in parallel, each scanning wiring and each signal wiring are supported on the edge of one glass substrate. A large number of protective thin film transistors are provided, and a drain shorting line that short-circuits each drain electrode of the protective thin film transistor is provided along the edge of the glass substrate, and a gate short circuit that short-circuits each gate electrode of the protective thin film transistor. Lines are arranged along the edge of the glass substrate, and during the subsequent manufacturing process, the drain short-circuit line is grounded and a constant voltage is applied to the gate short-circuit line to protect it. Configured to a thin film transistor conductive.

【0012】[0012]

【作用・効果】第一発明の製造方法では、アクティブマ
トリックス型液晶表示装置の製造時、ラビング処理や液
晶封入などの工程中、及びその後、ガラス基板の周縁部
を製品形状に切断する工程などを含む各走査配線と各信
号配線が駆動用ICに接続されるまで、各走査配線と各
信号配線は短絡線により短絡される。このため、そこに
接続された各TFTのソース電極及びゲート電極は短絡
されて同電位となり、静電気による電荷が各走査配線や
信号配線に注入された場合でも、TFTのソース電極と
ゲート電極間に高電圧がかかることはなく、静電気によ
って破壊されやすいソース・ゲート間の絶縁層は確実に
保護される。
According to the manufacturing method of the first invention, during the manufacturing of the active matrix type liquid crystal display device, during the steps of rubbing treatment and liquid crystal encapsulation, and thereafter, the step of cutting the peripheral portion of the glass substrate into the product shape is performed. The respective scanning wirings and the respective signal wirings are short-circuited by the short-circuiting line until the respective scanning wirings and the respective signal wirings included therein are connected to the driving IC. Therefore, the source electrode and the gate electrode of each TFT connected thereto are short-circuited to have the same potential, and even when the charge due to static electricity is injected into each scanning wiring or signal wiring, it is between the source electrode and the gate electrode of the TFT. High voltage is not applied, and the insulating layer between the source and the gate, which is easily damaged by static electricity, is securely protected.

【0013】また、ガラス基板の縁部上に駆動用ICを
実装して走査配線及び信号配線に接続した後、短絡線と
走査配線及び信号配線との接続箇所を切り離すため、従
来のように、短絡線と走査配線及び信号配線が切り離さ
れることによって、走査配線と信号配線が開放された状
態となることがなく、つまり短絡線の切り離し後、駆動
用ICが走査配線と信号配線に接続されるまでの配線が
開放されている期間がなくなり、製造工程全体にわたっ
て、TFTを静電気から効果的に保護することができ
る。
Further, after the driving IC is mounted on the edge of the glass substrate and connected to the scanning wiring and the signal wiring, the short-circuit line and the scanning wiring and the signal wiring are disconnected from each other. By disconnecting the short-circuit line from the scanning wiring and the signal wiring, the scanning wiring and the signal wiring are not opened, that is, the driving IC is connected to the scanning wiring and the signal wiring after the short-circuit line is separated. There is no longer a period in which the wiring is open, and the TFT can be effectively protected from static electricity throughout the manufacturing process.

【0014】第二発明の製造方法では、アレイ基板の製
造工程中、ガラス基板の縁部上に各走査配線と各信号配
線に対応して多数の保護用薄膜トランジスタを配設し、
保護用薄膜トランジスタの各ドレイン電極を短絡させる
ドレイン短絡線をガラス基板の縁部に沿って配設し、保
護用薄膜トランジスタの各ゲート電極を短絡させるゲー
ト短絡線をガラス基板の縁部に沿って配設する。そし
て、その後のラビング処理や液晶封入などの工程中、ド
レイン短絡線を接地し、ゲート短絡線に一定電圧を印加
して保護用薄膜トランジスタを導通状態とする。
In the manufacturing method of the second invention, during the manufacturing process of the array substrate, a large number of protective thin film transistors are arranged on the edge of the glass substrate corresponding to each scanning wiring and each signal wiring,
A drain short-circuit line that short-circuits each drain electrode of the protective thin film transistor is arranged along the edge of the glass substrate, and a gate short-circuit line that short-circuits each gate electrode of the protective thin film transistor is arranged along the edge of the glass substrate. To do. Then, during the subsequent steps such as rubbing treatment and liquid crystal encapsulation, the drain short-circuit line is grounded and a constant voltage is applied to the gate short-circuit line to bring the protective thin film transistor into a conductive state.

【0015】このため、各走査配線と各信号配線は、製
造工程中、常時、保護用TFTとドレイン短絡線を介し
て接地された状態となり、各TFTのソース電極及びゲ
ート電極が短絡されて同電位となるため、静電気による
電荷が各走査配線や信号配線に注入された場合でも、T
FTのソース電極とゲート電極間に高電圧がかかること
はなく、静電気によって破壊されやすいソース・ゲート
間の絶縁層は確実に保護される。
Therefore, each scanning wiring and each signal wiring are always grounded through the protection TFT and the drain short-circuit line during the manufacturing process, and the source electrode and the gate electrode of each TFT are short-circuited to each other. Because of the potential, even if electric charge due to static electricity is injected into each scanning wiring or signal wiring,
A high voltage is not applied between the source electrode and the gate electrode of the FT, and the insulating layer between the source and the gate, which is easily destroyed by static electricity, is surely protected.

【0016】[0016]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0017】図1〜図3は、上記第一発明の実施例を示
し、図1はアクティブマトリックス型液晶表示装置の製
造時におけるアレイ基板10の概略平面図を示してい
る。
1 to 3 show an embodiment of the first invention, and FIG. 1 shows a schematic plan view of an array substrate 10 at the time of manufacturing an active matrix type liquid crystal display device.

【0018】アレイ基板10を製造する場合、先ず、ガ
ラス基板1上に多数の走査配線2を一定の間隔をおいて
平行に形成すると共に、多数のTFT5を配置する各々
の位置に、そのゲート電極3を各走査配線2に接続して
形成する。この走査配線2及びゲート電極3は、クロム
等の金属を用いて、スパッタリング法及びホトリソグラ
フィー法等により形成される。
When manufacturing the array substrate 10, first, a large number of scanning wirings 2 are formed in parallel on the glass substrate 1 at regular intervals, and the gate electrodes are arranged at respective positions where a large number of TFTs 5 are arranged. 3 is formed by connecting to each scanning wiring 2. The scanning wiring 2 and the gate electrode 3 are formed by using a metal such as chromium by a sputtering method, a photolithography method, or the like.

【0019】また、このとき、ガラス基板の縁部、例え
ば図1の上縁部と左縁部に、L字状の短絡線9がクロム
等の金属を用いて形成され、前記各走査配線2の左端部
がその短絡線9に接続される。
At this time, an L-shaped short-circuit line 9 is formed by using a metal such as chrome at the edge of the glass substrate, for example, the upper edge and the left edge of FIG. The left end of is connected to the short-circuit line 9.

【0020】次に、各TFT5のゲート電極3上にゲー
ト絶縁膜を形成し、ゲート絶縁膜の上に活性層とドーピ
ング層を島状に形成する。
Next, a gate insulating film is formed on the gate electrode 3 of each TFT 5, and an active layer and a doping layer are formed in an island shape on the gate insulating film.

【0021】次に、ゲート絶縁膜の上に、ITO等の金
属を用いて画素電極6を、スパッタリング法及びホトリ
ソグラフィー法により形成する。そして、モリブデン、
アルミニウム等の金属を用いて、多数の信号配線4を前
記走査配線2と直交する方向に一定間隔をおいて平行に
形成し、さらに、同様の金属及び同方法を用いて、各T
FT5のソース電極7を各信号配線4に接続して形成
し、且つドレイン電極8を画素電極6に接続して形成す
る。これらの信号配線4は、図1に示すように、その上
端が上縁位置に配設された前記短絡線9に接続される。
Next, the pixel electrode 6 is formed on the gate insulating film by using a metal such as ITO by a sputtering method and a photolithography method. And molybdenum,
A large number of signal wirings 4 are formed in parallel in the direction orthogonal to the scanning wirings 2 at a constant interval by using a metal such as aluminum, and each T is formed by using the same metal and the same method.
The source electrode 7 of the FT 5 is formed by connecting it to each signal wiring 4, and the drain electrode 8 is formed by connecting it to the pixel electrode 6. As shown in FIG. 1, the upper ends of these signal wirings 4 are connected to the short-circuit lines 9 arranged at the upper edge positions.

【0022】このようにして、ガラス基板1上に走査配
線2と信号配線4がマトリックス状に形成され、それら
の交差位置にTFT5が配置されてアレイ基板10が製
造される。
In this way, the scanning wirings 2 and the signal wirings 4 are formed in a matrix on the glass substrate 1, and the TFTs 5 are arranged at the intersections of these to manufacture the array substrate 10.

【0023】一方、アレイ基板10と対向して配設され
る対向基板(図示せず)は、別のガラス基板上に、IT
O等からなる共通電極を形成して製造される。
On the other hand, the counter substrate (not shown) arranged so as to face the array substrate 10 is provided on another glass substrate, IT.
It is manufactured by forming a common electrode made of O or the like.

【0024】そして、アレイ基板10と対向基板の表面
(内側)にポリイミド等からなる配向膜を形成し、焼成
した後、配向膜の表面にはラビング処理が施される。こ
のラビングを行う際、空気やパイル等の摩擦により非常
に多くの静電気が発生する。しかし、アレイ基板10に
おける各走査配線2と各信号配線4は、短絡線9によっ
て短絡されているため、そこに接続された各TFT5の
ソース電極7及びゲート電極3は短絡されて同電位とな
り、静電気による電荷が各走査配線2や信号配線4に注
入された場合でも、ソース電極7とゲート電極3間に高
電圧がかかることはなく、静電気によって破壊されやす
いソース・ゲート間の絶縁層は確実に保護される。
Then, after an alignment film made of polyimide or the like is formed on the surfaces (inside) of the array substrate 10 and the counter substrate and baked, the surface of the alignment film is rubbed. When this rubbing is performed, a large amount of static electricity is generated due to friction of air, piles and the like. However, since the scanning lines 2 and the signal lines 4 on the array substrate 10 are short-circuited by the short-circuit line 9, the source electrode 7 and the gate electrode 3 of each TFT 5 connected thereto are short-circuited to have the same potential, Even if the charge due to static electricity is injected into each scanning wiring 2 or signal wiring 4, a high voltage is not applied between the source electrode 7 and the gate electrode 3, and the insulating layer between the source and the gate, which is easily destroyed by static electricity, is reliable. Protected by.

【0025】次に、アレイ基板10と対向基板を平行
に、その配向膜を対向させて一定の間隔をおいて重ね合
せ、周囲をシール材(接着剤)で注入口となる部分を残
してシールし、焼成した後、その注入口から基板の内部
に液晶を注入し、そして、注入口を封止する。
Next, the array substrate 10 and the counter substrate are parallel to each other, and the alignment films thereof are opposed to each other and are superposed at a constant interval, and the periphery is sealed with a sealing material (adhesive) leaving a portion serving as an injection port. Then, after firing, liquid crystal is injected into the substrate through the injection port, and the injection port is sealed.

【0026】その後、アレイ基板10及び対向基板のガ
ラス基板の周縁部が、製品形状となるように所定寸法だ
け切断されるが、このとき、図2のように、短絡線9は
ガラス基板1上に残して縁部が切断される。したがっ
て、各走査配線2と信号配線4が短絡線9によって短絡
された状態は、その後も継続され、製造工程中における
作業者との接触や運搬動作等によって静電気が帯電した
場合にも、TFT5のソース電極7及びゲート電極3は
短絡されて、同電位となり、上記と同様にTFT5を保
護することができる。
After that, the peripheral portions of the array substrate 10 and the glass substrate of the counter substrate are cut by a predetermined dimension so as to have a product shape. At this time, as shown in FIG. The edges are cut off. Therefore, the state in which each scan line 2 and the signal line 4 are short-circuited by the short-circuit line 9 continues after that, and even when static electricity is charged due to contact with a worker or a transportation operation during the manufacturing process, the TFT 5 is The source electrode 7 and the gate electrode 3 are short-circuited to have the same potential, and the TFT 5 can be protected as described above.

【0027】なお、上記では、各走査配線2と各信号配
線4を、1本の短絡線9によって短絡接続しているが、
各走査配線2に接続した短絡線(図の垂直部分)と各信
号配線4に接続した短絡線(水平部分)を切り離し、そ
の間に高抵抗を接続すれば、TFT5を静電気から保護
しながら、その短絡線を利用してTFT5の性能を検査
することができる。
In the above description, each scan line 2 and each signal line 4 are short-circuited and connected by one short-circuit line 9.
If the short-circuit line (vertical part in the figure) connected to each scanning line 2 and the short-circuit line (horizontal part) connected to each signal line 4 are separated and a high resistance is connected between them, the TFT 5 is protected from static electricity and The performance of the TFT 5 can be inspected by using the short circuit line.

【0028】この液晶表示装置は、駆動用ICがガラス
基板1上に直接実装される所謂COG型であり、図2に
示すように、ガラス基板1の右縁部と下縁部にその駆動
用ICを実装するためのスペースが形成されている。
This liquid crystal display device is a so-called COG type in which a driving IC is directly mounted on the glass substrate 1, and as shown in FIG. 2, the driving IC is mounted on the right edge portion and the lower edge portion of the glass substrate 1. A space for mounting the IC is formed.

【0029】そこで、駆動用IC11は、図3に示すよ
うに、ガラス基板1の右縁部と下縁部のスペースに、そ
の各端子を走査配線2及び信号配線4の延長部分に接続
するように、実装される。また、短絡線9は駆動用IC
11のGND端子に接続される。
Therefore, as shown in FIG. 3, the driving IC 11 connects its terminals to the extended portions of the scanning wiring 2 and the signal wiring 4 in the spaces at the right and lower edges of the glass substrate 1. Will be implemented. Further, the short-circuit line 9 is a driving IC
11 GND terminal.

【0030】そして、駆動用IC11を実装した後、図
3に示すように、各走査配線2、各信号配線4と短絡線
9との接続部分がレーザカッター等により切り離され
る。
After the driving IC 11 is mounted, as shown in FIG. 3, the connecting portions of the scanning wirings 2, the signal wirings 4 and the short-circuit wires 9 are separated by a laser cutter or the like.

【0031】このように、ガラス基板1の縁部上に駆動
用IC11を実装して走査配線2及び信号配線4に接続
した後、短絡線9と走査配線2及び信号配線4との接続
箇所を切り離すため、従来のように、ガラス基板の縁部
の切断と共に短絡線が切除される等によって、走査配線
と信号配線が開放された状態となることがなく、製造工
程全体にわたって、TFT5を静電気から効果的に保護
することができる。
As described above, after the driving IC 11 is mounted on the edge of the glass substrate 1 and connected to the scanning wiring 2 and the signal wiring 4, the short-circuit line 9 and the connecting portion of the scanning wiring 2 and the signal wiring 4 are connected. Because of the disconnection, unlike the conventional case, the scanning line and the signal line are not opened due to the cutting of the short-circuit line along with the cutting of the edge of the glass substrate, and the TFT 5 is protected from static electricity throughout the manufacturing process. Can be effectively protected.

【0032】また、短絡線9は駆動用IC11のGND
端子に接続された状態で製品となるため、液晶表示装置
の縁部にアース接続された導線が配設され、製品の静電
気保護に役立てることができる。
The short-circuit line 9 is the GND of the driving IC 11
Since the product becomes a product connected to the terminals, a conductor wire connected to the ground is provided at the edge of the liquid crystal display device, which can be useful for protecting the product from static electricity.

【0033】図4は上記第二発明の実施例であり、製造
時におけるアレイ基板20の概略平面図を示している。
FIG. 4 is a schematic plan view of the array substrate 20 during manufacturing, which is an embodiment of the second invention.

【0034】このアレイ基板20を製造する場合、先
ず、ガラス基板21上に多数の走査配線22を一定の間
隔をおいて形成すると共に、多数のTFT25を配置す
る各々の位置に、そのゲート電極23を各走査配線22
に接続して形成する。この走査配線22及びゲート電極
23は、クロム等の金属を用いて、スパッタリング法及
びホトリソグラフィー法等により形成される。
In the case of manufacturing this array substrate 20, first, a large number of scanning wirings 22 are formed on the glass substrate 21 at regular intervals, and a gate electrode 23 is formed at each position where a large number of TFTs 25 are arranged. Each scan wiring 22
Connect to and form. The scanning wiring 22 and the gate electrode 23 are formed by using a metal such as chromium by a sputtering method, a photolithography method, or the like.

【0035】同時に、ガラス基板21の縁部、例えば図
4の上縁部と右縁部に、ゲート短絡線29をクロム等の
金属で形成し、後述の保護用TFT30のゲート電極3
3をそのゲート短絡線29に接続して形成する。これら
の保護用TFT30は、ガラス基板20の上縁部と右縁
部に沿って、各走査配線22及び後述の信号配線24に
対応して配設される。
At the same time, a gate short-circuit line 29 is formed of a metal such as chromium at the edge of the glass substrate 21, for example, the upper edge and the right edge of FIG. 4, and the gate electrode 3 of the protective TFT 30 described later is formed.
3 is connected to its gate short-circuit line 29 to form. These protective TFTs 30 are arranged along the upper edge portion and the right edge portion of the glass substrate 20 so as to correspond to each scanning wiring 22 and a signal wiring 24 described later.

【0036】次に、各TFT25のゲート電極23及び
各保護用TFT30のゲート電極33上に、ゲート絶縁
膜を形成し、ゲート絶縁膜の上に活性層とドーピング層
を島状に形成する。
Next, a gate insulating film is formed on the gate electrode 23 of each TFT 25 and the gate electrode 33 of each protective TFT 30, and an active layer and a doping layer are formed in an island shape on the gate insulating film.

【0037】次に、ゲート絶縁膜の上に、ITO等の金
属を用いて画素電極26を、スパッタリング法及びホト
リソグラフィー法により形成し、同時に、ガラス基板1
の上縁部と右縁部に沿って、ドレイン短絡線39を同金
属、同方法により形成する。
Next, the pixel electrode 26 is formed on the gate insulating film by using a metal such as ITO by the sputtering method and the photolithography method, and at the same time, the glass substrate 1 is formed.
The drain short-circuit line 39 is formed by the same metal and the same method along the upper edge portion and the right edge portion.

【0038】次に、モリブデン、アルミニウム等の金属
を用いて、多数の信号配線24を前記走査配線22と直
交する方向に一定間隔をおいて同様な方法で形成する。
Next, using a metal such as molybdenum or aluminum, a large number of signal wirings 24 are formed in the same manner at regular intervals in the direction orthogonal to the scanning wirings 22.

【0039】そして、同様の金属、同様な方法により、
各TFT25のソース電極27を各信号配線24に接続
して形成し、且つドレイン電極28を画素電極26に接
続して形成し、同時に、各保護用TFT30のドレイン
電極38をドレイン短絡線39に接続して形成し、さら
に各保護用TFT30のソース電極37を各信号配線2
4に接続して形成する。
Then, using the same metal and the same method,
The source electrode 27 of each TFT 25 is connected to each signal line 24, and the drain electrode 28 is connected to the pixel electrode 26. At the same time, the drain electrode 38 of each protection TFT 30 is connected to the drain short-circuit line 39. Then, the source electrode 37 of each protection TFT 30 is connected to each signal wiring 2
4 is connected and formed.

【0040】なお、保護用TFT30はTFT25の形
成と同時にガラス基板21上に形成されるため、図4の
右縁部に配置される保護用TFT30は、上縁部に配置
される保護用TFT30を逆スタガード型とした場合、
ゲート側とソース・ドレイン側をその逆に形成したスタ
ガード型とすればよい。
Since the protective TFT 30 is formed on the glass substrate 21 simultaneously with the formation of the TFT 25, the protective TFT 30 arranged at the right edge portion of FIG. When using the inverted staggered type,
A staggered type may be used in which the gate side and the source / drain sides are formed in reverse.

【0041】このようにして、ガラス基板21上に走査
配線22と信号配線24がマトリックス状に形成され、
それらの交差位置にTFT25が配置され、同時に保護
用TFT30が縁部に配設されてアレイ基板20が製造
される。
In this way, the scanning wirings 22 and the signal wirings 24 are formed in a matrix on the glass substrate 21,
The TFTs 25 are arranged at their intersecting positions, and at the same time, the protective TFTs 30 are arranged at the edges to manufacture the array substrate 20.

【0042】アレイ基板20が上記のように製造される
と、図4に示すように、ドレイン短絡線39は接地さ
れ、ゲート短絡線29には電池等を用いた直流定電源回
路から一定電圧が印加され、これにより、各保護用TF
T30のゲート電極33にオン動作用の電圧が印加さ
れ、各保護用TFT30は導通状態とされる。
When the array substrate 20 is manufactured as described above, as shown in FIG. 4, the drain short-circuit line 39 is grounded, and the gate short-circuit line 29 receives a constant voltage from a DC constant power supply circuit using a battery or the like. Applied, which causes each protective TF
A voltage for ON operation is applied to the gate electrode 33 of T30, and each protection TFT 30 is brought into conduction.

【0043】一方、アレイ基板20と対向して配設され
る対向基板(図示せず)は、別のガラス基板上に、IT
O等からなる共通電極を形成して製造される。
On the other hand, the counter substrate (not shown) arranged so as to face the array substrate 20 is IT on another glass substrate.
It is manufactured by forming a common electrode made of O or the like.

【0044】そして、アレイ基板20と対向基板の表面
(内側)にポリイミド等からなる配向膜を形成し、焼成
した後、配向膜の表面にはラビング処理が施される。こ
のラビングを行う際、空気やパイル等の摩擦により非常
に多くの静電気が発生する。
Then, after an alignment film made of polyimide or the like is formed on the surfaces (inside) of the array substrate 20 and the counter substrate and baked, the surface of the alignment film is rubbed. When this rubbing is performed, a large amount of static electricity is generated due to friction of air, piles and the like.

【0045】しかし、アレイ基板20における各走査配
線22と各信号配線24は、保護用TFT30とドレイ
ン短絡線39を通して接地されているため、そこに接続
された各TFT25のソース電極27及びゲート電極2
3は同電位となり、静電気による電荷が各走査配線22
や信号配線24に注入された場合でも、ソース電極27
とゲート電極23間に高電圧がかかることはなく、静電
気によって破壊されやすいソース・ゲート間の絶縁層は
確実に保護される。
However, since the scanning wirings 22 and the signal wirings 24 on the array substrate 20 are grounded through the protective TFT 30 and the drain short-circuit line 39, the source electrode 27 and the gate electrode 2 of each TFT 25 connected thereto are provided.
3 has the same potential, and the charge due to static electricity is applied to each scanning wiring 22.
And the source electrode 27 even when injected into the signal wiring 24.
A high voltage is not applied between the gate electrode 23 and the gate electrode 23, and the insulating layer between the source and the gate, which is easily destroyed by static electricity, is surely protected.

【0046】その後、アレイ基板20は、図示しない対
向基板と一定の間隔をおいて重ね合せられ、周囲をシー
ル材(接着剤)でシールして、その内部に液晶が封入さ
れ、ガラス基板の縁部を製品形状に切断する等の各種の
工程を経て液晶表示装置が製造されるが、図示しない駆
動用ICが基板上に実装され各走査配線22及び信号配
線24に接続されるまで、保護用TFT30は導通状態
とされる。
After that, the array substrate 20 is superposed on a counter substrate (not shown) at a constant interval, and the periphery thereof is sealed with a sealing material (adhesive), and liquid crystal is sealed inside the array substrate 20. The liquid crystal display device is manufactured through various processes such as cutting the parts into product shapes. However, until the driving IC (not shown) is mounted on the substrate and connected to the scanning wirings 22 and the signal wirings 24, it is used for protection. The TFT 30 is turned on.

【0047】このため、各走査配線22と信号配線24
がドレイン短絡線39によって短絡された状態は、その
後の製造工程でも継続され、製造工程中における作業者
との接触や運搬動作等によって静電気が帯電した場合に
も、TFT25のソース電極27及びゲート電極23は
短絡されて、同電位となり、TFT25を保護すること
ができる。
Therefore, each scanning wiring 22 and signal wiring 24
The state in which is short-circuited by the drain short-circuit line 39 is continued in the subsequent manufacturing process, and even when static electricity is charged due to contact with a worker or a carrying operation during the manufacturing process, the source electrode 27 and the gate electrode of the TFT 25 are 23 is short-circuited to have the same potential, and the TFT 25 can be protected.

【図面の簡単な説明】[Brief description of drawings]

【図1】第一発明の一実施例であって、アクティブマト
リックス型液晶表示装置の製造時におけるアレイ基板1
0の概略平面図である。
FIG. 1 is an embodiment of the first invention and is an array substrate 1 at the time of manufacturing an active matrix type liquid crystal display device.
It is a schematic plan view of 0.

【図2】製品形状に切断された状態の概略平面図であ
る。
FIG. 2 is a schematic plan view in a state of being cut into a product shape.

【図3】駆動用ICを実装した状態の概略平面図であ
る。
FIG. 3 is a schematic plan view showing a state in which a driving IC is mounted.

【図4】第二発明の一実施例であって、アクティブマト
リックス型液晶表示装置の製造時におけるアレイ基板1
0の概略部分平面図である。
FIG. 4 is an embodiment of the second invention, which is an array substrate 1 at the time of manufacturing an active matrix type liquid crystal display device.
It is a schematic partial top view of 0.

【符号の説明】[Explanation of symbols]

1−ガラス基板、2−走査配線、4−信号配線、5−T
FT、9−短絡線、10−アレイ基板、11−駆動用I
C、29−ゲート短絡線、30−保護用TFT、39−
ドレイン短絡線。
1-glass substrate, 2-scan wiring, 4-signal wiring, 5-T
FT, 9-short circuit line, 10-array substrate, 11-driving I
C, 29-gate short-circuit line, 30-protective TFT, 39-
Drain short-circuit wire.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/12 A 8728−4M 29/784 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 27/12 A 8728-4M 29/784

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一方のガラス基板上に走査配線と信号配
線がマトリックス状に配設され、各配線の交差位置に薄
膜トランジスタを接続してアレイ基板が形成され、他方
のガラス基板上に共通電極を形成した対向基板が形成さ
れ、アレイ基板と対向基板の上面に配向膜を形成し、間
隙をおいて平行に貼り合わせた該アレイ基板と該対向基
板間に液晶を封入してなるアクティブマトリックス型液
晶表示装置の製造方法において、 前記一方のガラス基板の縁部上に前記走査配線と前記信
号配線とを短絡させる短絡線が配設され、前記アレイ基
板と対向基板間に液晶を封入した後、前記ガラス基板の
周縁部を所定の製品形状に該短絡線を残した状態で切断
し、該ガラス基板の縁部上に駆動用集積回路を実装し、
前記走査配線及び信号配線を該駆動用集積回路に接続し
た後、該短絡線と走査配線及び該信号配線との接続箇所
を切り離すことを特徴とするアクティブマトリックス型
液晶表示装置の製造方法。
1. A scanning wiring and a signal wiring are arranged in a matrix on one glass substrate, a thin film transistor is connected to the intersection of each wiring to form an array substrate, and a common electrode is formed on the other glass substrate. An active matrix liquid crystal in which the formed counter substrate is formed, an alignment film is formed on the upper surfaces of the array substrate and the counter substrate, and liquid crystal is sealed between the array substrate and the counter substrate bonded in parallel with each other with a gap. In the method for manufacturing a display device, a short-circuit line for short-circuiting the scanning wiring and the signal wiring is arranged on an edge of the one glass substrate, and after enclosing a liquid crystal between the array substrate and a counter substrate, The peripheral portion of the glass substrate is cut into a predetermined product shape with the short-circuit line left, and a driving integrated circuit is mounted on the edge portion of the glass substrate,
A method for manufacturing an active matrix type liquid crystal display device, comprising: connecting the scanning wiring and the signal wiring to the driving integrated circuit, and then disconnecting the connection portion between the short-circuit line and the scanning wiring and the signal wiring.
【請求項2】 一方のガラス基板上に走査配線と信号配
線がマトリックス状に配設され、各配線の交差位置に薄
膜トランジスタを接続してアレイ基板が形成され、他方
のガラス基板上に共通電極を形成した対向基板が形成さ
れ、アレイ基板と対向基板の上面に配向膜を形成し、間
隙をおいて平行に貼り合わせた該アレイ基板と該対向基
板間に液晶を封入してなるアクティブマトリックス型液
晶表示装置の製造方法において、 前記一方のガラス基板の縁部上に各走査配線と各信号配
線に対応して多数の保護用薄膜トランジスタを配設し、
該保護用薄膜トランジスタの各ドレイン電極を短絡させ
るドレイン短絡線を該ガラス基板の縁部に沿って配設
し、該保護用薄膜トランジスタの各ゲート電極を短絡さ
せるゲート短絡線を該ガラス基板の縁部に沿って配設
し、その後の製造工程中、該ドレイン短絡線を接地し、
該ゲート短絡線に一定電圧を印加して該保護用薄膜トラ
ンジスタを導通状態とすることを特徴とするアクティブ
マトリックス型液晶表示装置の製造方法。
2. A scan wiring and a signal wiring are arranged in a matrix on one glass substrate, a thin film transistor is connected at the intersection of each wiring to form an array substrate, and a common electrode is formed on the other glass substrate. An active matrix liquid crystal in which the formed counter substrate is formed, an alignment film is formed on the upper surfaces of the array substrate and the counter substrate, and liquid crystal is sealed between the array substrate and the counter substrate bonded in parallel with each other with a gap. In the method of manufacturing a display device, a large number of protective thin film transistors are arranged on the edge of the one glass substrate in correspondence with each scanning wiring and each signal wiring,
A drain short-circuit line for short-circuiting each drain electrode of the protective thin film transistor is arranged along the edge of the glass substrate, and a gate short-circuit line for short-circuiting each gate electrode of the protective thin film transistor is provided at the edge of the glass substrate. And the drain short-circuit wire is grounded during the subsequent manufacturing process.
A method for manufacturing an active matrix type liquid crystal display device, wherein a constant voltage is applied to the gate short-circuit line to bring the protective thin film transistor into a conductive state.
JP3752092A 1992-02-25 1992-02-25 Manufacture of active matrix type liquid crystal display device Pending JPH05232511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3752092A JPH05232511A (en) 1992-02-25 1992-02-25 Manufacture of active matrix type liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3752092A JPH05232511A (en) 1992-02-25 1992-02-25 Manufacture of active matrix type liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH05232511A true JPH05232511A (en) 1993-09-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP3752092A Pending JPH05232511A (en) 1992-02-25 1992-02-25 Manufacture of active matrix type liquid crystal display device

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Country Link
JP (1) JPH05232511A (en)

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JP2006048006A (en) * 2004-07-30 2006-02-16 Lg Phillips Lcd Co Ltd Liquid crystal display device and manufacturing method thereof
US7046312B2 (en) 1995-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Active matrix liquid crystal display and method of fabricating same
JP2008282029A (en) * 2004-07-26 2008-11-20 Seiko Epson Corp Light-emitting device and electronic equipment
US7538849B2 (en) 1995-02-15 2009-05-26 Semiconductor Energy Laboratory Co., Ltd. Active matrix display and forming method thereof
JP2013225135A (en) * 1997-10-14 2013-10-31 Samsung Display Co Ltd Substrate for liquid crystal display device, and liquid crystal display device and manufacturing method therefor
CN105293935A (en) * 2015-10-31 2016-02-03 深圳市金立通信设备有限公司 Design method for LCD (Liquid Crystal Display) glass typesetting and terminal

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538849B2 (en) 1995-02-15 2009-05-26 Semiconductor Energy Laboratory Co., Ltd. Active matrix display and forming method thereof
US7924392B2 (en) 1995-02-15 2011-04-12 Semiconductor Energy Laboratory Co., Ltd. Active matrix display and forming method thereof
US7046312B2 (en) 1995-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Active matrix liquid crystal display and method of fabricating same
JP2013225135A (en) * 1997-10-14 2013-10-31 Samsung Display Co Ltd Substrate for liquid crystal display device, and liquid crystal display device and manufacturing method therefor
JP2008282029A (en) * 2004-07-26 2008-11-20 Seiko Epson Corp Light-emitting device and electronic equipment
JP2006048006A (en) * 2004-07-30 2006-02-16 Lg Phillips Lcd Co Ltd Liquid crystal display device and manufacturing method thereof
KR101108782B1 (en) * 2004-07-30 2012-02-24 엘지디스플레이 주식회사 Liquid Crystal Display device and the fabrication method thereof
CN105293935A (en) * 2015-10-31 2016-02-03 深圳市金立通信设备有限公司 Design method for LCD (Liquid Crystal Display) glass typesetting and terminal
CN105293935B (en) * 2015-10-31 2019-04-23 深圳市金立通信设备有限公司 The design method and terminal of a kind of pair of liquid crystal display LCD glass typesetting

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