KR100543021B1 - Wiring structure including electrostatic protection element and method for manufacturing same - Google Patents

Abstract

A data line is formed on the substrate, and an amorphous silicon pattern is formed. A portion extending from the data line overlaps one edge of the amorphous silicon pattern to form a first pattern portion, and a second pattern portion overlapping the opposite edge is formed of the same metal as the first pattern portion. At this time, the ends of the first and second pattern portions are formed pointed so that tunneling can easily occur through the amorphous silicon pattern, and the ITO patterns for capacitors storing the electrostatic charges that have moved are formed at the ends of the second pattern portions. At this time, a capacitor is formed between the ITO pattern for the capacitor and the common electrode of the upper plate.

Description

Wiring structure including electrostatic protection element and method for manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a method for manufacturing the same, and more particularly, to a wiring structure and a manufacturing method for preventing defects caused by static electricity.

Static electricity is a phenomenon in which a large amount of charge is instantaneously generated in a local part, which causes a voltage difference with a peripheral part, so that charge is transferred. Liquid crystal displays, which are mostly performed on glass substrates, are susceptible to static electricity because in a glass substrate which is a nonconductor, instantaneous charges are not easily dispersed throughout the substrate. As a result, an insulating film or the like on the substrate is broken to cause a defect in the substrate.

In order to prevent the failure of the substrate by static electricity, a method of forming shorting bars and connecting the metal wires in the substrate to one, using an electrostatic protection circuit using a nonlinear element such as an electrostatic diode, or a spare holding capacitor Is used to make source and drain electrodes or gate lines.

Next, a wiring and a manufacturing method of the liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a wiring diagram of a liquid crystal display device having a shorting bar.

As shown in FIG. 1, a plurality of gate lines 10 are formed in a horizontal direction on the substrate 1, a gate insulating film (not shown) is covered thereon, and a plurality of gate lines 10 are formed on the substrate 1. The data line 20 is formed in the vertical direction. A thin film transistor TFT is formed in the pixel region defined by the gate line 10 and the data line 20 to switch the signal from the data line 20. The gate lines 10 are connected to the gate shorting bar 11 formed outside the gate line 10, and the data line 20 is connected to the data shorting bar 21 formed outside the data line 20. ) Are connected as one, and the gate shorting bar 11 and the data shorting bar 21 are connected to each other.

In the wiring structure of the liquid crystal display device, the static electricity generated during the manufacturing process is dispersed through the gate shorting bar 11 and the data shorting bar 21. The gate and data shorting bars 11 and 21 are cut along the cutting line L after all wiring processes are completed.

However, since the metal wires 10 and 20 are exposed at the edges of the glass substrate after the cutting process, the wires 10 and 20 may be damaged in the process of handling the substrate. To prevent this, a method of thinly applying a non-conductive adhesive such as silicon adhesive to the glass substrate edge after the cutting process of the shorting bars 11 and 21 is used, but an additional process is inserted and the thickness of the adhesive is kept uniform. It is difficult to do so, and there is a problem of inconsistency in mounting the exterior mechanism part.

In addition, it is not possible to prevent damage caused by static electricity occurring after the cutting process.

To solve this problem, an antistatic circuit using a nonlinear element such as a diode is used or a dummy holding capacitor is formed, but it occupies a large area in the substrate and crosstalk due to signal delay, etc. Another problem arises.

An object of the present invention is to implement a wiring structure for effectively dissipating static electricity.

In the wiring structure according to the present invention for solving such a problem, a discharge pattern is formed on the wiring formed on the transparent insulating substrate. The discharge pattern has a semiconductor pattern. When static electricity is generated, tunneling occurs in the semiconductor pattern to form a channel, and the static electricity is discharged through the formed channel.

At this time, it is preferable that a capacitor is formed at the end of the semiconductor pattern to effectively discharge static electricity.

Here, the plurality of discharge patterns may be connected in parallel with respect to one wiring or in parallel with respect to two wirings.

In an embodiment according to the present invention, a data line is formed in a vertical direction on an insulating film on a substrate, and an amorphous silicon pattern for electrostatic discharge is formed outside thereof. Both edges of the amorphous silicon pattern and the first and second electrodes overlap each other, and the first electrode is connected to the wiring.

At this time, the ends of the first and second electrodes are sharply formed so that the static electricity flowing along the data line is easily tunneled through the amorphous silicon pattern.

An ITO pattern for a capacitor is formed at the end of the second electrode to form a capacitor including a common electrode and a liquid crystal material of the upper substrate, thereby storing the tunneled static electricity.

Further, a metal line may be formed so as to overlap the ITO pattern for a capacitor with an insulating film interposed therebetween.

In addition, in the method of manufacturing the wiring, the metal line is formed in the forming of the gate line, the amorphous silicon pattern is formed in the process of forming the amorphous silicon layer and the doped amorphous silicon layer in the pixel region, and the first and second electrodes. Is formed at the same time as the data line.

Such a liquid crystal display wiring and a manufacturing method thereof form a discharge pattern having a semiconductor pattern at one end of the wiring to discharge static electricity through the semiconductor pattern.

Next, the wiring for the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the wiring.

2 is a layout view schematically illustrating the wiring of the liquid crystal display according to the present invention.

As illustrated in FIG. 2, a plurality of gate lines 100 are formed on the transparent insulating substrate 1 in the horizontal direction, and a gate pad 101 is formed at one end of the gate line 100. In addition, a plurality of data lines 400 are formed in the vertical direction, and data pads 401 are formed at the ends of the data lines 400. The gate line 100 and the data line 200 are insulated with a gate insulating film (not shown) therebetween. In the pixel area PX defined by the intersection of the data line 400 and the gate line 100, a thin film transistor TFT, which is a switching element, is formed, and an area in which the pixel area PX is formed is an active image. It becomes an active area (A / A).

Discharge patterns P1, P2, and P3 for effectively discharging static electricity are formed outside the active area A / A. In the discharge patterns P1, P2, and P3, a discharge element D tunneling static electricity is connected to the data line 400, and a capacitor Cst is connected to an end of the discharge element D. Several discharge elements D may be connected in parallel to one data line 400 (in case of P2), or several may be connected in parallel between two data lines 400 (in case of P3). When the static electricity generated on the substrate flows along the data line 400 and flows into the discharge patterns P1, P2, and P3, the discharge device D is turned on and the static electricity is formed at the end of the discharge device D. Stored in a capacitor. Therefore, it is possible to prevent the thin film transistor TFT and the like in the active region A / A from being destroyed. At this time, a common voltage applied to the common electrode of the upper substrate is applied to the other terminal of the capacitor.

The detailed structure of the discharge patterns P1, P2, and P3 will be described later.

Next, the pixel area of the liquid crystal display will be further described with reference to FIGS. 3 to 6.

3 is a layout view illustrating pixels of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV 'of FIG. 3, that is, a thin film transistor. 6 is a cross-sectional view of the VI-VI ′ line, that is, the gate pad part of FIG. 3.

The gate line 100 is formed on the substrate 1 in the horizontal direction, and a portion which is separated from the gate line 100 forms the gate electrode 110, and a gate pad 101 is formed at the end of the gate line 100. It is.

The gate insulating layer 200 is covered on the gate lines such as the gate line 100, the gate electrode 110, and the gate pad 101, and is disposed on the gate insulating layer 200 corresponding to the position of the gate electrode 110. An amorphous silicon layer 310 is formed. In addition, a data line 400 is formed in the vertical direction on the gate insulating layer 200, and a portion split from the data line 400 overlaps a portion of the semiconductor pattern 300 to become a source electrode 410. A drain electrode 420 is formed on the electrode 110 opposite to the source electrode 410. In the contact portion between the source and drain electrodes 410 and 420 and the amorphous silicon layer 310, n ⁺ amorphous silicon layers 321 and 322 are formed to reduce contact resistance. The data pad 401 is formed at the end of the data line 400.

A passivation layer 500 is stacked on top of data lines such as the source and drain electrodes 410 and 420, the data line 400, and the data pad 401. The passivation layer 500 includes a drain electrode 420 and a data pad. Contact holes C1 and C2 exposing 401 are formed. In addition, a portion of the passivation layer 500 and the gate insulating layer 200 on the gate pad 101 may be removed to form the contact hole C3.

The pixel electrode 600 is formed of ITO in the pixel region PX, and the pixel electrode 600 contacts the drain electrode 420 through the contact hole C1. In addition, ITO patterns 601 and 602 are formed on the gate pad 101 and the data pad 401 to compensate for the contact characteristics of the pads 101 and 401. The contact holes C2 and C3 are formed through the contact holes C2 and C3. The data pad 401 and the gate pad 101 are in contact with each other.

When static electricity is generated in the liquid crystal display, the gate insulating layer 200 may be destroyed by static electricity or the edge of the amorphous silicon layer 310 of the thin film transistor may burn out. Therefore, in the present invention, discharge patterns P1, P2, and P3 for discharging static electricity are formed outside the active region.

FIG. 7 is an enlarged layout view of a discharge pattern according to a first embodiment of the present invention, that is, a portion P1 of FIG. A perspective view showing a capacitor formed at the end of a discharge pattern.

The data line 400 is formed on the gate insulating layer 200 on the substrate 1, and the amorphous silicon pattern 350 for discharge is formed. A portion of the portion extending from the data line 400 becomes the first pattern portion 430. The first pattern portion 430 is formed to overlap one edge of the amorphous silicon pattern 350, and the first pattern portion 430 overlaps one edge of the amorphous silicon pattern 350. The two pattern portions 440 overlap. At this time, the ends of the first and second pattern portions 430 and 440 are sharply formed, and n ⁺ amorphous silicon is formed at a portion where the first and second pattern portions 430 and 440 and the amorphous silicon pattern 350 are in contact with each other. Patterns 351 and 352 are formed. The passivation layer 500 is formed on the data line 400 and the first and second pattern portions 430 and 440, and the contact hole C4 exposing the second pattern portion 440 is formed on the passivation layer 500. The capacitor ITO pattern 610 overlapping the second pattern portion 440 is formed on the passivation layer 500. The capacitor ITO pattern 610 is connected to the second pattern portion 440 through the contact hole C4.

That is, the discharge pattern according to the first exemplary embodiment includes an amorphous silicon pattern 350, an ITO pattern 610 for a capacitor for storing discharged static electricity, and the two patterns 350 and 610 are electrically connected to the data line 400. The first and second pattern parts 430 and 440 are connected to each other.

When static electricity flows into the discharge pattern P1, tunneling occurs faster than breakdown of the amorphous silicon pattern 350 so that the electrostatic charge passes through the second pattern part 440 to the capacitor ITO pattern 610. The reason why the tunneling effect is greater than the breakdown is that the ends of the first and second pattern parts 430 and 440 are sharply formed, so that charges are concentrated at the ends.

When a particle encounters a barrier that has a higher energy than itself, it is common to go back without passing it. However, when a particle passes through a barrier, it is called tunneling. This tunneling is due to the wave nature of the particles and can be solved through the Schrodinger equation of quantum mechanics. In the present invention, it means a phenomenon that the charge due to the static electricity crosses the barrier, that is, when the charge is generated by the static electricity, the charge introduced into the discharge pattern (P1) exceeds the amorphous silicon pattern 350, the second pattern portion 440 It is to be moved to the ITO pattern 610 for the capacitor past. This phenomenon occurs because the energy of the charge due to static electricity is large, and also because the pattern portions 430 and 440 symmetrically formed in the inversion pattern P1 are sharp and formed close to each other. As a result, static electricity proceeds only through the pattern portions 430 and 440, and does not damage the amorphous silicon pattern 350 therebetween.

As shown in FIG. 9, the ITO pattern 610 of the discharge pattern corresponds to face the common electrode 700 of the upper substrate, and a liquid crystal material LC is formed between the ITO pattern 610 and the common electrode 700. Since it exists, the holding capacitor Cst is formed in the end part of a discharge pattern. Therefore, the electrostatic charges transferred to the capacitor ITO pattern 610 are stored in the sustain capacitor, and thus do not affect the thin film transistor TFT in the active region A / A.

10 and 11 are enlarged layout views of discharge patterns according to the second and third embodiments of the present invention, that is, parts P2 and P3 of FIG. 2.

The discharge pattern according to the second embodiment has a basic structure based on the discharge pattern of the type mentioned in the first embodiment. However, two or more discharge elements are different from the first embodiment in that they are connected to the capacitor ITO pattern 610 and the data line 400 in parallel.

8 and 10, the first discharge element D1 and the second discharge element D1 including the first amorphous silicon pattern 350 and the first and second pattern portions 430 and 440 on the gate insulating layer 200. The second discharge element D2 including the amorphous silicon pattern 360 and the third and fourth pattern portions 450 and 460 is formed in the row direction with respect to the data line 400. Contact holes C4 and C5 exposing the second and fourth pattern parts 440 and 460 are formed in the passivation layer 500, and the second and fourth pattern parts are used for capacitors through the contact holes C4 and C5. The ITO pattern 610 is in contact.

As described in the first embodiment, the ends of the first to fourth pattern portions 430, 440, 450, and 460 are sharply formed, and the first and third pattern portions 430, 450 are formed in the second portion. And formed in pairs with the fourth pattern parts 440 and 460 so as to face each other on the first and second amorphous silicon patterns 350 and 360, the static electricity flowing along the data line 400 is easily stored through the pointed portion. It is discharged and stored in the existing ITO pattern 610.

If necessary, the number of discharge elements D1 and D2 connected in parallel can be increased.

In the discharge pattern P3 according to the third embodiment, two or more discharge devices are connected in parallel to two adjacent data lines.

As shown in FIGS. 8 and 11, the second and fourth pattern portions 441 and 461 of the first and second discharge devices D1 and D2 of the above-described type are connected to the adjacent data line 400 '. It is connected.

Also in the third embodiment, the number of discharge elements can be increased as necessary.

In the first to third embodiments described above, the capacitor which stores static electricity is formed after the upper and lower substrates for the liquid crystal display are assembled. It is a structure suitable for discharging.

Next, the discharge pattern according to the fourth embodiment will be described with reference to FIG. 12.

12 is a layout view of the discharge pattern according to the fourth embodiment, which has the discharge pattern according to the first embodiment, and a dummy metal line is formed under the discharge element.

As shown in FIG. 12, the discharge metal structure 120 is the same as that of the first embodiment except that the dummy metal line 120 is formed on the substrate 1 in the horizontal direction. In this case, since the dummy metal wire 120 is grounded and overlaps the capacitor ITO pattern 610 with the gate insulating film 200 and the passivation layer 500 therebetween, tunneling occurs in the amorphous silicon pattern 350 to prevent static electricity. When moving from the first pattern portion 430 to the second pattern portion 440 and the capacitor ITO pattern 610, the capacitor ITO pattern 610 and the dummy metal line 151 form a capacitor.

The structure as in the fourth embodiment can discharge static electricity more effectively because another capacitor structure is constructed in the process of forming the wiring in the substrate.

Next, a method of manufacturing a wiring structure according to the present invention will be described below with reference to FIGS. 3 to 12 and 13A to 13F.

First, a metal layer is stacked and patterned on the substrate 1 to form gate wirings such as the gate line 100, the gate pad 101, and the gate electrode 110. In the case of having the structure of the fourth embodiment, in this process, the dummy metal line 120 may be formed parallel to the gate line 100 outside the active area A / A (see FIG. 13A).

The silicon nitride or silicon oxide is laminated, and the amorphous silicon and the doped amorphous silicon are sequentially stacked thereon, and then patterned to form the gate insulating film 200, the amorphous silicon layer 310, and the doped amorphous silicon layers 321 and 322. do. In this process, the amorphous silicon pattern 350 for discharge and the n ⁺ amorphous silicon pattern 351 are formed outside the active area A / A (see FIG. 13B).

Next, the metal layer is deposited and patterned to form data lines such as the data line 400, the data pad 401, the source and drain electrodes 410 and 420. In the process of forming the data line, the first pattern portion 430 and the second pattern portion 440 for discharging may also be formed. When two or more discharge elements D are formed, a plurality of pairs of pattern portions 450 and 460 are formed in this process. The n ⁺ amorphous silicon material exposed by using the source and drain electrodes 410 and 420 and the first and second pattern portions 430 and 440 as a mask is etched to n ⁺ amorphous silicon layers 321 and 322 and n ⁺ amorphous. Silicon patterns 351 and 352 are formed (see FIG. 13C).

A contact hole exposing the drain electrode 420, the data pad 401, and the gate pad 101 by depositing the passivation layer 500 thereon (see FIG. 13D) and patterning the gate insulating layer 200 and the passivation layer 500. C1, C2, C3 are formed, and contact holes C4, C5 exposing the second and fourth pattern portions 440, 441, 460, 461 and the like are formed (see FIG. 13E).

Finally, an ITO material is deposited and patterned to form the pixel electrode 600 in the pixel region PX, and an ITO pattern 610 for a capacitor and a gate pad and data pad contact pattern outside the active region A / A. 601 and 602 are formed (see FIG. 13F).

As described above, by discharging a plurality of discharge patterns of the above-described form in parallel to one data line or two adjacent data lines positioned outside the active region, it is possible to effectively discharge static electricity generated in the substrate.

1 is a layout view schematically showing a liquid crystal display substrate according to the related art,

2 is a layout view schematically illustrating the wiring of the liquid crystal display according to the present invention;

3 is a layout view illustrating pixels of the liquid crystal display according to the present invention;

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

FIG. 5 is a cross-sectional view taken along line VV ′ of FIG. 3.

FIG. 6 is a cross-sectional view taken along line VI-VI ′ of FIG. 3;

7 is a layout view showing a discharge pattern, that is, a portion P1 of FIG. 2,

FIG. 8 is a cross-sectional view taken along line VIII-VIII ′ of FIG. 7;

9 is a perspective view showing a capacitor formed at the end of the discharge pattern,

FIG. 10 is a layout view illustrating a portion P2 of FIG. 2;

FIG. 11 is a layout view illustrating a portion P3 of FIG. 2;

FIG. 12 is a layout view of another embodiment of the portion P1 of FIG. 2;

13A to 13F are cross-sectional views illustrating a method of forming wirings for a liquid crystal display device according to the present invention, in order of process.

Claims (14)

Transparent insulation substrate, A plurality of wirings formed on the substrate, And a discharge part including a semiconductor pattern including a first metal connected to the wiring, a second metal opposite thereto, and a channel between the first metal and the second metal, Static electricity is discharged through the channel by the tunneling effect. In claim 1, A wiring structure in which a holding capacitor is formed on the second metal side. In claim 2, And a plurality of discharge parts connected in parallel to the wiring. In claim 2, And a plurality of discharge parts connected in parallel to two adjacent wirings. Transparent insulation substrate, An insulating film formed on the substrate, A wiring formed in the vertical direction on the insulating film, An amorphous silicon pattern for discharge formed on one outside of the wiring, A first electrode extending from the wiring and in contact with one edge of the amorphous silicon pattern, A second electrode in contact with an edge of the amorphous silicon pattern opposite the first electrode, Static electricity is discharged to the second electrode through the amorphous silicon pattern from the first electrode by the tunneling effect. In claim 5, The liquid crystal display device wiring, wherein the ends of the first and second electrodes are sharply formed. In claim 6, A protective film formed on the first and second electrodes and having a contact hole for exposing the second electrode, and an ITO pattern for a capacitor connected to the second electrode through the contact hole, wherein the ITO The pattern is a wiring for a liquid crystal display device to form a storage capacitor and a common electrode formed on the upper plate of the liquid crystal display device to store the electrostatic charge. In claim 7, And a metal wire formed on the substrate in a horizontal direction, wherein the metal wire overlaps the ITO pattern for the capacitor with the insulating film and the protective film interposed therebetween. Stacking a first metal layer on the transparent insulating substrate, Patterning the first metal layer to form a gate wiring; Forming a gate insulating film, an amorphous silicon layer, a doped silicon layer, and an amorphous silicon pattern for discharge, Stacking a second metal layer, Patterning the second metal layer to form first and second electrodes for data wiring and discharge; The manufacturing method of the wiring for liquid crystal display devices containing these. In claim 9, And the first electrode extends from the data line and has a sharp end thereof, and the pointed portion overlaps one edge of the amorphous silicon pattern. In claim 10, And a tip of the second electrode is sharply formed so as to overlap the edge of the amorphous silicon pattern opposite to the first electrode. In claim 11, Stacking a passivation layer on the data line and the first and second electrodes; and forming a contact hole exposing the second electrode by patterning the gate insulating layer and the passivation layer. In claim 12, Stacking an ITO material on the passivation layer and patterning the ITO material to form an ITO pattern for a capacitor connected to the second electrode through a pixel electrode and the third contact hole. In claim 13, And forming a dummy metal line for discharging by patterning the first metal layer.