KR100633316B1 - Method for fabricating a substrate for TFT type liquid crystal display device - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate, and in order to prevent electrostatic defects between even-numbered gate lines and odd-numbered gate lines respectively connected by short-circuit lines, extending from the arbitrary odd-numbered gate pads, The adjacent even-numbered gate pads are formed so as to face the antistatic wiring extending from the connected gate short wiring very closely, and when static electricity is generated between the two gate wirings during dry etching, the electrostatic discharge is discharged from the antistatic wiring, thereby preventing the electrostatic defects. In addition, since the process of separately cutting the antistatic wiring in a later process can be omitted, there is an effect of preventing damage to the pixel electrode generated during the cutting process.

Description

Method for fabricating a substrate for TFT type liquid crystal display device             

1 is a plan view of a thin film transistor array substrate according to a first example of the related art,

2 is a plan view of a thin film transistor array substrate according to a second conventional example,

3A to 3D are process cross-sectional views cut along II-II, III-III, and IV-IV of FIG. 2 according to a process sequence;

4 is a plan view of a thin film transistor array substrate according to the present invention;

5A through 5D are cross-sectional views of the V-V, VI-VI, and VIII-V of FIG.

  <Brief description of the main parts of the drawing>

111: gate wiring 113: gate pad

115: data wiring 117: data pad

121: source electrode 123: drain electrode

125: active layer 127: gate electrode

129: first gate short-circuit wiring 131: second gate short-circuit wiring

113: gate pad 113a: odd-numbered gate pad

113b: Even-numbered gate pad

141: antistatic wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array for preventing static electricity between gate lines during formation of an array substrate including a data line and a gate line. It relates to a method for manufacturing a substrate.

In general, thin film transistor array substrates are commonly used in liquid crystal display devices and X-ray image sensing devices.

The panel for the liquid crystal display device or the image sensing device is manufactured by bonding an upper substrate and a lower substrate together, and the liquid crystal display device is manufactured by filling a liquid crystal between the upper substrate and the lower substrate, and in the case of the X-ray image sensing device. In the manufacturing process by forming a conductive material between the upper substrate and the lower substrate.

Array substrates used in the two devices are similar in configuration and process.

In general, an array substrate (active matrix array substrate) is formed with a plurality of thin film transistors that drive each pixel in correspondence with a plurality of pixels.

In addition, the gate wiring and the data wiring respectively connected to the gate electrode and the source electrode of the thin film transistor are formed to cross each other.

The pad part includes a gate pad formed at an end of the gate line and a source pad formed at a predetermined area at the end of the data line.

In order to form the above-described array substrate, each element is formed while repeating deposition, photolithography, and etching for each process.

The etching process of the process is determined according to the etching method, and the means for etching may vary according to the material to be etched.

For example, the etching method may be largely divided into dry etching and wet etching, and the wet etching is isotropically etched, so that side etching is performed at the same time.

On the contrary, the dry etching is often performed when anisotropic etching is necessary.

Of the elements constituting the array substrate, the elements etched using the dry etching are mainly a semiconductor layer and an insulating layer, and the elements etched using the wet etching are mainly a conductive metal layer.

The wet etching uses a chemical as an etchant, but the dry etching is performed by using a gas rather than an etching solution.

For example, in the case of dry etching, the etching gas is placed in a plasma state through RF discharge so that the etching gas reacts with the material of the portion to be etched to remove the etching portion, and the ion beam is removed. For example, the etching portion may be removed by using the same method.

The above methods require a high electric field, and when such a dry etching method is used, there is a great possibility of generating static electricity in a patterned wiring, etc., under the element to be etched, and therefore, the open wiring or the lower part of the lower wiring is thus very high. It may cause a short with the wiring.

Therefore, in the case of forming the plurality of gate wirings and the data wiring, it is common to form a shorting bar that binds the plurality of wirings together so that all the wirings are in an equipotential state.

In general, the gate short wiring and the data short wiring connect the gate wiring and the data wiring by dividing the odd and even lines.

Hereinafter, the configuration described above will be described with reference to the accompanying drawings.

1 is a plan view illustrating a portion of a thin film transistor array substrate according to a first example of the related art.

As illustrated, the thin film transistor array substrate 9 includes a thin film transistor T, a pixel P, a gate wiring 11, a gate pad 13 formed at a predetermined area at an end of the gate wiring 11, and a thin film transistor array substrate 9. And a data line 15 formed to intersect the gate line 11 and a data pad 17 formed at a predetermined area at an end of the data line 15.

The thin film transistor T includes a source electrode 21 and a drain electrode 23, and an active layer 25 and a gate electrode 27 that serve as a channel between the two electrodes, and the gate electrode 27. Is formed by protruding and extending from the gate line 11 to a predetermined area, and the source electrode 21 is formed by protruding and extending from a portion of the data line 15.

The plurality of gate lines 11 and the data lines 15 are connected to each other by a single line, which is generally referred to as a shorting bar.

The short-circuit wiring serves to prevent the disconnection or short-circuit of the wiring by the static electricity generated when the array substrate is formed because the plurality of wirings are in an equipotential state.

The gate short wirings 29 and 31 of the gate wiring 11 are formed on one side of the array substrate 9, and the first gate short wiring 29 of the gate short wirings is the gate pad 13. The even-numbered gate pads 13b are connected to each other, and the second gate short wiring 31 is formed by connecting all the odd-numbered gate pads 13a.

The second gate short interconnection 31 connecting the odd-numbered gate pads 13a among the gate short interconnections is formed on the same layer as the data interconnection 15.

At this time, the first gate contact hole 53 formed on the second gate short interconnection 31 of the vertical pattern extending from the second gate short interconnection 31 in the one direction toward the odd gate pad 13a. The transparent electrode is patterned at the same time to the second gate contact hole 54 formed on the gate pad 13 to connect the second gate short interconnection 31 and the odd-numbered gate pad 13a.

This connection can be variously modified.

At this time, in the array substrate having the above-described configuration, the plurality of gate wirings 11 of the portion leading to the gate pad 13 are bent at a predetermined interval and patterned.

Since the bent portion A is patterned in a corner shape, when dry etching the insulating layer formed on the gate wiring 11, charges charged by the RF discharge are concentrated to the corner portion A. FIG.

Therefore, a phenomenon in which charge is charged between adjacent gate wirings 11 may occur, and a short circuit of the gate wirings 11 may occur due to such static electricity.

In order to solve this problem, in the related art, a separate antistatic wiring connecting the odd-numbered gate pad 13a and the first gate short interconnection 29 is formed to leave the odd-numbered and even-numbered gate pads in an equipotential state. have.

Hereinafter, a conventional antistatic structure will be described with reference to the drawings.

2 is a partial plan view of a thin film transistor array substrate having a conventional antistatic structure.

As shown, an odd-numbered gate pad 13a and the first gate short connected to the second gate short interconnect 31 by a transparent electrode pattern 59 formed on the same layer as the data line 15. An antistatic wiring 41 may be formed to electrically connect the wiring 29 so that the even-numbered gate pad 13b and the odd-numbered gate pad 13a may have an equipotential, and thus may occur between the gate wiring 11. To prevent static failure.

However, in order to test the short circuiting of the odd-numbered gate pad 13a and the even-numbered gate pad 13b after the array substrate is completed, a process of cutting the antistatic metal wiring 41 is required.

Hereinafter, the manufacturing process for the above-described configuration will be described with reference to the process cross-sectional views of FIGS. 3A to 3D.

3A through 3D are cross-sectional views illustrating the process sequence by cutting along II-II, III-III, and IV-IV of FIG. 2. (In this case, general components except for the antistatic wiring are indicated by the symbols of FIG. 1. See)

As shown in FIG. 3A, a conductive metal material is deposited and patterned on the transparent substrate 9 to form a gate wiring 11 formed in one direction among the gate electrode 27 and the gate electrode, and an end of the gate wiring. The gate pad 13a having a predetermined area and a first gate short interconnection 29 connecting the even-numbered gate pads (not shown) are formed.

At this time, even-numbered gate pads (not shown) and the first gate short wiring line 29 of the gate pads 13a are orthogonally connected.

In addition, it extends from the plurality of odd-numbered gate pads 13a not connected to the gate short wiring 29 to simultaneously form the antistatic wiring 41 connected to the adjacent first gate short wiring 29.

Next, an insulating material is deposited on the entire surface of the substrate 9 on which the gate wiring 11 and the like are formed to form the gate insulating layer 43.

Next, as shown in FIG. 3B, a semiconductor layer and an impurity semiconductor layer are sequentially stacked and patterned on the gate insulating layer 43 to form an active layer 25 in an island shape on the gate electrode 27. Form.

Next, a conductive metal material is deposited on the entire surface of the substrate 9 on which the active layer 25 is formed, and then patterned to form a source electrode protruding from the data line 15 and the data line above the gate electrode 27. 21, a drain electrode 23 spaced apart from the predetermined interval, a data pad (not shown) extending to a predetermined area at an end of the data line 15, and the first gate short line line 29 are formed. A second gate short interconnection 31 is formed on one side thereof and includes a pattern parallel to the first gate short interconnection 29 and vertically extended to one side of the odd-numbered gate pad 13a.

At this time, chromium (Cr) is generally used as the metal forming the source / drain electrodes 21 and 23. The chromium usable as the data line 15 has a higher resistance than molybdenum (Mo) or other conductive metals, but has excellent chemical resistance to etching solutions.

Molybdenum, on the other hand, has a low resistance and is not strong in strong acid etching solutions. As a result, when the data wiring 15 is formed using molybdenum, a pin hole formed on the protective layer is formed with a strong acid used to later cut the antistatic wiring of the gate metal 27 material. Penetrates into and causes a disconnection defect in the data wiring 15 and the like.

Therefore, to prevent this, chromium is generally used.

Next, a protective layer 49 is formed by depositing the above-described insulating material on the entire surface of the substrate 9 on which the second gate short interconnection 31 and the data interconnection 15 are formed.

As a result, the gate insulating layer 43 and the protective layer 49 are stacked on the odd-numbered gate pad 13a and the even-numbered gate pad 13b of FIG. 2 and on the antistatic wiring 41. The protective layer 49 is stacked on the data line 15, the data pad (not shown), and the second gate short line line (not shown).

Next, as shown in FIG. 3C, the upper portion of the drain electrode 23, the data pad (not shown), and the protection layer 49 on the vertical pattern of the second short circuit 31 are etched to drain the drain. A contact hole 55, a data pad contact hole (not shown), and a first gate pad contact hole 53 are formed, an upper portion of the odd-numbered gate pad 13a, an upper portion of an even-numbered gate pad (not shown), and the The gate insulating layer 43 and the protective layer 49 on the antistatic wiring 41 are etched to etch the second gate pad contact hole 54, the third gate pad contact hole (not shown), and the etching groove 51. To form.

Next, as shown in FIG. 3D, a transparent conductive metal patterned with a strong acid solution such as indium-tin oxide (ITO) or the like is deposited and patterned on the protective layer 49 having the respective contact holes formed therein. The pixel electrode 57 connected to the drain electrode 23 through the contact hole 55, and the first gate pad contact hole 53 and the second gate pad contact hole 54 are simultaneously filled with the pixel electrode 57. An even-numbered gate pad (not shown) through a first gate pad terminal 59 connecting the odd-numbered gate pad 13a and the second short circuit 31 and the third gate pad contact hole (not shown). ) To form a second gate pad terminal (not shown).

At this time, the transparent conductive metal is patterned and the transparent electrode deposited through the etch groove 51 above the antistatic wiring 41 and the antistatic wiring 41 under the same are simultaneously etched.

In order to etch the antistatic wiring 41, a strong acidic etching solution should be used, and thus the transparent conductive metal mainly uses indium-tin oxide (ITO) having excellent chemical resistance.

After forming the array substrate through such a process, a short or open defect between the even-numbered gate line 11 and the odd-numbered gate line is tested.

However, in the above-described process, since the transparent conductive metal pattern is continuously affected by the etching solution while the antistatic wiring 41 is etched, the surface of the pixel electrode 57 is over-etched. do. As a result, damage occurs on the surface of the pixel electrode 57, resulting in deterioration of image quality of the liquid crystal display.

In addition, since a strong acid solution is used, chromium (Cr) having strong chemical resistance is used, but the chromium has a problem that resistance is greater than that of molybdenum or other metal materials.

Therefore, in order to solve the above problems, by designing the anti-static wiring in a new method, by omitting the process of cutting the anti-static wiring, to provide a method for manufacturing a thin film transistor array substrate in a simple process. The purpose is.

The thin film transistor array substrate according to the present invention for achieving the above object is a substrate; A plurality of gate and data lines disposed on the substrate and crossing each other; A plurality of gate pads formed at one end of each gate line and a plurality of data pads formed at one end of the data line; A first gate short interconnection line connecting the even-numbered gate pads of the gate pads, a second gate short interconnection line connecting the odd-numbered gate pads and formed on the same layer as the data line; An antistatic portion having a first antistatic wiring extending from the odd-numbered gate pad and a second antistatic wiring extending from the first gate short wiring and positioned proximate to the first antistatic wiring; And a gate electrode connected to each of the gate lines, a source electrode and a drain electrode connected to the data lines, and an active layer.

The first and second antistatic wirings are each branched into at least two wirings.

The first and second antistatic wirings may be arranged to have first and second proximity distances.

The first proximity distance of the first and second antistatic wiring is about 5 μm, and the second proximity distance is about 10 μm.

The first and second antistatic wirings are each characterized as having an F shape.

According to an aspect of the present invention, a method of manufacturing a thin film transistor array substrate includes preparing a substrate; A plurality of gate wirings on the substrate and gate pads formed at predetermined ends of each of the gate wirings, a first gate short wiring which connects even-numbered gate pads of the gate pads, and an extension of an odd-numbered gate pad; Forming an antistatic portion having a first antistatic wiring and a second antistatic wiring extending from said first gate short wiring and located proximate said first antistatic wiring; Forming a gate insulating layer by depositing an insulating material on an entire surface of the substrate on which the gate wiring and the antistatic part are formed; Forming a second gate short interconnection line, a data interconnection, a source electrode, and a drain electrode on the gate insulation layer, the second gate short interconnection line having a vertical pattern extending in the odd-numbered gate pad direction; Forming a protective layer by depositing an insulating material on the entire surface of the substrate on which the second gate short wiring and the data wiring are formed; The protective layer is patterned to form a drain contact hole on the drain electrode, a first gate pad contact hole and a second gate pad contact on the vertical pattern of the second gate short circuit and the odd / even gate pads, respectively. Forming an etching groove on the hole, the third gate pad contact hole, and the first and second antistatic wirings; Depositing a transparent electrode to fill the pixel electrode in contact with the drain electrode, and filling the first gate pad contact hole and the second gate contact hole, and patterning the second electrode to connect the second gate short circuit and the odd-numbered gate pad. Etching the first gate pad terminal, the second gate pad terminal connected to the even-numbered gate pad through the third gate pad contact hole, and the transparent conductive metal deposited on the etch groove formed on the electrostatic wiring. And exposing the second antistatic wiring.

An antistatic method between gate wirings according to an aspect of the present invention includes a substrate having a first region and a second region, and a plurality of gate wirings extending in one direction from the first region on the substrate; A plurality of data lines crossing the gate lines; A method for preventing static electricity between a plurality of gate wirings of a thin film transistor array substrate including a thin film transistor connected to the gate wiring and the data wiring, the method comprising: a first antistatic wiring connected to an odd-numbered gate wiring in the second region; And a second antistatic wiring connected to the even-numbered gate wiring and positioned in close proximity to the first antistatic wiring.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a partial plan view of a thin film transistor array substrate according to the present invention.

As shown, the thin film transistor array substrate may be largely divided into a pad portion C and a display portion D, and the pad portion C may include a gate pad portion 113 and a data pad 117. The display unit D is defined by the gate wiring 111, the data wiring 115, the gate wiring 111 and the data wiring 115 intersecting with each other, and the pixel electrode 157 is formed thereon. ) And a thin film transistor (T) which is a switching element at the intersection of the gate wiring 111 and the data wiring 115.

The thin film transistor T may include a gate electrode 127 having a predetermined area protruding in one direction from the gate wiring 111 and a source electrode 121 and a drain protruding from the data wiring 115 above the gate electrode 127. The electrode 123 and the active layer 125 are included.

A gate pad 113 is formed at the end of the gate wiring 111, and a data pad 117 is formed at the end of the data wiring 115.

At this time, the portion B, which is bent from the gate wiring 111 to the gate pad 113 and continues to be bent, unlike the conventional method, thereby preventing the wiring defect due to the accumulation of electric charge.

The gate pad 113 and the data pad 117 are defined as odd and even numbers, respectively, and the even gate pad 113b and the data pad 117b are respectively provided with a first gate short wiring 129 and a first gate. The odd-numbered gate pad 113a and the data pad 117a are simultaneously connected to the second gate short circuit 131 and the first data short circuit (not shown). .

Each of the short-circuit wirings allows a plurality of pads connected to each short-circuit wiring to have an equipotential, thereby preventing disconnection of each wiring that may occur in the odd-numbered or even-numbered wiring by static electricity generated by RF discharge during dry etching. have.

In this case, in order to prevent an electrostatic defect that may occur between the adjacent odd-numbered gate lines and even-numbered gate lines, the first anti-static line extending from the odd-numbered gate pads 113a and the even-numbered gate pads 113b are provided. The second antistatic wiring extending from the first gate short wiring 129 connecting the second antistatic wiring 141 is formed to form a proximity.

At this time, the anti-static wiring 141 is not connected, preferably by forming a very close distance facing the two F-shaped wiring, if the static electricity between the gate wiring 111, the charged charge is Discharge occurs along the anti-wiring 141 and damages only the anti-static wiring 141 by generating a discharge in the closely spaced portion E. FIG. At this time, the distance between the first protrusion 141a protruding from the antistatic wiring formed in one direction of the F-shaped electrostatic wiring 141 is patterned to have a distance of 1 ~ 5㎛, the second protrusion protruding from the wiring 141b is patterned so as to have a distance of 5 to 10 μm.

Therefore, unlike the related art, the process of cutting the antistatic wiring 141 at the end of the process may be omitted.

Since the step of cutting the antistatic wiring 141 is omitted, it is not necessary to use a strong acid solution used to cut the antistatic wiring 141.

For this reason, the metal material forming the source / drain electrodes 121 and 123 may be patterned in a weak acidic solution, a conductive metal such as molybdenum having a low resistance, and may be indium-zinc-oxide etched in a weak acid. The pixel electrode 157 may be formed using IZO.

A process sequence of the thin film transistor array substrate according to the present invention having the configuration as described above will be described with reference to FIGS. 5A to 5D.

5A through 5D are cross-sectional views of the V-V, VI-VI, and VIII-V of FIG.

As shown in FIG. 5A, a conductive metal material such as aluminum (Al), aluminum alloy (Mo alloy), molybdenum (Mo), tungsten (W), chromium (Cr), or the like is deposited on the transparent substrate 109 to form a pattern. The gate electrode 127, the gate wiring 111, the gate pad having a predetermined area (113 in FIG. 4), and the even-numbered gate pad (113b in FIG. 4) are disposed at the end of the gate wiring. A first gate short interconnection line 129 is formed to connect.

An antistatic wiring 141b is formed between the plurality of odd-numbered gate pads 113a not connected to the short circuit and the first gate short wiring 129 adjacent thereto.

The antistatic wiring 141b has two F-shaped antistatic wirings (141 in FIG. 4) formed to extend to the odd-numbered gate pad 113a and the first gate short wiring 129, and face each other. Configure to view.

Next, an inorganic insulating material such as a silicon oxide film (SiO ₂ ) and a silicon nitride film (SiN _x ), and in some cases benzocyclobutene (BCB) and acryl, on the entire surface of the substrate 109 on which the gate wiring 111 and the like are formed. An organic insulating material such as (Acryl) is deposited to form a gate insulating layer 143.

Next, as illustrated in FIG. 5B, a semiconductor layer and an impurity semiconductor layer are formed and patterned on the gate insulating layer 143 to form an active layer 125 on the gate electrode 127.

Next, a conductive metal material is deposited on the entire surface of the substrate 109 on which the active layer 125 is formed, and then patterned to form a data electrode 115 and a source electrode protruding from the data electrode to the gate electrode 127. (121), a drain electrode 123 spaced apart from the predetermined interval, a data pad (not shown) extending to a predetermined area at the end of the data wiring 115, and the first gate short wiring 129 is formed A second gate short interconnection line 131 is formed on one side of the second gate short interconnection line 129, the second gate short interconnection line 131 being parallel to the first gate short interconnection line 129 and including a pattern extending vertically to the top of the odd-numbered gate pad 113a.

Next, the protective layer 149 is formed by depositing the above-described insulating material on the entire surface of the substrate 109 on which the second gate short wiring 131 and the data wiring 115 are formed.

As a result, the gate insulating layer 143 and the protective layer 149 are stacked on the gate pad 113a and the antistatic wiring 141, and the data wiring 115 and the second gate are stacked. The protective layer 149 is stacked on the short circuit line 131.

Next, as shown in FIG. 5C, the protective layer 149 is etched on the drain electrode 123, the data pad (not shown), and the vertical pattern of the second gate short circuit 131. A drain contact hole 155, a data pad contact hole (not shown), and a first gate pad contact hole 153 are formed, and an upper portion of the odd-numbered gate pad 113a and an upper portion of an even-numbered gate pad (not shown) are provided. The gate insulating layer 143 and the protective layer 149 on the antistatic wiring 141 are etched to etch the second gate pad contact hole 154, the third gate pad contact hole (not shown), and the etching groove 151. ).

Next, as illustrated in FIG. 5D, the transparent conductive metal etched in a weakly acidic solution such as indium-zinc-oxide (IZO) or the like is deposited and patterned on the protective layer 149 on which each contact hole is formed. The pixel electrode 157 connected to the drain electrode 123 through the contact hole 155, and the first gate pad contact hole 153 and the second gate pad contact hole 154 are simultaneously filled with the pixel electrode 157. An even-numbered gate pad (not shown) through a first gate pad terminal 159 connecting the odd-numbered gate pad 113a and the second short circuit line 131 and the third gate pad contact hole (not shown). ) To form a second gate pad terminal (not shown).

In this case, the main array process is completed by simultaneously etching the transparent conductive metal deposited through the etching groove 151 formed on the antistatic wiring 141 and exposing the antistatic wiring 141b.

In the process according to the present invention as described above, the conductive metal material for forming the data wiring and the source electrode, etc. may use molybdenum which can be etched in a weak acidity with low resistance. Because the anti-static wiring formed on the same layer as the gate wiring does not need a cutting process later, the data wiring may be disconnected by the etching solution since it is not necessary to use a strong acid etching solution used to cut the anti-static wiring. Because there is no concern.

In addition, since the weakly acidic solution is used, the transparent electrode used for the pixel electrode may use indium-zinc-oxide etched with weak acid.

In addition, the antistatic wiring structure according to the present invention as described above can be configured in the thin film transistor array substrate by a process of less than 4 masks.

Therefore, the thin film transistor array substrate according to the present invention as described above is formed by separating the antistatic wiring at a close distance, there is no need to cut the antistatic wiring separately for the electrical test between the wiring.

Therefore, first, there is a process simplification effect in manufacturing the array substrate.

Second, since the antistatic wiring is not continuously etched while the transparent electrode is patterned, there is no fear that the pixel electrode is excessively etched and damaged, so that a high quality display panel can be manufactured.

Third, molybdenum, a low-resistance material that was difficult to mass-produce, can be used because it does not require the use of a strongly acidic solution for cutting antistatic wiring, thereby improving signal delay problems and using indium-zinc-oxide having low specific resistance Since the pixel electrode can be formed, the image quality can be improved.

Claims (9)

A substrate; A plurality of gate and data lines disposed on the substrate and crossing each other; A plurality of gate pads formed at one end of each gate line and a plurality of data pads formed at one end of the data line; A first gate short interconnection line connecting the even-numbered gate pads of the gate pads, a second gate short interconnection line connecting the odd-numbered gate pads and formed on the same layer as the data line; An antistatic portion having a first antistatic wiring extending from the odd-numbered gate pad and a second antistatic wiring extending from the first gate short wiring and positioned proximate to the first antistatic wiring; A switching element including a gate electrode connected to each of the gate lines, a source electrode and a drain electrode connected to the data lines, and an active layer Thin film transistor array substrate comprising a. The method of claim 1, And the conductive metal forming the data line with the source / drain electrodes is one selected from the group consisting of molybdenum and chromium. delete The method of claim 1, And the first and second antistatic wirings are branched into at least two wirings, respectively, and are disposed with first and second proximity distances, respectively. The method of claim 4, wherein The first proximity distance of the first and second antistatic wiring is 1 ~ 5㎛, the second proximity distance is 5 ~ 10㎛ thin film transistor array substrate. Preparing a substrate; A plurality of gate wirings on the substrate and gate pads formed at predetermined ends of each of the gate wirings, a first gate short wiring which connects even-numbered gate pads of the gate pads, and an extension of an odd-numbered gate pad; Forming an antistatic portion having a first antistatic wiring and a second antistatic wiring extending from said first gate short wiring and located proximate said first antistatic wiring; Forming a gate insulating layer by depositing an insulating material on an entire surface of the substrate on which the gate wiring and the antistatic part are formed; Forming a second gate short interconnection line, a data interconnection, a source electrode, and a drain electrode on the gate insulation layer, the second gate short interconnection line having a vertical pattern extending in the odd-numbered gate pad direction; Forming a protective layer by depositing an insulating material on the entire surface of the substrate on which the second gate short wiring and the data wiring are formed; Patterning the protective layer, a drain contact hole on the drain electrode, A first gate pad contact hole, a second gate pad contact hole, and a third gate pad contact hole on the vertical pattern of the second gate short wiring and the odd / even gate pads, respectively, and the first and second static electricity Forming an etching groove on an upper part of the prevention wiring; Depositing a transparent conductive metal and filling the pixel electrode in contact with the drain electrode, and filling the first gate pad contact hole and the second gate contact hole to pattern the second gate short interconnection line and the odd-numbered gate pad. A first gate pad terminal, a second gate pad terminal connected to the even-numbered gate pad through the third gate pad contact hole, and a transparent electrode deposited in an etching groove formed on the first and second electrostatic wirings To expose the antistatic wiring Thin film transistor array substrate manufacturing method comprising a. The method of claim 6, The transparent conductive metal is a thin film transistor array substrate manufacturing method of one selected from the group of transparent conductive metals including indium tin oxide, indium zinc oxide. The method of claim 6, And the first and second antistatic wirings are branched into at least two wirings, respectively, and are disposed with first and second proximity distances, respectively. The method of claim 8, The first proximity distance of the first and second antistatic wiring is 1 ~ 5㎛, the second proximity distance is 5 ~ 10㎛ thin film transistor array substrate manufacturing method.

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