KR101433105B1 - An Array mother glass substrate of Liquid Crystal Display Device and the method for fabricating thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of detecting the occurrence of static electricity.

In order to visually or microscopically detect the presence or absence of the generation of static electricity entering the array mother substrate for a liquid crystal display device, a test pattern, which is easy to measure the voltage of the static electricity, is inserted in the via array region of the array mother substrate, The presence or absence of defects can be read.

Such a test pattern is advantageous in that the production yield can be improved by detecting the presence or absence of defects before proceeding with the cell process because it is easy to grasp the generation level of the static electricity in each process.

Description

[0001] The present invention relates to an array mother substrate for a liquid crystal display device and a manufacturing method thereof,

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of detecting the occurrence of static electricity.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal layer filled in spaces between the color filters and the array substrate. The liquid crystal is driven by a vertical electric field which is vertically applied to the upper and lower sides, and the characteristics such as the transmittance and the aperture ratio are excellent.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a plan view showing a conventional array substrate for a liquid crystal display device.

As shown in the drawing, a plurality of gate wirings (not shown) are provided to receive a scan signal in one direction on a substrate 10 divided into a display area AA for realizing an image and a non-display area NAA excluding the display area AA. And a plurality of data lines 30 crossing the plurality of gate lines 20 and receiving data signals. At this time, the gate line 20 and the data line 30 define a plurality of pixel regions P in a matrix form.

A gate electrode (not shown), a semiconductor layer (not shown), and a source and a drain electrode (not shown) are provided in a one-to-one correspondence with the intersections of the gate wiring 20 and the data wiring 30 A plurality of thin film transistors T constituted by three terminal elements constituting a plurality of thin film transistors are formed. In addition, the pixel electrodes 80 connected to the thin film transistor T correspond to the pixel regions P in a one-to-one correspondence.

At this time, the pixel electrode 70 is driven by a vertical electric field system that controls the liquid crystal direction by a potential difference with a common electrode (not shown) formed inside a color filter substrate (not shown) bonded to the array substrate 10 . Although not shown in the drawings, the pixel electrode 70 and the common electrode (not shown) are alternately arranged in the pixel region P so that the horizontal electric field between the pixel electrode 70 and the common electrode A transverse electric field system for driving the liquid crystal can be used.

A plurality of gate pads 52 and data pads 62 for transferring scan signals and data signals to the plurality of gate wirings 20 and the data wirings 30 are formed in the non-display area NAA on the substrate 10, ).

In the array substrate for a liquid crystal display having the above-described configuration, a cell process step for fabricating a liquid crystal panel is performed between the array substrate and the color filter substrate via a liquid crystal layer in a state of being adhered to a color filter substrate on which color filter elements are formed do.

Such a cell process refers to a process in which a completed array substrate and color filter substrate are attached to each other in a face-to-face manner, and a driving circuit portion is attached to an array substrate to produce a signal driveable state, which will be described in detail below with reference to the accompanying drawings .

Figure 2 is a process flow diagram showing the cell processing steps.

As shown, generally, the cell process steps can be classified into seven stages.

First, a first step ST1 is a step of preparing an array substrate on which array elements and color filter elements are formed and a color filter substrate, respectively.

Next, the second step ST2 is an alignment film formation and a rubbing process. In the above step, upper and lower alignment films are formed on the array substrate and the color filter substrate by using a polymer material such as polyimide, and a uniform line inclination angle (pretilt angle) to align the liquid crystal molecules uniformly.

The third step ST3 is a step of forming a cell gap, which ensures a cell gap of the array and the color filter substrate uniformly. In this case, since the liquid crystal display device is an electro-optical device that applies voltage to the liquid crystal molecules injected with a certain gap between the array substrate and the color filter substrate to drive them, if the cell gap of both substrates is not constant, It is difficult to realize uniform brightness.

Therefore, it is an important task to uniformly spray the spacers on the front surface of the driven liquid crystal panel to uniformly maintain the cell gap of both substrates.

The fourth step (ST4) is a lapping step. In the above step, the seal patterns made of the thermosetting resin or the ultraviolet ray-curable resin are bonded together while maintaining a constant cell gap.

The fifth step ST5 is a cell cutting step. The above step is a step of cutting and separating each substrate on a cell-by-cell basis after the seal pattern hardening step. In this step, a diamond- And a braking process in which a force is applied to cut the braking process.

The sixth step (ST6) is a liquid crystal injection step, and the above step is a step of injecting liquid crystal onto both substrates. At this time, when fine air bubbles in the liquid crystal are injected into the cells, bubbles are formed due to bonding of the liquid crystal molecules with time, which may lead to defects. Therefore, a vacuum process and a liquid crystal injection process .

Finally, the seventh step ST7 is a polarizing plate attaching step. In the above step, the cell lighting test is performed to apply optical and electrical signals to the cells into which the liquid crystal is injected, and then the upper and lower polarizing plates are attached to both sides of the cell The cell process step is finally completed.

However, conventionally, there is not provided means for determining whether or not the static electricity is generated at each step of forming the array elements which are the steps before the cell process.

In addition, in the manufacturing process of the array device, in the super-clean room where the miniaturization technology is advanced, when static electricity accumulates due to defects due to sub-micron fine dust and defective rate increase, floating dust in the ambient air is adsorbed and attached, There is a problem that the defective rate due to the defects increases. This may cause a short circuit between electrodes due to electrostatic high electric field.

In this case, the presence or absence of defects such as defective driving due to static electricity and line defects can be detected through the cell process step, particularly cell lighting inspection, It is impossible to detect defects.

In some liquid crystal display devices, static electricity prevention circuit wirings and circuit elements (not shown) for grasping the presence or absence of static electricity in each circuit portion during the manufacturing process of the array element are further configured to detect the occurrence of static electricity, There is a problem that the presence or absence of static electricity in the entire region of the array substrate can not be detected, and the detection power is significantly lowered.

Therefore, in the conventional liquid crystal display device, cell lighting inspection for monitoring the entire area of the array substrate with a microscope must be performed in order to trace the occurrence of static electricity, and it is impossible to derive the defective stage early.

This is a factor that significantly deteriorates the production yield in that it can detect the occurrence of static electricity only after the cell process for attaching the array substrate and the color filter substrate to each other.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to improve a production yield by inserting a test pattern capable of detecting the occurrence of static electricity before proceeding with a cell process step.

According to an aspect of the present invention, there is provided an array mother substrate for a liquid crystal display, comprising: a mother substrate divided into an array region and a via region; an array element corresponding to the array region on the mother substrate; And a plurality of test patterns inserted in an electrically insulated state in order to detect the occurrence of static electricity corresponding to the non-array area on the test pattern. And the plurality of test patterns are designed to correspond to the via-lay regions surrounding the four sides of the array region, respectively.

The test pattern may include a gate pattern made of the same material as the gate wiring, first to fifth semiconductor patterns in which a part of the gate pattern and the gate insulating film are overlapped with each other, and a part of the gate pattern And includes an exposed gate hole.

Wherein the gate pattern includes a vertical portion vertically branched to both sides, a horizontal portion connecting the vertical portions on both sides from the upper side and the lower side, and a second portion extending from the horizontal portion to the first portion, And vertically diverted first to fifth lightning conductors and first to fifth lightning conductors.

In addition, the first through the fifth lightning conductors and the first through fifth lightning conductors further include first through fifth detection regions superimposed on the first through fifth semiconductor patterns, respectively, with the gate insulating film interposed therebetween.

At this time, the first to fifth detection areas detect an amount of static electricity generated in the process of forming the array device in stages.

In the test pattern, the first detection region is 1 kV, the second detection region is 2 kV, the first detection region is 2 kV, the second detection region is 2 kV, The third detection region is set to 3 kV, the fourth detection region is set to 4 kV, and the fifth detection region is set to have the gate insulating film corresponding to each of them when the electrostatic voltage of 5 kV is introduced.

The first to fifth semiconductor patterns may be formed of a single layer of polycrystalline silicon, or amorphous silicon containing pure amorphous silicon and impurities, in that order.

According to an aspect of the present invention, there is provided an array mother substrate for a liquid crystal display, comprising: a mother substrate divided into an array region and a via region, the array elements corresponding to the array region on the mother substrate, And forming a plurality of electrically insulated test patterns to detect the occurrence of static electricity corresponding to the via-lay region.

The forming of the test pattern may include forming first to fifth semiconductor patterns corresponding to a via region on the mother substrate, forming a gate insulating film on the first to fifth semiconductor patterns, Forming an electrically insulated gate pattern on the gate insulating layer, and forming an interlayer insulating layer including a gate hole exposing a part of the gate pattern on the gate pattern.

And the plurality of test patterns are formed corresponding to the via area regions surrounding the four sides of the array area.

The gate pattern may include a vertical portion vertically branched on both sides, a horizontal portion connecting the vertical portions on both sides from the upper side and the lower side, and a second portion extending from the first portion to the fifth semiconductor pattern, And includes first through fifth and fifth through fifth lightning conductors vertically branched so as to overlap each other.

The first to fifth resistive elements and the first to fifth resistive elements further include first to fifth detection regions superimposed on the first to fifth semiconductor patterns with the gate insulating film interposed therebetween.

At this time, the first to fifth detection areas are regions for detecting the amount of static electricity generated in the process of forming the array elements in stages.

In the test pattern, the first detection region is 1 kV, the second detection region is 2 kV, the first detection region is 2 kV, the second detection region is 2 kV, The third detection region is set to 3 kV, the fourth detection region is set to 4 kV, and the fifth detection region is set to have the gate insulating film corresponding to each of them when the electrostatic voltage of 5 kV is introduced.

At this time, the first to fifth semiconductor patterns may be formed as a single layer of polycrystalline silicon, or amorphous silicon containing pure amorphous silicon and impurities, in that order.

In the present invention, first, the presence or absence of defects due to static electricity can be detected early by inserting a test pattern.

Second, the production yield can be improved by detecting the defects due to static electricity before the cell process step.

Third, microscopic examination of the entire area according to each process step of the array device is unnecessary.

Fourth, by inserting test patterns, it is possible to identify the electrostatic voltage generated in the array mother board by the microscope and the naked eye.

Fifth, no additional masking process is required.

--- Example ---

The present invention is characterized in that the presence or absence of static electricity can be determined through a test pattern inserted in a via area during formation of array elements on an array mother substrate for a liquid crystal display.

Hereinafter, a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

3 is a plan view showing an array mother substrate for a liquid crystal display according to the present invention.

As shown in FIG. 1, an array substrate (not shown) for a liquid crystal display (LCD) is generally divided into a plurality of array regions AA and a plurality of array mother substrates 100 Thereby forming array elements. In the array region AA on the array mother substrate 100, gate and data lines 120 and 130 are formed to define a plurality of liquid crystal cells perpendicularly intersecting each other.

A plurality of thin film transistors T corresponding one-to-one to the liquid crystal cell and a plurality of pixel electrodes (not shown) respectively contacting the plurality of thin film transistors T are formed at intersections of the gate and data lines 120 and 130 . At this time, all the electrodes and wiring formed on the array mother substrate 100 are referred to as an array substrate.

On the other hand, a plurality of electrically isolated island-shaped test patterns 180 are formed corresponding to the via-lay regions NAA surrounding the four sides of the array region AA on the mother substrate 100. At this time, the plurality of test patterns 180 function to detect the occurrence of static electricity before completion of the array elements.

The test pattern 180 is most preferably designed corresponding to the entire area on the mother substrate 100. The array area AA is formed by inserting the test pattern 180 into a portion where a plurality of array elements are formed There is a limitation that four holes are inserted correspondingly in the up, down, left, and right directions surrounding the array area AA corresponding to the above-mentioned via array area NAA.

Hereinafter, the test pattern described above will be described in detail with reference to the accompanying drawings.

FIG. 4 is an enlarged plan view of part A of FIG. 3, and FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 4, illustrating a coplanar type structure.

4 and 5, the test pattern 180 is formed in correspondence with the via area NAA on the mother substrate 100, and the test pattern 180 is electrically insulated from the first, A gate insulating film 145 on the first to fifth semiconductor patterns 140a to 140e and a gate insulating film 145 on the gate insulating film 145. The gate insulating film 145 is formed on the first to fifth semiconductor patterns 140a, 140b, 140c, A pattern 150 and a gate hole GH exposing a part of the gate pattern 150. [

The first to fifth semiconductor patterns 140a to 140e are formed on a semiconductor layer (not shown) corresponding to the array region (AA in FIG. 4) and the gate pattern 150 is formed on the gate wiring ) And the same material of the same layer. The gate hole GH may be formed by the same process as a source and a drain hole (not shown) that respectively expose a part of a semiconductor layer (not shown) corresponding to the array region (AA in FIG. 4).

The gate pattern 150 includes a vertical portion 150a vertically branched on both sides and a horizontal portion 150b connecting the vertical portions 150a on both sides from the upper side and the lower side, 150b, 150c, 150d, 150e, 150f, 150g and the first through fifth lightning rods 150h, 150h, 150e, and 150d vertically branched so as to overlap the first through fifth semiconductor patterns 140a through 140e, respectively, 150i, 150j, 150k, 150l).

The first through fifth semiconductor light-emitting devices 150a through 150g and the first through fifth semiconductor light-emitting devices 150h through 150l are spaced apart from each other with the first through fifth semiconductor patterns 140a through 140e interposed therebetween The first and second lightning arresters 150c and 150h, the 2a and 2b 150d and 150i lightning rods, the 3a and 3b lightning rods 150e and 150j and the 4a and 4b lightning rods D2, d3, d4, d5 between the first, fifth, and fifth lightning arresters 150g, 150k, 150a, 150b, 150k and the fifth and fifth lightning arresters 150g, 150l.

The first through fifth lightning conductors 150c through 150g and the first through fifth lightning strikers 150h through 150l are connected to the mother board 100 in such a manner that when the static electricity flows into the mother board 100, .

Here, the first and second lightning arresters 150c and 150h and the first semiconductor pattern 140a, the second and the second lightning conductors 150d and 150i and the second semiconductor pattern 140b, the third and the third lightning rods 150a and 150j and the third semiconductor pattern 140c, the fourth and fourthb lightning rods 150f and 150k and the fourth semiconductor pattern 140d, the fifth and fifthb lightning conductors 150g and 150l, D2, D3, D4, and D5 are defined as the first, second, third, fourth, and fifth detection regions D1, D2, D3, D4, and D5. The first through fifth lightning conductors 150c through 150g and the first through fifth lightning conductors 150h through 150l corresponding to the first through fifth detection regions D1 through D5 are electrically connected to each other through the gate insulating film 145 And are overlapped with the first to fifth semiconductor patterns 140a to 140e, respectively.

The first to fifth lightning arresters 150c to 150g corresponding to the first to fifth detection areas D1 to D5 and the first to fifth light receiving parts 150a to 150g corresponding to the first to fifth detection areas Dl to D5 from the first detection area D1 to the fifth detection area D5, D2, d3, d4, and d5 of the fifth through fifth lightning rods 150h through 150l are spaced apart from each other to detect the amount of static electricity that is drawn into the mother board 100. [

In this test pattern 180, when static electricity is drawn into the mother substrate 100, a static electricity of several kV or more flows through the gate pattern 150 in which the current flows, and the sharpness of the gate pattern 150 The static electricity is concentrated on the end portions of the first to fifth lightning rods 150c to 150g and the first to fifth lightning rods 150h to 150l, which have a small radius of curvature.

At this time, the free electrons accelerated by the electric field of the static electricity are concentrated in the first through fifth light-emitting devices 150c through 150g and the first through fifth light-incident devices 150h through 150l, The electric energy is released as thermal energy when the electric field intensity of the electric field reaches the dielectric breakdown field by the patterns 140a to 140e and the weak portion of the gate insulating film 145 corresponding to this electric field is destroyed.

In other words, the test pattern 180 according to the present invention is formed so that the distance d1, d2, d3, d4, and d5 from the first detection area D1 to the fifth detection area D5, The fragile portion of the gate insulating film 145 is broken, and the amount of static electricity can be grasped by a microscope or the naked eye.

For example, in the test pattern 180, the respective distances d1, d2, d3, d4, and d5 corresponding to the first to fifth detection areas D1 to D5 are 10 μm, 20 μm, 30 μm, The second detection region D2 is 2 kV, the third detection region D3 is 3 kV, the fourth detection region D4 is 4 kV, the fifth detection region D2 is 5 kV, The region D5 is set so that the gate insulating film 145 corresponding to each of the regions D5 is broken when an electrostatic voltage of 5 kV is introduced.

Accordingly, it is possible to grasp the static electricity generation voltage at each process step through the breakdown of the gate insulating film 145 corresponding to the first to fifth detection regions D1, D2, D3, D4, and D5.

For example, the set values may identify the presence or absence of breakage of the gate insulating film 145 in each of the first to fifth detection regions D1 to D5 by a microscope or the naked eye, and detect the presence or absence of breakage of the gate insulating film 145 in the first to third detection regions D1, When the gate insulating film 145 corresponding to the fourth and fifth detection regions D4 and D5 is destroyed, it is determined that there is a possibility of a defect due to static electricity. Which is the final result.

Therefore, the test pattern 180 according to the present invention has an advantage that it can grasp the occurrence level of static electricity step by step and grasp the defect by static electricity before the cell process step.

In this case, the test pattern 180 is divided into the first to fifth detection regions D1 to D5 to detect the generation level of the electrostatic voltage. However, the present invention is not limited thereto. For accurate measurement, 7 detection area (not shown) can be further designed.

Here, the set values may vary according to the separation distances d1 to d5 corresponding to the first to fifth detection areas D1 to D5, respectively, and these set values are derived through the electrostatic test test. The static test is performed to determine whether the test pattern 180 formed on the non-array area NAA of the array mother substrate 100 is operated and the distance d1 To detect the electrostatic voltage at which the gate insulating film 145 in each of the regions D1 to D5 is destroyed.

The static electricity test is performed by contacting an electrostatic gun (not shown) with the gate hole GH exposing a part of the gate pattern 150 to sequentially increase the electrostatic voltage, D5 of the test pattern 180 are all broken, thereby determining whether the test pattern 180 is operated.

The gate insulating film 145 is broken in the regions D1 to D5 according to the distance d1 to d5 of the first to fifth detection regions D1 to D5 through the electrostatic gun (not shown) The specific electrostatic voltage is measured.

Therefore, in the present invention, it is possible to detect in advance the presence or absence of a defect in the static electricity by inserting the test pattern into the step of forming the array element. Accordingly, when the defects due to excessive static electricity are detected as test patterns in the process of forming the array elements, the production yield can be improved by crushing or disposing the array mother substrate.

Hereinafter, a method of manufacturing an array mother substrate for a liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

FIGS. 6A to 6D are sectional views of the process in accordance with the process order of cutting along the line V-V of FIG. 4, and FIGS. 7A to 7D are cross-sectional views of the process of cutting along the thin film transistor portion corresponding to the array region, to be.

As shown in FIGS. 6A and 7A, a step of dividing an array area AA, which implements an image on the mother substrate 100, into a via area NAA excluding the array area AA is proceeded.

A polycrystalline silicon layer (not shown) made of polycrystalline silicon is formed on the mother substrate 100 divided into the plurality of regions AA and NAA and patterned to form a semiconductor layer 140 and 140a, 140b, 140c, 140d and 140e of FIG. 4 are formed in correspondence with the via-hole regions NAA, respectively.

Although not shown in the drawing, the semiconductor layer 140 and the first to fifth semiconductor patterns 140a to 140e may include an active layer (not shown) made of pure amorphous silicon (a-Si: H) , And an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities are stacked in this order.

Inorganic insulating materials, including the semiconductor layer 140 and the first to fifth semiconductor pattern (Fig. 140a to 140e of four) of silicon oxide on the mother substrate 100, the upper front-formed (SiO ₂₎ and silicon nitride (SiNx) A gate insulating film 145 is formed with a selected one of the groups.

6B and 7B, copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), and aluminum are sequentially stacked on the mother substrate 100 having the gate insulating film 145 formed thereon. A gate metal layer (not shown) made of one selected from the group consisting of aluminum alloy (AlNd) and a conductive metal group including chromium (Cr) or the like is formed and patterned to form a gate metal layer (120 in FIG. 3) and the gate electrode 125 extending from the gate wiring (120 in FIG.

At the same time, a gate pattern (150 in FIG. 4) is formed corresponding to the via area NAA. The gate pattern 150 in FIG. 4 includes vertical portions 150a vertically branched on both sides, A horizontal part 150b connecting the vertical part 150a of the first semiconductor chip 150a to the vertical part 150a of the first semiconductor chip 150a, 150b, 150c, 150d, 150e, 150f, 150g of FIG. 4 and the first through fifth lightning rods 150h, 150i, 150j, 150k, 150l vertically branched so as to overlap each other.

In this case, the first to fifth semiconductor patterns (140a to 140e in FIG. 4), the 1a to 5a lightning rod (150c, 150d, 150e, 150f, 150g in FIG. 4) D2, D3, D4, and D5 of FIG. 4) corresponding to each of the first, second, third, and fourth detection regions 150a, 150h, 150i, 150j, 150k,

The first to fifth detection areas (D1 to D5 in Fig. 4) are the distance between the 1st to 5th lightning rods (150c to 150g in Fig. 4) and the 1st to 5th lightning rods (150h to 150l in Fig. 4, (D1 to d5 in FIG. 4), thereby detecting the amount of static electricity that is drawn into the mother substrate 100 in the process of forming the array elements.

7C and 8C, silicon oxide (SiO ₂ ) is formed on the mother substrate 100 on which the gate electrode 125, the gate wiring (120 in FIG. 3) and the gate pattern (150 in FIG. 4) And an organic insulating material group including a group of inorganic insulating materials containing silicon nitride (SiNx) or photo acryl and benzocyclobutene.

Next, an interlayer insulating film 155 corresponding to the vertical portion 150a of the gate pattern and the source and drain regions (not shown) is patterned to form a part of the semiconductor layer 140 corresponding to the array region AA A gate hole GH exposing the vertical portion 150a of the gate pattern corresponding to the via hole region NAA is formed.

4), gate patterns (150 in FIG. 4), and gate holes (GH) corresponding to the via array regions (NAA) Of 180).

The test pattern (180 in Fig. 4) according to the present invention has a distance (d1, d2, d3, d4 in Fig. 4) from the first detection area (D1 in Fig. 4) to the fifth detection area and d5, and an element that induces a fragile portion of the gate insulating film 145 to break in accordance with the set electrostatic voltage. Thus, it is possible to grasp the amount of static electricity generated by a microscope or the naked eye.

Therefore, it is possible to grasp the static electricity generation voltage at each process step through the breakdown of the gate insulating film 145 corresponding to the first to fifth detection regions (D1, D2, D3, D4, and D5 in FIG. 4) .

7D and 8D, copper (Cu), molybdenum (Mo), molybdenum alloy (molybdenum), and the like are formed on the mother substrate 100 including the source and drain holes SH and DH and the gate hole GH A source and drain metal layer (not shown) made of one or two or more alloys selected from the group consisting of aluminum (Al), aluminum (AlNd), and chromium (Cr) A source electrode 132 extending in the data line and in contact with the semiconductor layer 140 through the source hole SH; And a drain electrode 134 spaced apart from the source electrode 132 and in contact with the semiconductor layer 140 through a drain hole DH.

Next, a drain contact hole CH1 is formed on the mother substrate 100 on which the data line (130 in FIG. 3) and the source and drain electrodes 132 and 134 are formed, with a selected one of the above- A protective film 165 is formed.

Next, a transparent metal layer (not shown) is formed on the passivation layer 165 including the drain contact hole CH1 with a conductive metal group selected from the group consisting of indium-tin-oxide (ITO) and indium-zinc- And the pixel electrode 170 is formed in contact with the drain electrode 134 through the drain contact hole CH1.

Thus, the array substrate for a liquid crystal display according to the present invention can be manufactured.

Therefore, the present invention has the advantage of not requiring an additional mask since it constitutes each element of the test pattern in the step of forming the array elements corresponding to the array area.

Although the coplanar structure is described as an example in the embodiment of the present invention, the present invention is not limited thereto, and a top gate type in which the gate electrode is located at the uppermost position or a bottom gate type in which the gate electrode is located at the bottom Of the present invention.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

1 is a plan view of a conventional array substrate for a liquid crystal display;

Figure 2 is a process flow diagram illustrating a cell processing step.

3 is a plan view showing an array substrate for a liquid crystal display according to the present invention.

4 is an enlarged plan view of a portion A in Fig. 3;

5 is a cross-sectional view taken along the line V-V in Fig.

FIGS. 6A to 6D are process cross-sectional views taken along the line V-V in FIG.

7A to 7D are cross-sectional views of the thin film transistor section corresponding to the array region, which are cut along the process sequence.

Description of the Related Art [0002]

100: Mosquito board

140a, 140b, 140c, 140d, 140e: first to fifth semiconductor patterns

150: gate pattern 150a: gate pattern vertical section

150b: gate pattern horizontal part 150c to 150g: 1a to 5a Lightning rod

150h to 150l: 1st to 5b lightning rods

D1, D2, D3, D4, D5: first to fifth detection areas

GH: Gate hole 180: Test pattern

NAA: Bare Ray region

Claims (16)

A mother board divided into an array area and a via area; An array element configured corresponding to the array area on the mother substrate; And a plurality of test patterns inserted in an electrically insulated state so as to detect the occurrence of static electricity corresponding to the via-lay region on the mother substrate and the amount of static electricity generated in each step of the array element, The plurality of test patterns may include first and second semiconductor patterns formed in a state of being spaced apart from each other along a lateral direction and a gate pattern formed to overlap both edges of the first and second semiconductor patterns with a gate insulating film therebetween ≪ / RTI & The semiconductor device according to claim 1, wherein the gate pattern comprises first to second lightning arresters positioned along the lateral direction so as to overlap one edge of each of the first and second semiconductor patterns, And first and second lightning rods positioned to overlap with the other edge of each of the first semiconductor pattern and the second semiconductor pattern. The method according to claim 1, Wherein the plurality of test patterns are designed to correspond to the via-lay regions surrounding the four sides of the array region, respectively. The method according to claim 1, Wherein the plurality of test patterns further include third to fifth semiconductor patterns formed in a state of being spaced apart from each other, The gate pattern further includes third to fifth contactors respectively corresponding to the third to fifth semiconductor patterns and third and fifthb lightning conductors having different distances from the third and fiftha lightning arresters, The first to fifth semiconductor patterns are formed of the same material as the semiconductor layer, and the gate pattern is formed of the same material as the gate wiring and includes a gate hole exposing a part of the gate pattern Wherein the first and second connection terminals are connected to each other. The method of claim 3, Wherein the gate pattern includes a vertical portion vertically branched to both sides, a horizontal portion connecting the vertical portions on both sides from the upper side and the lower side, and the 1a through 5aa lightning rods vertically branched from each other in the horizontal portion, 1b to 5b lightning arresters. 5. The method of claim 4, The first to fifth resistive elements and the first to fifth resistive elements further include first to fifth detection regions superimposed on the first to fifth semiconductor patterns with the gate insulating film interposed therebetween, Display array motherboard. 6. The method of claim 5, Wherein the first to fifth detection areas are regions for detecting the amount of static electricity generated in the process of forming the array device in stages. 6. The method of claim 5, In the test pattern, the first detection region is 1 kV, the second detection region is 2 kV, the first detection region is 2 kV, the second detection region is 2 kV, Wherein the gate insulating film corresponding to each of the third detection region, the fourth detection region, and the fifth detection region is set to break when an electrostatic voltage of 3 kV is applied to the third detection region, 4 kV is applied to the fourth detection region, and 5 kV is applied to the fifth detection region. 3. The method of claim 2, Wherein the first to fifth semiconductor patterns are formed of a single layer made of polycrystalline silicon or an amorphous silicon containing pure amorphous silicon and an impurity in this order. Preparing a mother board divided into an array area and a via area; An array element corresponding to the array area on the mother substrate; a plurality of electrically insulated test patterns for detecting presence or absence of static electricity corresponding to the via array area and an amount of static electricity generated at each step of the array element; , ≪ / RTI > Wherein forming the test pattern comprises: Forming first and second semiconductor patterns spaced apart from each other along a lateral direction in a via-lay region on the mother substrate; Forming a gate insulating film on the first and second semiconductor patterns; And forming an electrically insulated gate pattern on the gate insulating film, Wherein forming the gate pattern comprises: First and second lightning arresters positioned along a lateral direction so as to overlap with one edge of each of the first and second semiconductor patterns; a first and a second lightning arresters having different distances from each other, And forming the first and second light-emitting rods to overlap with the other edge of each of the semiconductor patterns. 10. The method of claim 9, Wherein forming the test pattern comprises: Third and fifth semiconductor patterns spaced apart from each other at the time of forming the first and second semiconductor patterns are formed Forming an interlayer insulating film including a gate hole exposing a part of the gate pattern on the gate pattern, Wherein forming the gate pattern comprises: Further comprising the steps of forming third through fifth semiconductor light-emitting elements, third through fifth semiconductor light-emitting elements, and third and fourth light-emitting arrays respectively having different distances from the third and fifth semiconductor light- Wherein the step of forming the mother substrate comprises the steps of: 11. The method of claim 10, Wherein the plurality of test patterns are formed corresponding to the via-lay regions surrounding the four sides of the array region, respectively. Claim 12 is abandoned in setting registration fee. 11. The method of claim 10, Wherein the gate pattern includes a vertical portion vertically branched to both sides, a horizontal portion connecting the vertical portions on both sides from the upper side and the lower side, and the first through fifth light- 1b to 5b lightning rods. 5. A method of manufacturing an array mother board for a liquid crystal display device, comprising the steps of: Claim 13 has been abandoned due to the set registration fee. 13. The method of claim 12, The first to fifth resistive elements and the first to fifth resistive elements further include first to fifth detection regions superimposed on the first to fifth semiconductor patterns with the gate insulating film interposed therebetween, A method for manufacturing an array mother substrate. Claim 14 has been abandoned due to the setting registration fee. 14. The method of claim 13, Wherein the first to fifth detection regions are regions for detecting the amount of static electricity generated in the process of forming the array elements in steps of the array. Claim 15 is abandoned in the setting registration fee payment. The method according to claim 9 or 13, In the test pattern, the first detection region is 1 kV, the second detection region is 2 kV, the first detection region is 2 kV, the second detection region is 2 kV, Wherein the gate insulating film corresponding to each of the third detection region, the fourth detection region, and the fifth detection region is set to be broken when an electrostatic voltage of 3 kV, 4 kV, and 5 kV is applied to the third detection region, Gt; Claim 16 has been abandoned due to the setting registration fee. 11. The method of claim 10, Wherein the first to fifth semiconductor patterns are formed of a single layer of polycrystalline silicon or an amorphous silicon layer of pure amorphous silicon and impurities.

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