WO2019010753A1

WO2019010753A1 - Goa test circuit and goa test method

Info

Publication number: WO2019010753A1
Application number: PCT/CN2017/098257
Authority: WO
Inventors: 吕晓文
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2017-07-12
Filing date: 2017-08-21
Publication date: 2019-01-17
Also published as: CN107221274A; CN107221274B

Abstract

A GOA test circuit comprises a first wiring (31) arranged outside an area where a plurality of display panels (40) are located, a second wiring (32) located between two adjacent areas, and a switch unit (33) arranged between the first wiring (31) and each second wiring (32), wherein the areas are obtained by dividing the area where the plurality of display panels (40) are located; when the switch unit (33) is switched off, an Array test signal can be only applied to one side of a display panel (40); and when the switch unit (33) is switched on, an HVA Curing process signal can be applied to two sides of the display panel (40). Further disclosed is a GOA test method. The test circuit and the test method can not only realize single-side driving of an Array test, but can also realize dual-side driving of an HVA Curing process.

Description

GOA test circuit and GOA test method

【技术领域】[Technical Field]

The present invention relates to the field of liquid crystal display technology, and in particular to a GOA (Gate Driver on Array, Array substrate row drive) test circuit and GOA test method.

【背景技术】【Background technique】

LCD (Liquid Crystal Display, based on GOA technology) The liquid crystal display has the advantages of simple process and low cost, and has gradually become a mainstream display device. In the production process, the LCD needs to set up the test circuit for Array test (array test) and HVA. Curing (High Vertical Alignment Curing) process.

In the current circuit design, please refer to Figure 1, Array test and HVA. The Curing process can share the peripheral traces 11, and a trace 12 is disposed in the middle of the adjacent two rows of display panels 10, and the traces 12 are not connected to the peripheral traces 11. By applying a driving signal to the trace 12 or the peripheral trace 11, each display panel 10 can receive the Array test signal only on one side of the display panel 10 through the Array test pad 13, that is, realize the unilateral driving of the Array test. And in HVA In the Curing process, a driving signal is applied to the peripheral traces 11. Each display panel 10 can receive a driving signal only on one side of the display panel 10 through the HVA Curing pad 14, that is, only HVA can be realized. One-sided drive for the Curing process. When the size of the display panel 10 is large or the size of the area where the plurality of display panels 10 are located is large, the line impedance and the RC (Resistance-Capacitance) load are heavy, and the drive signal transmission is more severely attenuated. The display panel 10 causes problems such as screen splitting or screen gradation.

In order to avoid this problem, the industry has proposed the circuit structure design shown in FIG. 2, and the two ends of the trace 12 are connected to the peripheral trace 11. When a driving signal is applied to the peripheral trace 11, each side of each display panel 10 can receive a driving signal to realize HVA. The bilateral drive of the Curing process. However, the circuit structure design cannot realize the unilateral driving of the Array test. When the driving circuit on the display panel 10 side cannot work normally, the driving circuit on the other side can still make the pixels of the display panel 10 normal under the control of the driving signal. Work, which leads to missed inspections.

【发明内容】 [Summary of the Invention]

In view of this, the present invention provides a GOA test circuit and a GOA test method, which can realize both the unilateral drive of the Array test and the HVA. The bilateral drive of the Curing process.

A GOA test circuit according to an embodiment of the present invention is configured to test a plurality of display panels arranged in an array, the GOA test circuit comprising:

The first trace is surrounded by the area where the plurality of display panels are located, and the Array test pad and HVA of each display panel Curing pad connection;

At least one second line parallel to the row direction, the area where the plurality of display panels are located is divided into at least two areas arranged in the column direction by at least one second line, and each second line is located in the adjacent two Array test pads and HVA between each of the regions, each of the second traces and the respective display panels on both sides thereof Curing pad connection;

a thin film transistor disposed between the first trace and each of the second traces for controlling the turn-on and turn-off of the first trace and each of the second traces, wherein each of the second traces A thin film transistor is disposed between the terminal and the first trace, and a source and a drain of the thin film transistor are respectively connected to the first trace and the second trace;

The third trace is connected to the gate of the thin film transistor.

The first trace is disposed outside the area where the plurality of display panels are located, and the Array test pad and HVA of each display panel Curing pad connection;

At least one second trace parallel to the first direction, the area where the plurality of display panels are located is divided into at least two regions arranged along the second direction by at least one second trace, wherein the second direction is opposite to the first One direction is perpendicular, and each second trace is located between two adjacent regions, each second trace and Array test pads and HVA of each display panel on both sides thereof Curing pad connection;

The switch unit is disposed between the first trace and each of the second traces for controlling the turn-on and turn-off of the first trace and each of the second traces.

A GOA test method for testing a plurality of display panels arranged in an array, the GOA test method includes:

Setting a first trace outside the area where the plurality of display panels are located, the first trace and the Array test pad and HVA of each display panel Curing pad connection;

Forming at least one second trace parallel to the first direction, the region of the plurality of display panels being divided by the at least one second trace into at least two regions arranged along the second direction, wherein the second direction is The first direction is perpendicular, and each second trace is located between two adjacent regions, and each second trace has an Array test pad and HVA of each display panel on both sides thereof Curing pad connection;

Forming a switching unit between the first trace and each of the second traces;

The switch unit disconnects the first trace and the second trace, and applies an Array test signal to the first trace and the second trace to perform Array test on the plurality of display panels;

The switch unit turns on the connection of the first trace and the second trace, and applies HVA to the first trace and the second trace Curing process signals to perform HVA Curing processes on multiple display panels.

Advantageous Effects: The present invention sets a first trace outside a region where a plurality of display panels are located, and divides a region where the plurality of display panels are located into at least two regions, and sets a second trace between adjacent two regions. And setting a switch unit between the first trace and each second trace. When performing the Array test, the switch unit is disconnected, and only the Array test signal can be applied to one side of the display panel, thereby implementing the Array test. Drive while driving HVA During the Curing process, the switch unit is turned on to apply HVA Curing process signals to both sides of the display panel, thereby achieving bilateral driving of the HVA Curing process.

【附图说明】 [Description of the Drawings]

1 is a schematic structural diagram of a GOA test circuit according to an embodiment of the prior art;

2 is a schematic structural diagram of a GOA test circuit according to another embodiment of the prior art;

3 is a schematic structural diagram of a GOA test circuit according to an embodiment of the present invention;

4 is a schematic flow chart of a GOA test method according to an embodiment of the present invention.

【具体实施方式】【Detailed ways】

The technical solutions of the various exemplary embodiments provided by the present invention are clearly and completely described in the following with reference to the accompanying drawings. The various embodiments described below and the features in the embodiments can be combined with one another without conflict.

FIG. 3 is a schematic structural diagram of a GOA test circuit according to an embodiment of the present invention. Referring to FIG. 3, the GOA test circuit of this embodiment includes a first trace 31, a second trace 32, and a switch unit 33 disposed between the first trace 31 and the second trace 32.

The first traces 31 are disposed outside the area where the plurality of display panels 40 are located. Specifically, the plurality of display panels 40 may be arranged in an array on a glass substrate, and the first traces 31 are formed on the glass substrate. The rectangular structure is closed and encircled around the area where the plurality of display panels 40 are located. The first trace 31 of this embodiment can be regarded as an Array test and an HVA. The peripheral traces shared by the Curing process are based on which the first traces 31 are connected to the Array test pads 41 and the HVA Curing pads 42 of each display panel 40.

The second trace 32 is parallel to the first direction (ie, the row direction) and is disposed within the area where the plurality of display panels 40 are located. Specifically, the area where the plurality of display panels 40 are located is divided into two areas arranged in a second direction (ie, column direction) perpendicular to the first direction, the two areas may be equal in size, and the second line 32 is located at Between these two areas. Of course, in this embodiment, the first direction is the column direction and the second direction is the row direction. At this time, the regions where the plurality of display panels 40 are located are divided into two regions arranged in the row direction, and the second trace 32 is Parallel to the column direction. With continued reference to FIG. 3, the second trace 32 and the Array test pads 41 and HVA of the respective display panels 40 on either side thereof Curing pads 42 are all connected.

The switch unit 33 is disposed between the first trace 31 and the second trace 32 for controlling conduction and disconnection between the first trace 31 and the second trace 32. Specifically, a switch unit 33 is disposed between the two ends of the second trace 32 and the first trace 31. The switch unit 33 can be disposed outside the area where the plurality of display panels 40 are located, or disposed adjacent to the two Between the above areas. Moreover, in an embodiment of the invention, the switching unit 33 can be a thin film transistor (Thin Film Transistor, TFT), the source and the drain of the thin film transistor are respectively connected to the first trace 31 and the second trace 32. In order to control the on and off of the thin film transistor, the embodiment may be in two adjacent regions. The third trace 34 is disposed to connect the gate of the thin film transistor to the third trace 34, and a control signal is applied to the third trace 34 to turn on and off the thin film transistor. The gates of the two thin film transistors connected to the same second trace 32 may be connected to the same third trace 34, and the third trace 34 may be parallel to the second trace 32, of course, the same second walk. The gates of the two thin film transistors connected by the line 32 may also be connected to a third trace 34, respectively. It should be noted that the third trace 34 of the embodiment and the Array test pads 41 and HVA of the respective display panels 40 are required. There is no connection between the Curing pads 42.

When the Array test is performed on the plurality of display panels 40, the present embodiment applies a low level signal to the third trace 34, and the thin film transistor is turned off, that is, the switch unit 33 turns off the first trace 31 and the second trace 32. The connection between the two. At this time, by applying an Array test signal to the first trace 31 or the second trace 32, each display panel 40 can receive an Array test signal by setting an Array test pad 41 on one side (upper or lower side) thereof. That is, the Array test signal is received only on one side, thereby implementing the unilateral drive of the Array test.

Performing HVA on a plurality of display panels 40 In the Curing process, the present embodiment applies a high level signal to the third trace 34, and the thin film transistor is turned on, that is, the switch unit 33 turns on the connection between the first trace 31 and the second trace 32. At this time, the first trace 31 and the second trace 32 form a closed loop circuit, and HVA is applied to the first trace 31 or the second trace 32. Curing process signals, each display panel 40 can receive HVA Curing process signals by setting HVA Curing pads 42 on both sides (upper side and lower side), that is, receiving HVA on both sides thereof Curing the process signal to achieve a bilateral drive for the HVA Curing process.

It can be seen that this embodiment can implement the unilateral driving of the Array test, avoid the missed detection problem caused by the bilateral driving of the Array test, and can realize the HVA. The bilateral drive of the Curing process avoids problems such as screen splitting or screen gradation on the display panel 40.

It should be understood that, in other embodiments of the present invention, the area where the plurality of display panels 40 are located may be divided into two or more areas, and is not limited to the two areas shown in FIG. 1 above, correspondingly, the GOA test circuit Two or more second traces 32 may be included, and only one switch unit is disposed at each end of each of the second traces 32, and the first trace 31 and each of the second traces 32 are controlled by the switch unit. Between the conduction and disconnection, the present invention can simultaneously realize the unilateral driving and HVA of the Array test. The bilateral drive of the Curing process.

4 is a schematic flow chart of a GOA test method according to an embodiment of the present invention. Referring to FIG. 4, the GOA test method of this embodiment may include the following steps S41 to S45.

S41: setting a first trace outside the area where the plurality of display panels are located, the first trace and the Array test pad and HVA of each display panel Curing pad connections.

S42: forming at least one second trace parallel to the first direction, where the plurality of display panels are divided by at least one second trace into at least two regions arranged along the second direction, wherein the second direction is The first direction is perpendicular, and each second trace is located between two adjacent regions, each second trace and an Array test pad and HVA of each display panel on both sides thereof Curing pad connections.

S43: forming a switching unit between the first trace and each of the second traces.

S44: The switch unit disconnects the first trace and the second trace, and applies an Array test signal to the first trace and the second trace to perform Array test on the plurality of display panels.

S45: The switch unit turns on the connection of the first trace and the second trace, and applies HVA to the first trace and the second trace Curing process signals to perform HVA Curing processes on multiple display panels.

Wherein, steps S41 to S43 can be regarded as forming the GOA test circuit shown in FIG. 1, and steps S44 and S45 can be regarded as performing Array test and HVA on the GOA test circuit respectively. Curing process. The principle and process of the GOA test method can be referred to the description of the embodiment shown in FIG. 1, so the GOA test method has the same beneficial effects.

It should be understood that the above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention, the equivalent structure or equivalent process transformations, such as the techniques between the embodiments, using the present specification and the drawings. The combination of features, or directly or indirectly, in other related technical fields, is equally included in the scope of patent protection of the present invention.

Claims

An array substrate row driving GOA test circuit for testing a plurality of display panels arranged in an array, wherein the GOA test circuit comprises:

a first trace surrounding the area where the plurality of display panels are located, and an Array test pad and a high vertical alignment HVA of each of the display panels Curing pad connection;

At least one second trace parallel to the row direction, the region of the plurality of display panels being divided by the at least one second trace into at least two regions arranged in a column direction, each of the second traces Between the two adjacent regions, each of the second traces and the Array test pads and HVA of each of the display panels on both sides thereof Curing pad connection;

a thin film transistor disposed between the first trace and each of the second traces for controlling conduction and disconnection of the first trace and each of the second traces, wherein One thin film transistor is disposed between both ends of each of the second traces and the first trace, and a source and a drain of the thin film transistor are respectively connected to the first trace and the The second trace;

The third trace is connected to the gate of the thin film transistor.
The GOA test circuit according to claim 1, wherein the thin film transistor is disposed outside a region where the plurality of display panels are located or between two adjacent regions.
An array substrate row driving GOA test circuit for testing a plurality of display panels arranged in an array, wherein the GOA test circuit comprises:

a first trace disposed outside the area where the plurality of display panels are located, and an Array test pad and a high vertical alignment HVA with each of the display panels Curing pad connection;

At least one second trace parallel to the first direction, the region of the plurality of display panels being divided by the at least one second trace into at least two regions arranged along the second direction, wherein the second direction And perpendicular to the first direction, and each of the second traces is located between two adjacent regions, each of the second traces and each of the display panels on both sides thereof Array test pad and HVA Curing pad connection;

And a switching unit disposed between the first trace and each of the second traces for controlling conduction and disconnection of the first trace and each of the second traces.
The GOA test circuit according to claim 3, wherein said switching unit comprises a thin film transistor, said GOA test circuit further comprising a third trace between adjacent two of said regions, said gate of said thin film transistor The pole, the source and the drain are connected to the third trace, the first trace and the second trace, respectively.
The GOA test circuit according to claim 4, wherein the thin film transistor is disposed outside a region where the plurality of display panels are located or between two adjacent regions.
The GOA test circuit according to claim 3, wherein the first trace is disposed around the area where the plurality of display panels are located, and both ends of each of the second traces are separated from the first trace One of the switching units is disposed between the lines.
The GOA test circuit according to claim 3, wherein one of the first direction and the second direction is a row direction and the other is a column direction.
An array substrate row driving GOA testing method for testing a plurality of display panels arranged in an array, wherein the GOA testing method comprises:

Providing a first trace outside the area where the plurality of display panels are located, the first trace and the Array test pad of each display panel and the high vertical alignment HVA Curing pad connection;

Forming at least one second trace parallel to the first direction, the region of the plurality of display panels being divided by the at least one second trace into at least two regions arranged along the second direction, wherein the second The direction is perpendicular to the first direction, and each of the second traces is located between two adjacent regions, each of the second traces and each of the display panels on both sides thereof Array Test Pad and HVA Curing pad connection;

Forming a switching unit between the first trace and each of the second traces;

The switch unit disconnects the first trace and the second trace, and applies an Array test signal to the first trace and the second trace to face the plurality of display panels Perform an Array test;

The switch unit turns on the connection of the first trace and each of the second traces, and applies HVA to the first trace and the second trace Curing a process signal to perform an HVA Curing process on the plurality of display panels.
The GOA testing method according to claim 8, wherein the switching unit comprises a thin film transistor, a source and a drain of the thin film transistor are respectively connected to the first trace and the second trace, The GOA test method also includes:

Forming a third trace between two adjacent regions, and the third trace is connected to a gate of the thin film transistor;

The switch unit disconnects the first trace and the second trace, including:

Applying a low level signal to the third trace;

The switching unit turns on the connection of the first trace and the second trace, including:

A high level signal is applied to the third trace.
The GOA testing method according to claim 9, wherein the thin film transistor is disposed outside a region where the plurality of display panels are located or between two adjacent regions.
The GOA testing method according to claim 8, wherein the first trace is disposed around the area where the plurality of display panels are located, and both ends of each of the second traces are separated from the first One of the switching units is disposed between the lines.
The GOA testing method according to claim 8, wherein one of the first direction and the second direction is a row direction and the other is a column direction.