KR101010470B1 - Array substrate for LCD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same, which can improve the detection reliability of a defect due to a wiring short circuit inside an array substrate.

The present invention improves detection power when disconnection occurs in a liquid crystal panel by lowering the wiring resistance by using a low resistance wire in which the high resistance of the MPS data inspection wiring is formed in the MPS test of the array substrate of the liquid crystal display device. .

In addition, defect outflows to subsequent processes are reduced, increasing production efficiency, reducing costs and improving product reliability.

MPS, MPS Test, Liquid Crystal Panel, Low Resistance Wiring

Description

Array substrate for liquid crystal display device

1 is a plan view showing an array substrate constituting a conventional liquid crystal panel.

2 is a schematic view of one cell formed on a conventional large substrate.

3 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a pad part and a thin film transistor taken along the line AA ′ in FIG. 3.

5 is a plan view schematically illustrating an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention.

<Description of Signs of Major Parts of Drawings>

301 and 501 Liquid crystal panels 302 and 502 Gate wiring

303, 503: data wiring 311, 511: antistatic circuit

331, 531: MPS test pad 333, 433, 533: data pad

340, 540: second MPS data inspection wiring                 

341, 541: First MPS data inspection wiring

345: contact holes 350, 450, 550: outer guidelines

410: substrate 411: gate electrode

413a and 413b: source electrode and drain electrode

414 active layer 415 gate insulating film

416: protective film 417: pixel electrode

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same, which can improve the detection reliability of a defect due to a wiring short circuit.

BACKGROUND ART Liquid crystal display devices, which have recently been in the spotlight as flat panel display elements, have been actively studied due to their high contrast ratio, suitable for gray scale display and moving image display, and low power consumption.

In particular, the liquid crystal display can be manufactured with a thin thickness, so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and it is light in weight and consumes significantly less power than the CRT CRT. It is used as a display of a notebook computer, and is drawing attention as a next generation display device.

Such a liquid crystal display generally includes an array substrate having a thin film transistor and a pixel electrode formed in each pixel region defined by a gate wiring and a data wiring, a color filter substrate having a color filter layer and a common electrode formed therebetween, and interposed between the two substrates. The liquid crystal layer is configured to display an image by controlling an amount of light transmitted by applying a voltage to the electrode to rearrange the liquid crystal molecules of the liquid crystal layer.

At this time, the color filter substrate and the array substrate are bonded by a sealant such as an epoxy resin, and the driving circuit on the PCB (Printed Circuit Board) is connected to the thin film array substrate through a tape carrier package (TCP).

More specifically, the array substrate is divided into an active region and a pad portion region, and a plurality of gate wirings and data wirings are formed in the active region, and a thin film transistor is used as a switching element at the intersection of the gate wiring and the data wiring. (Thin Film Transistor) is formed.

Here, the gate pads extending from the gate lines and the data pads extending from the data lines are formed in the outer portion of the liquid crystal panel.

The array substrate thus constructed is subjected to a Mass Production System (MPS) test process to test for defects such as line defects and point defects before bonding to the color filter substrate.

In this case, each of the gate pads and the data pads is connected to an MPS test line for testing the liquid crystal panel for the MPS test process.

The MPS test test is performed in a form of determining whether a substrate is defective by using a value measured by applying a signal voltage through a shorting bar connected to a gate wiring of an active region and a shorting bar connected to a data wiring.

Hereinafter, a structure of an array substrate according to the prior art will be described with reference to the accompanying drawings.

FIG. 1 is a view showing a top view of a lower substrate constituting a conventional liquid crystal panel, and FIG. 2 is a view schematically showing one cell formed on a conventional large substrate.

As shown in FIG. 1, a plurality of unit liquid crystal panels A, B, C, D, E, and F are formed on the substrate 100.

Here, the color filter substrate and the array substrate constituting the liquid crystal panel are formed of a plurality of unit liquid crystal panels on a large glass substrate, and are usually formed four or six at the same time and then cut into each unit panel to improve the yield Promote.

In the liquid crystal display, when the fabrication of the array substrate including the thin film transistor is completed, the array substrate is subjected to the inspection step, that is, the MPS test process, before bonding to the color filter substrate on which the color filter is formed. Approach and inspect the panel at.

Therefore, part of the unit panels (A, C, E) and the remaining unit panels (B, D, E) are configured in the same form, so that the panel contact points for the MPS test are opposite to each other.

2 is a view schematically showing a unit panel configured in a conventional lower substrate.

As shown in FIG. 2, a plurality of gate lines 202 formed in parallel in the horizontal direction on the substrate 201, a plurality of data lines 203 formed in parallel in the vertical direction, and the data lines 203 A data pad 233 formed at an end thereof to apply an external signal to the data line 203, a first MPS data test line 241 connected to the data pad 233, and a second MPS data test line opposite to the data pad 233. 240 is included and formed.

Here, the first MPS data test line 241 and the second MPS data test line 240 are made of different materials, and in general, the first MPS data test line 241 is the same as the data pad 233. Material having a small resistance (about 100 Ω), and the second MPS data test line 240 is made of the same material as the pixel electrode made of a material such as indium tin oxide (ITO), and has a relatively large resistance (about several tens of kΩ). Has

At this time, an antistatic circuit 211 for preventing static electricity is formed at the end of the data line 203.

 Although not shown, a thin film transistor TFT is formed at a point where the gate line 202 and the data line 203 cross each other.

In addition, although only the MPS data test wirings 241 and 240 are shown in the drawing, the MPS gate test wiring for the gate wiring is also formed.

In addition, although not shown, the gate pad is formed at the end of the gate line for the MPS gate inspection line to apply an external signal to the gate line.

In addition, an MPS pad 231 is formed to perform an MPS test through the MPS data test line.

Here, in the case of the unit panels A, C, and E (shown in FIG. 1), the MPS test is performed using the first MPS data inspection wiring 241. In the case of the unit panels B, D, and F, the second MPS data inspection wiring is performed. At 240, the MPS test is made.

However, in the case of the first MPS data test wiring 241, a defect is easy to detect when data is opened due to a small resistance, but the test wiring itself is used in the MPS test using the second MPS data test wiring 240. Due to the large resistance of the data open voltage has a low drop in the data open detection ability has a problem.

That is, since the wiring resistance between cb is much larger than the wiring resistance between ab, when 25 V is applied to the MPS pad 231 at the point 'c', the voltage at the 'b' input terminal is kept at a substantially low potential, so Since the voltage difference between bd is not large, there exists a problem that a detection power falls.

Therefore, when the wiring is disconnected for a plurality of unit panels formed on one substrate, a difference occurs in the defect detection force.

SUMMARY OF THE INVENTION An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, in which a wiring structure is reduced by changing a wiring structure for an MPS test in a liquid crystal display device, thereby improving detection power during disconnection.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention comprises: gate wiring and data wiring crossing vertically and horizontally to define a pixel; A gate pad and a data pad extending from and connected to the gate wiring and the data wiring; And an MPS test wiring electrically connected to the gate pad and the data pad, wherein the MPS test wiring is overlapped with an outer guide line, and the MPS test wiring is superimposed on the outer pad. And a contact with the guide line in parallel.

The gate wiring material and the data wiring material are made of a metal selected from aluminum, aluminum alloy, chromium and molybdenum.

The MPS inspection wiring is made of a pixel electrode material.

The pixel electrode material is formed of any one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

The outer guide line is made of at least one material selected from aluminum, aluminum alloy, chromium, molybdenum.

The MPS inspection line and the outer guide line may be contacted by laser welding.

An inspection pad may be further formed at one end of the MPS inspection line.                     

Further, in order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention includes: gate wiring and data wiring crossing vertically and horizontally to define a pixel; A gate pad and a data pad extending from and connected to the gate wiring and the data wiring; And an MPS test wiring electrically connected to the gate pad and the data pad, wherein the MPS test wiring is formed by connecting the gate pad and the data pad to an outer guide line. It is done.

The MPS inspection wiring and the outer guide line are contacted by laser welding.

The MPS inspection wiring is made of a pixel electrode material.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 3, a plurality of gate lines 302 formed in parallel in the horizontal direction on the substrate 301, a plurality of data lines 303 formed in parallel in the vertical direction, and the data lines 303 A data pad 333 formed at an end thereof to apply an external signal to the data line 303, a first MPS data test line 341 connected to the data pad 333, and a second MPS data test line opposite to the data pad 333. 340 is included and formed.                     

Here, the first MPS data test wiring 341 and the second MPS data test wiring 340 are made of different materials, and in general, the first MPS data test wiring 341 is the same as the gate wiring and the data wiring. It is made of a material and has a small resistance (about 100 Ω), and the second MPS data test wiring 340 is made of the same material as the pixel electrode and has a relatively large resistance (about several tens of kΩ).

For example, the first MPS data test wiring 341 is made of aluminum alloy, and has a small resistance. The second MPS data test wiring 340 has indium tin oxide (ITO), indium zinc oxide (IZO), and ITZO. made of a transparent conductive material such as (indium tin zinc oxide).

At this time, in the present invention, low resistance is realized by connecting the second MPS data test wiring 340 by the outer guide line 350 made of an aluminum alloy and the contact hole 345.

Meanwhile, an antistatic circuit 311 for preventing static electricity is formed at the end of the data line 303.

 Although not shown, a thin film transistor is formed at a point where the gate line 302 and the data line 303 cross each other.

In addition, although only the MPS data test wiring is shown in the drawing, the MPS gate test wiring for short circuit inspection of the gate wiring is also formed.

Although not shown, a gate pad is formed at an end of the gate line for the MPS gate inspection line to apply an external signal to the gate line.

In addition, the first MPS data test line 341 and the second MPS data test line 340 have MPS pads 331 formed at one end thereof in order to perform an MPS test.

In the array substrate having such a structure, the second MPS data inspection wiring 340 contacts the outer guide line 350, which is a low resistance wiring such as aluminum alloy, so that the two wirings 340 and 350 form a parallel structure. Therefore, a relatively low resistance test wiring is achieved.

4 is a cross-sectional view illustrating a cross-sectional view of the pad portion taken along the line AA ′ in FIG. 3 and a structure of the thin film transistor.

As shown in FIG. 4, a gate pattern is formed by depositing and patterning a metal on the substrate 410 by sputtering.

The gate pattern includes a gate wiring and a gate electrode 411, a gate pad, and an MPS gate inspection wiring (not shown).

In this case, aluminum (Al), aluminum alloy, chromium (Cr) or molybdenum (Mo) is used as the metal.

Next, a gate insulating film 415 having a thickness of about 2000 μs is formed on the entire surface including the gate wiring, and an active layer 414 is deposited by depositing amorphous silicon (a-Si) on the gate insulating film 415 on the gate electrode 411. ).

Thereafter, a metal is deposited and patterned on the gate insulating layer 415 by sputtering to form a data pattern.

The data pattern includes a data line, a source, a drain electrode 413a and 413b, and a data pad 433.

In this case, aluminum (Al), aluminum alloy, chromium (Cr) or molybdenum (Mo) is used as the metal.

Subsequently, a low dielectric constant BCB (Benzocyclobutane), an acrylic resin, or the like is coated on the entire surface including the data pattern to form a protective film 416 having a predetermined thickness.

The pixel electrode 417 connected to the drain electrode 113b is formed on the entire surface including the passivation layer 416.

The pixel electrode 417 is made of a transparent conductive material, and may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or the like.

In this case, a second MPS data test line 440 is formed of a material forming the pixel electrode 417, and one side of the second MPS data test line 440 is electrically connected to the data pad 433. One side is connected to the MPS test pad 331.

Here, the second MPS data test line 440 contacts the outer guide line 450 formed on the outer side of the liquid crystal panel.

Since the second MPS data test wiring 440 is in contact with the outer guide line 450, which is a low resistance wire such as an aluminum alloy, a predetermined wire length is formed in a parallel structure, so that the second MPS data test wiring 440 is relatively large. ) Becomes the low resistance test wiring.

The array substrate completed through the manufacturing process as described above undergoes an inspection process step of checking defects occurring during the process and repairing the checked defects for normal operation of the device.

A plurality of liquid crystal panels configured as described above are formed in the same shape on a single large area substrate. Since the MPS test process is performed on both sides of the substrate, the liquid crystal panels located on one side of the substrate are tested by the first MPS data inspection wiring. The liquid crystal panels located on the other side of the substrate are tested by the second MPS data inspection wiring.

Therefore, in the case of the liquid crystal panel which performs the MPS test with the first MPS data inspection wiring, if a disconnection occurs between the data wirings in the liquid crystal panel, a high resistance is detected by the MPS inspection pad.

At this time, since the first MPS data test wiring is a low resistance wiring (wiring resistance of about 100 Ω) made of an alloy such as aluminum, a high resistance due to data open can be discriminated.

In addition, in the case of the liquid crystal panel which performs the MPS test with the second MPS data inspection wiring, when disconnection occurs between the data wirings in the liquid crystal panel, a high resistance is detected by the MPS inspection pad.

In this case, since the second MPS data test wiring is connected in parallel with the low resistance wiring and has a relatively small resistance (wiring resistance of about 4.8 kΩ), the high resistance due to data open can be detected with discrimination.

In the liquid crystal panel according to the present invention, the contact between the MPS data test wiring and the low resistance wiring may be made by laser welding, or may be formed by forming a contact hole using a mask pattern correction during the passivation process.

5 is a plan view schematically illustrating an array substrate of a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 5, the liquid crystal panel 501 includes a plurality of gate lines 502 formed in parallel in the horizontal direction on the array substrate, a plurality of data lines 503 formed in parallel in the vertical direction, and the data lines. A data pad 533 formed at an end of the 503 to apply an external signal to the data wire 503, a first MPS data test wire 541 connected to the data pad 533, and a second opposite to the data pad 533. The MPS data inspection wiring 540 is included and formed.

In this case, the second MPS data test line 540 implements low resistance by using the outer guide line 550 made of aluminum alloy, and the data pad 533 and the outer guide line 550 are made of pixel electrode material. Are contacted and connected.

The outer guide line 550 and the MPS test pad 531 are also contacted and connected to the pixel electrode material.

Meanwhile, an antistatic circuit 511 for preventing static electricity is formed at the end of the data line 503.

The array substrate having the above structure has a relatively low resistance test wiring because the second MPS data test wiring 540 uses the outer guide line 550 which is a low resistance wire such as aluminum alloy (AlNd).

 Although the present invention has been described in detail with reference to specific examples, this is for describing the present invention in detail, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto, and the technical concept of the present invention is defined. It will be apparent to those skilled in the art that modifications and variations are possible.

The present invention improves detection power when a disconnection occurs in a liquid crystal panel by lowering wiring resistance by using a low resistance wiring in which the high resistance of the MPS data inspection wiring is pre-formed during the MPS test of the array substrate of the liquid crystal display device. Since the outflow of defects to the post-process is reduced, it has the effect of increasing the production efficiency, reducing the cost, and improving the reliability of the product.

Claims (10)

Gate wiring and data wiring crossing vertically and horizontally to define a pixel; A gate pad and a data pad extending from and connected to the gate wiring and the data wiring; In the outer portion of the array substrate for a liquid crystal display device comprising a; MPS (Mass Production System) test wiring electrically connected to the gate pad, the data pad, The MPS inspection wiring is overlapped with the outer guide line, and the MPS inspection wiring is contacted in parallel with the outer guide line. The MPS inspection line is formed of a material forming a pixel electrode, and the outer guide line is formed of a material forming the data pad and the data line. And the MPS inspection wiring and the outer guide line are contacted by laser welding. The method of claim 1, And the gate wiring material and the data wiring material are made of a metal selected from aluminum, aluminum alloy, chromium, and molybdenum. delete The method of claim 1, The pixel electrode material is any one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The method of claim 1, The outer guide line is at least one material selected from aluminum, aluminum alloy, chromium, molybdenum array substrate for a liquid crystal display device. delete The method of claim 1, And an inspection pad is further formed at one end of the MPS inspection line. Gate wiring and data wiring crossing vertically and horizontally to define a pixel; A gate pad and a data pad extending from and connected to the gate wiring and the data wiring; In the outer portion of the array substrate for a liquid crystal display device comprising a; MPS (Mass Production System) test wiring electrically connected to the gate pad, the data pad, The MPS test wiring is made by connecting a gate pad and a data pad to an outer guide line, The MPS inspection line is formed of a material forming a pixel electrode, and the outer guide line is formed of a material forming the data pad and the data line. And the MPS inspection wiring and the outer guide line are contacted by laser welding. delete delete

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