KR20030058085A - Thin Film Array Substrate And Method For Fabricating The Same - Google Patents

Abstract

PURPOSE: A thin film array substrate and a method for fabricating the same are provided to remove ITO on intersecting portions between shorting bars or shorting bar portions for resolving the short among the shorting bars by the ITO when static electricity occurs. CONSTITUTION: A thin film array substrate includes gate and data wires defining pixel areas on a glass substrate(110), first and second shorting bars respectively connected to odd-numbered data wires and even-numbered data wires, the first and second shorting bars being insulated from each other, third and fourth shorting bars(131c,131d) respectively connected to odd-numbered gate wires and even-numbered gate wires, the first and second shorting bars being insulated from each other, a protecting film formed on the entire surface including the data wires, and a transparent conductive film selectively formed on the protecting film except intersecting portions between the shorting bars or the shorting bar portions.

Description

Thin Film Array Substrate And Method For Fabricating The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a thin film array substrate for preventing a short circuit caused by static electricity and a method of manufacturing the same.

BACKGROUND ART Liquid crystal display devices, which have recently been spotlighted as flat panel display devices, have been actively researched due to their high contrast ratio, suitable for gradation display or moving picture display, and low power consumption.

In particular, it can be manufactured with a thin thickness so that it can be used as an ultra-thin display device such as a wall-mounted TV in the future, and is light in weight and consumes significantly less power than a CRT CRT. It is being used as a next generation display device.

Such a liquid crystal display device generally includes a thin film array substrate having a thin film transistor and a pixel electrode formed in each pixel region defined by gate wiring and data wiring, a color filter substrate having a color filter layer and a common electrode formed therebetween, It is composed of an interposed liquid crystal layer, by applying a voltage to the electrode to rearrange the liquid crystal molecules of the liquid crystal layer to adjust the amount of light transmitted to display an image.

At this time, the color filter substrate and the thin film array substrate are bonded by a sealant such as an epoxy resin, and the driving circuit on the printed circuit board (PCB) is connected to the thin film array substrate through a tape carrier package (TCP).

Specifically, the thin film array substrate is divided into an active region and a pad portion region, and a plurality of gate lines and data lines are formed on the glass substrate in the active area, and a switching element is formed at the intersection of the gate lines and the data lines. As a thin film transistor (Thin Film Transistor) is formed.

In the pad region, a gate driver for applying a gate driving signal to the active region and a source driver for applying signal data to the active region are formed.

The gate driver sequentially applies a scan signal to a plurality of gate lines arranged in the active region, and the source driver applies a signal voltage through the data line.

When the thin film transistor connected to the gate line receiving the scan signal from the gate driver is turned on, the signal voltage applied from the source driver is transferred to each pixel electrode to display an image.

The gate driver includes a gate pad extending from the gate line, and the source driver includes a data pad extending from the data line.

Each gate pad and data pad is connected to a mass production system line for a test.

The thin film array substrate configured as described above undergoes a Mass Production System (MPS) test process to test defects such as line defects and point defects before bonding to the color filter substrate.

The test test is performed by applying a signal voltage through a shorting bar connected to the gate wiring of the active region and a shorting bar connected to the data wiring to determine whether the substrate is defective.

Hereinafter, a structure of a thin film array substrate according to the prior art will be described with reference to the accompanying drawings.

1A is a top view of a conventional thin film array substrate designed to perform an MPS test.

FIG. 2 is a cross-sectional view illustrating a cutting line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view of a liquid crystal display for explaining a problem of the prior art.

As shown in FIG. 1, the thin film array substrate is divided into an active region including a gate wiring 11 and a data wiring 13 and a pad portion region connected to the gate pad 12 and the data pad 14. The shorting bar for the MPS test is connected to the ends of the gate pad 12 and the data pad 14.

1 illustrates first and second shorting bars 31a and 31b connected to the data pad 14 and third and fourth shorting bars 31c and 31d connected to the gate pad 12.

The first shorting bar 31a is connected to the odd-numbered data lines, the second shorting bar 31b is connected to the even-numbered data lines, and the third shorting bar 31c. Is connected to the odd-numbered (ODD) -th gate lines, and the fourth shorting bar 31d is connected to the even-numbered (EVEN) -th gate lines.

In this case, the first and second shorting bars 31a and 31b are connected to the first and second test pads 33a and 33b and the third and fourth shorting bars 31c and 31d are tested. The pads are connected to 33c and 33d, and the first, second, third and fourth test pads 33a, 33b, 33c and 33d are formed at the edges of the thin film array substrate.

The first and third shorting bars 31a and 31c are formed at the same time as the data line, and the second and fourth shorting bars 31b and 31d are formed at the same time as the gate line.

Accordingly, the third shorting bar 31c and the gate pad 12 are connected through the insulating film therebetween, and the second shorting bar 31b and the data pad 14 are connected through the insulating film therebetween.

At this time, the insulating film is a gate insulating film 15, as shown in FIG.

Hereinafter, a method of testing a defect of a thin film array substrate using an MPS tester will be described.

The MPS tester has a structure in which a transparent electrode and a liquid crystal layer are formed below the first test pad 33a and the third test formed at the ends of the first shorting bar 31a and the third shorting bar 31c. When the MPS tester is connected to the pad 33c, the MPS tester and the thin film array substrate are configured as one liquid crystal display device to drive the liquid crystal between the pixel electrode of the thin film array substrate and the transparent electrode of the MPS tester.

Thus, defects such as line defects and point defects of the pixel defined by the odd-numbered gate lines and the odd-numbered data lines are tested.

The line defect and point defect defects of the pixel defined by the even-numbered gate line and the even-numbered data line are also tested in the same manner.

However, when static electricity occurs during the process of the thin film array substrate, a portion vulnerable to the electrostatic response, that is, a portion where the first shorting bar 31a and the second shorting bar 31b intersect, and the third shorting bar 31c and the third shorting bar 31c are formed. Sparks occur at portions where the shorting bars 31d intersect, and as shown in FIG. 3, the gate insulating layer 15 and the protective layer 16 are destroyed, and different layers are formed by the upper ITO 17. The shorting bar in the shot is shortened.

The ITO 17 is a material used to form the pixel electrode of the active region, and is further formed on the protective layer 16 on the shorting bar to prevent the shorting bar of the pad region from being eroded by the ITO etchant. .

However, since the protective film is formed on the shorting bar, the shorting bar is not eroded by the ITO etchant. In addition, indirect shorting due to ITO in the part where the insulating film is destroyed is more important than the shorting problem caused by the static electricity generation itself. Is even more serious.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a thin film array substrate and a method of manufacturing the same, which removes ITO at a portion where the shorting bar intersects and prevents a shot at a portion where an insulating film is destroyed by static electricity. There is a purpose.

1A is a plan view of a conventional thin film array substrate designed to perform an MPS test.

FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1; FIG.

3 is a cross-sectional view of a liquid crystal display device for explaining the problems of the prior art.

4A to 4D are cross-sectional views of manufacturing processes of the liquid crystal display device according to the present invention.

* Explanation of symbols on the main parts of the drawings

110: glass substrate 111a: gate electrode

113a: source electrode 113b: drain electrode

114: active layer 115: gate insulating film

116: protective film 117: pixel electrode

118: pixel electrode 131c: third shorting bar

131d: fourth shorting bar

The thin film array substrate of the present invention for achieving the above object is connected to the gate line and the data line and the first shorting bar and the even-numbered data line connected to the odd-numbered data line to cross the horizontally and horizontally to define the pixel. And a second shorting bar insulated from the first shorting bar, a third shorting bar connected to the odd-numbered gate wires, a fourth shorting bar connected to the even-numbered gate wires and insulated from the third shorting bar, and the data wires. And a transparent conductive film selectively formed on an upper portion of the protective film except for a portion in which the shorting bar intersects or a portion in which the shorting bar is formed.

And, the manufacturing method of the thin film array substrate according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are cross-sectional views of the manufacturing process of the liquid crystal display device according to the present invention.

As described above, the liquid crystal display device includes a color filter substrate on which a color filter layer for color realization is formed, a thin film array substrate on which a switching element capable of changing the arrangement direction of liquid crystal molecules, and a liquid crystal layer formed between the two substrates. As a result, looking at the manufacturing method of the thin film array substrate corresponding to the antistatic more effectively as follows.

First, as shown in FIG. 4A, a gate pattern is formed by depositing and patterning a metal on the glass substrate 110 divided into an active region and a pad portion region by sputtering.

The gate pattern includes a gate line and a gate electrode 111a formed in an active region, a gate pad and a shorting bar formed in a pad portion region.

The shorting bar may be formed by dividing the second shorting bar connected to the even-numbered data pad in the source driver and the fourth shorting bar connected to the even-numbered gate pad in the gate driver (see FIG. 1).

In this case, aluminum, aluminum alloy, chromium or molybdenum is used as the metal.

Next, silicon nitride, which is an inorganic material having good dielectric breakdown characteristics, is deposited on the entire surface including the gate wiring by PECVD to form a gate insulating film 115 having a thickness of 2000 kV, and polycrystalline on the gate insulating film 115 on the gate electrode 111a. Silicon (a-Si) is deposited to form an active layer 114.

Thereafter, as illustrated in FIG. 4B, a metal pattern is deposited and patterned on the gate insulating layer 115 by sputtering to form a data pattern.

The data pattern includes data lines and source / drain electrodes 113a and 113b formed in the active region, and data pads and shorting bars formed in the pad portion region.

The shorting bar may be divided into a first shorting bar connected to an odd data pad in a source driver and a third shorting bar connected to an odd gate pad in a gate driver (see FIG. 1).

In this case, aluminum, aluminum alloy, chromium or molybdenum is used as the metal.

Therefore, in the source driver, the first shorting bar and the second shorting bar are insulated by the gate insulating film and intersect at a predetermined position. In the gate driver, the third shorting bar 131c and the fourth shorting bar 131d are connected to the gate insulating film 115. Are insulated by and crossed at a predetermined position.

The intersection of these shorting bars becomes a vulnerable part when static electricity is generated.

The odd-numbered gate pads and the third shorting bar in the different layers are connected through the gate insulating film, and the even-numbered data pads and the second shorting bars in the different layers are also connected through the gate insulating film.

On the other hand, the laminated film of the gate electrode 111a, the gate insulating film 115, the active layer 114, and the source / drain electrodes 113a and 113b formed in the active region becomes a thin film transistor.

Subsequently, as shown in FIG. 4C, a low dielectric constant BCB (Benzocyclobutane), an acrylic resin, or the like is applied to the entire surface including the data pattern to form a protective film 116 having a predetermined thickness, and the entire surface including the protective film 116. Indium Tin Oxide (ITO) is deposited on and patterned to form a pixel electrode 117 connected to the drain electrode 113b of the thin film transistor.

At this time, the portion where the shorting bars cross or the ITO deposited on the shorting bar is removed.

As a result, as shown in FIG. 4D, even if the insulating film, ie, the gate insulating film 115 and the protective film 116, is destroyed by the spark generated by static electricity at the portion where the shorting bar crosses, there is no ITO at the portion where the shorting bar crosses. It is possible to prevent the defect that the shorting bar is shortened by.

In the thin film array substrate formed as described above, when the thin film transistor is turned on by the scan signal applied from the gate driver, a signal voltage applied from the source driver is transferred to each pixel electrode to display an image.

Subsequently, a thin film array substrate is completed by detecting a defect such as a line defect or a point defect by applying a voltage to a test pad connected to each shorting bar in order to inspect the defect of the thin film array substrate.

The number of the shorting bars is not limited to the above embodiments, and various substitutions, modifications, and changes are possible to those skilled in the art to which the present invention pertains without departing from the technical spirit of the present invention. It will be obvious.

The method of manufacturing the thin film array substrate of the present invention as described above has the following effects.

That is, by eliminating the ITO formed at the intersection of the shorting bars or the top of the shorting bar, the shorting bar by the ITO is shortened when static electricity occurs.

Therefore, process yield can be improved by minimizing defects caused by static electricity.

Claims (7)

Gate wiring and data wiring crossing vertically and horizontally to define a pixel; A first shorting bar connected to the odd-numbered data line and a second shorting bar connected to the even-numbered data line and insulated from the first shorting bar; A third shorting bar connected to the odd-numbered gate line and a fourth shorting bar connected to the even-numbered gate line and insulated from the third shorting bar; A protective film formed on an entire surface including the data line; And a transparent conductive film selectively formed on an upper portion of the protective film except for a portion where the shorting bars cross or a portion where the shorting bar is formed. The thin film array substrate of claim 1, wherein the first shorting bar and the second shorting bar cross each other. The thin film array substrate of claim 1, wherein the third shorting bar and the fourth shorting bar intersect each other. Forming a gate wiring on the substrate; Forming a data line insulated from the gate line; Forming at least one shorting bar selectively connected to the gate wiring; Forming at least one shorting bar selectively connected to the data line; Forming a protective film on the entire surface including the data line; Forming a transparent conductive film on the protective film; And forming a pixel electrode by patterning the transparent conductive layer, and removing the portion of the shorting bar crossing the transparent conductive layer or the upper portion of the shorting bar. The method of claim 4, wherein the shorting bar is formed at the same time as the gate line or the data line. The method of claim 4, wherein the transparent conductive film is ITO. The method of claim 4, further comprising forming a thin film transistor connected to the pixel electrode at an intersection point of the gate line and the data line.