KR20040060044A - Lcd and method for manufacturing lcd - Google Patents

Abstract

PURPOSE: A liquid crystal display and a manufacturing method thereof are provided to check contact badness of a pad pattern contacted with a gate pad and a data pad as well as disconnection of a line and badness of a TFT(Thin Film Transistor) and a pixel electrode. CONSTITUTION: The first shorting bar(200) and the second shorting bar(100) are separately arranged at the outline of a gate pad and a data pad. Contact holes are formed at the gate pad(115), the first shorting bar(200) and the second shorting bar(100) facing with the data pad. A gate pad pattern(110) and a data pad pattern are arranged with a bridge type by interposing an insulation film. The first shorting bar(200) is connected with even number of gate pads(115) and data pads by pad patterns, respectively. The second shorting bar(100) is connected with odd number of gate pads(115) and data pads by pad patterns, respectively.

Description

Liquid crystal display and its manufacturing method {LCD AND METHOD FOR MANUFACTURING LCD}

The present invention relates to a liquid crystal display device and a method of manufacturing the same. More specifically, in the TFT defect inspection process after the array process of the liquid crystal display device, the electrical contact with the pad patterns formed on the pads can be inspected. The present invention relates to a liquid crystal display device and a manufacturing method thereof.

Among the screen display devices that display image information on the screen, CRT displays (or Cathode Ray Tubes (CRTs)), which have been widely used so far, have been replaced with thin-film flat panel displays that can be easily used anywhere.

In particular, the liquid crystal display device is the product which is most active development research because the display resolution is superior to other flat-panel devices and the response speed is faster than that of the CRT when implementing a moving picture. In addition, array substrates using active elements such as thin film transistors as switching elements have been widely applied to liquid crystal displays and the like.

In general, a structure of an array substrate using a thin film transistor as a switching element has a plurality of gate bus lines formed in parallel in a horizontal direction on a transparent insulating substrate, and the plurality of data bus lines are vertically intersected and arranged in a unit pixel region in a matrix form. Qualify them.

Gate pads and data pads are disposed at edges of the gate bus line and the data bus line, so that driving signals and graphic signals applied from an external PCB can be applied.

A thin film transistor, which is a switching element, is disposed on a region where the gate bus line and the data bus line are vertically intersected. The thin film transistor is a gate insulating film, a semiconductor layer, a source / source on a gate electrode drawn from the gate bus line. A drain electrode is formed and arranged.

As described above, the manufacturing process of the array substrate is manufactured using masks such as 4, 5, 6, and 7, and there is an inspection process to inspect the defects of the lines formed on the substrate according to the manufacturing process steps of the array substrate.

In particular, in the present invention, when the thin film transistor is completed and the pixel electrode is formed, defects in electrical contact between the pad patterns after the data pad and the gate pad are opened are examined.

1 is a diagram for describing a process of inspecting defects of pixels on an array substrate in general.

As shown in FIG. 1, when the array substrate and the color filter substrate are completed, a seal line is formed on the color filter substrate, the spacers are dispersed on the array substrate, and then bonded together with the liquid crystal layer interposed therebetween.

At this time, an array inspection process is performed for each progress of the process. When the TFT is completed, it is checked whether the TFT and the pixel electrode formed on the array substrate operate normally.

While contacting an area where the pad area is opened by a pin probe, a signal was applied to check for defects in the pixel area.

Recently, however, a defect inspection is performed using a shorting bar. In other words, the first shorting bar and the second shorting bar formed outside the pad region are even and the odd number of the gate pads G1, G2, G3 .... Gn or the data pads D1, D2, D3 ... Dn. Are connected along the first line, and a test signal is applied through each line.

The first shorting bar is connected to even-numbered lines of the gate pads G2, G4 and G6 .. and the data pads D2, D4 and D6 .. The second shorting bar is connected to the gate pad. G1, G3, G5 ..) and odd-numbered lines of the data pads D1, D3, D5 ..).

Thus, when a test signal is applied to the gate pads G2, G4, G6 .. and the data pads D2, D4, D6 .. connected to the first shorting bar, pixel electrodes corresponding to even-numbered lines are applied. And TFTs may be inspected for defects, and a test signal may be applied to the gate pads G1, G3, G5... And data pads D1, D3, D5 .. that are connected to the second shorting bar. In this case, it is possible to check whether the pixel electrode and the TFT corresponding to the odd-numbered lines are defective.

2 is a diagram illustrating a structure of a pad region when inspecting whether an array substrate is defective in a shorting bar form according to the related art.

As shown in FIG. 2, it can be seen that the first shorting bar 20 and the second shorting bar 10 are connected to the gate pads 15 alternately in even and odd numbers.

After the gate pad 15 is opened on the gate pad 15, when the pixel electrode is formed, a gate pad pattern 11 is formed to apply a driving signal to the gate pads 15 positioned below the substrate. It can be connected to the terminal.

When a test signal is applied to the first shorting bar 20, a signal is applied to the even-numbered gate pads 15 to pass through the gate pads 15 and are disposed in the active region. Turn on / off the sound.

Similarly, when a signal is applied to the second shorting bar 10 for a defect inspection, a signal is applied to the gate pads 11 corresponding to an odd number to drive the TFTs.

Although not shown in the drawing, the data pads are connected to the shorting bar in the same manner and a test signal is applied to check whether the pixel electrode is defective.

A plurality of contact holes formed on the gate pads may be in contact with the gate pad pattern and the metal layer.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

As shown in FIG. 3, the process of forming the A-A 'region of FIG. 2 is as follows.

First, a gate metal layer is deposited and etched on the transparent lower substrate 30 to form a gate bus line and a gate pad 15. Next, a gate insulating film 33 is coated on the lower substrate 30 on which the gate pad 15 is formed, and a protective film is coated on the gate insulating film 33. Then, when forming a contact hole for contact between the drain electrode of the TFT and the pixel electrode, a contact hole is formed in the gate pad region.

Therefore, contact holes 17 are formed in the gate insulating layer 33 while the protective layer applied on the gate pad 15 is removed. When an ITO metal film is deposited on a lower substrate on which the contact hole 17 is formed to form a pixel electrode, a gate pad pattern for electrical contact with the gate pad 15 is formed in an open area on the gate pad 15. 11) is formed.

Thus, it can be seen that the gate pad pattern 11 is electrically contacted with the gate pads 15 while being deposited along the contact hole 17 formed on the gate pad 15.

However, as shown in FIG. 3, when the gate insulating layer is not partially removed in the pad opening process, a problem occurs in that electrical contact between the gate pad patterns and the gate pads is difficult.

However, in order to inspect the defect of the TFT array substrate using the shorting bar described with reference to FIGS. 1 and 2, a signal is applied to the pad through the first shorting bar and the second shorting bar, and the signal does not pass through the gate pad pattern. However, since it is directly applied to the gate bus line through the gate pad, it is impossible to determine a defective contact with the gate pad pattern.

The present invention provides a liquid crystal display device capable of inspecting not only line breaks, TFT and pixel electrode defects, but also poor contact between the gate pad and the pad pattern in contact with the data pad when the array substrate defect inspection of the liquid crystal display device is performed. The purpose is to provide a method of manufacturing the same.

1 is a diagram for explaining a process of inspecting defects of pixels on an array substrate in general.

2 is a diagram illustrating a structure of a pad region when inspecting whether an array substrate is defective in a shorting bar form according to the related art.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

4 is a diagram illustrating a structure of a pad region for defect inspection of a liquid crystal display according to the present invention.

FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. 4. FIG.

* Description of the symbols for the main parts of the drawings *

100: second shorting bar 110: gate pad pattern

115: gate pad 117: contact hole

200: first shorting bar 300: insulating substrate

333: insulating film

In order to achieve the above object, the liquid crystal display device according to the present invention,

A plurality of gate bus lines and gate pads disposed on the transparent insulating substrate to apply driving signals;

A plurality of data bus lines and data pads arranged perpendicularly to the gate bus lines to define unit pixels and to apply graphic signals;

A thin film transistor which is a switching element disposed on an area in which the gate bus line and the data bus line are vertically intersected and arranged;

A pixel electrode electrically contacting the thin film transistor to form an electric field for twisting the liquid crystal;

A first shorting bar and a second shorting bar arranged to apply a signal during TFT inspection while preventing line breaks due to static electricity outside the gate pad and the data pads; And

Pad patterns disposed to electrically connect the first shorting bar, the even gate pad, and the data pad, and electrically connect the second shorting bar, the odd gate pad, and the data pad; Characterized in that it comprises a.

The gate pad, the data pads, the first shorting bar, and the second shorting bar may be spaced apart from each other without being directly connected, and the pad patterns may be electrically connected to each other by a contact hole formed in the first shorting bar and the second shorting bar. It is characterized by being connected.

In addition, the liquid crystal display device manufacturing method according to another embodiment of the present invention,

Forming a gate bus line, a gate pad, and a first shorting bar on the transparent insulating substrate;

Applying a gate insulating film on the transparent insulating substrate, and forming a thin film transistor which is a data bus line, a data pad, a second shorting bar, and a switching element so as to vertically intersect the gate bus line;

Forming a contact hole on the drain electrode, the gate pad, the data pad, the first shorting bar, and the second shorting bar of the thin film transistor by applying and etching a passivation layer on the insulating substrate on which the thin film transistor is formed; And

And depositing and etching an ITO metal film on the insulating substrate on which the contact hole is formed to form a pixel electrode, a gate pad pattern, and a data pad pattern.

Here, the first shorting bar, the second shorting bar, the gate pad, and the data pad may be electrically connected to each other by the gate pad pattern and the data pad pattern in a bridge form, and the gate pad pattern and the data pad pattern may be connected to the first shorting bar. It is characterized in that the electrical contact by depositing on the contact hole formed on the second shorting bar.

According to the present invention, not only the gate bus line, the data bus line, the TFT of the active region, and the pixel electrode defect inspection in the TFT inspection process of the liquid crystal display device, but also poor electrical contact between the pads and the pad pattern when actually completed. The pad pattern was formed in a crosslinked form so as to be examined.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a structure of a pad area for defect inspection of a liquid crystal display according to the present invention.

As shown in FIG. 4, in the array substrate, a plurality of gate bus lines applying driving signals and data bus lines applying graphic signals are vertically intersected to define a unit pixel area on the transparent insulating substrate.

A thin film transistor, which is a switching element, is disposed on an area where the gate bus line and the data bus line are vertically intersected, and a pixel electrode is disposed in electrical contact with the thin film transistor to form an electric field capable of twisting a liquid crystal. have.

If a gate pad is disposed at the edge of the gate bus line and a data pad is disposed at the edge of the data bus line, the first shorting bar 200 and the second shorting bar 100 may be formed outside the gate pad and the data pad. Spaced apart.

A contact hole is formed on the first shorting bar 200 and the second shorting bar 100 facing the gate pad 115 and the data pad, and the gate pad pattern 110 is formed in a cross-linked manner with an insulating layer therebetween. And a data pad pattern are arranged.

Although the gate pad region is illustrated in FIG. 4, the data pad region is also arranged in the same manner.

The gate pad pattern 110 is electrically connected to the gate pad 115, the first shorting bar 200, and the second shorting bar 100, and is connected by a line drawn from the pad as in the related art. The structure is electrically connected only by pad patterns.

The first shorting bar 200 is connected to an even number of the gate pad 115 and the data pad by pad patterns, and the second shorting bar 100 is an odd number of the gate pad 115 and the data pad. And are respectively connected by pad patterns.

However, the first shorting bar 200 may be connected to the odd pads or the second shorting bar 100 may be connected to the even pads.

When the test signal is applied to the first shorting bar 200, the gate pads 115 corresponding to even-numbered gate pad patterns 110 are connected to the first shorting bar 200. The TFTs are applied to the gate pads 115 and turn on / off the respective TFTs disposed in the active region.

Similarly, when a signal is applied to the second shorting bar 100 for a defect inspection, the gate pads 115 corresponding to the odd-numbered gates are bridge-shaped gate pad patterns connected to the second shorting bar 100. Applied to the gate pads 115 by 110, the TFTs disposed in the active region are driven.

Although not shown in the drawing, data pads are connected to the shorting bar in the same manner and a test signal is applied to check whether the pixel electrode is defective.

Therefore, in the present invention, a signal applied for TFT defect inspection is transmitted to the gate pads or the data pads through the gate pad pattern or the data pad pattern through the shorting bar, thereby inspecting the defects of the TFT and the pixel electrode. The poor contact due to the poor etching can be inspected.

FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. 4.

As shown in FIG. 5, a metal film is deposited and etched on the transparent insulating substrate 300 to form a gate bus line, a gate electrode, a gate pad 115, and a first shorting bar 200. Then, the gate insulating film 333 is applied over the entire region on the transparent insulating substrate 300, and an amorphous silicon film and a doped silicon film are coated, etched, and then deposited a metal film to form an active layer. The source / drain electrodes are completed to form a thin film transistor, a data bus line, a data pad, and a second shorting bar, which are switching elements.

The protective layer is coated on the insulating substrate on which the thin film transistor, the data bus line, the data pad, and the second shorting bar are formed and then etched to form a contact hole.

The contact hole is formed on a drain electrode of the thin film transistor, a gate pad, a data pad region, and the first shorting bar and the second shorting bar facing the gate pad and the data pad.

Depositing an ITO metal film on an entire area of the insulating substrate on which the contact hole is formed, etching to form a pixel electrode, and a gate pad pattern for electrically connecting the gate pad with the first shorting bar and the second shorting bar And a data pad pattern for electrical connection between the data pad, the first shorting bar, and the second shorting bar.

Thus, as shown in FIG. 5, the pad 115 region and the shorting bars 200 are formed on the transparent insulating substrate 300, and the gate pad pattern 110 is disposed on the gate insulating layer 333. It can be seen that the bridge is connected in a form.

That is, the ITO metal layer is patterned on the contact hole formed on the first shorting bar 200 and the second shorting bar and the contact hole formed on the gate pad 115 and the data pad, thereby forming two terminals. Electrically connected.

Therefore, in the present invention, by electrically connecting the shorting bar and the pad pattern used for the TFT inspection during the array process, it is possible to inspect the electrical contact failure between the pads and the pad patterns in the TFT inspection process.

As described in detail above, the present invention forms a crosslinked pad pattern that can be contacted with the shorting bar to inspect the pad pattern and the paddle contact failure in the TFT inspection process of the liquid crystal display device, thereby causing TFT defects and pixel defects. In addition, there is an effect that can check the line breakage and the electrical failure of the pad and pad pattern.

In addition, it is possible to check whether the pad pattern and the pads are in electrical contact through the open contact hole at the time of TFT inspection, so that the overall failure rate can be reduced and the production yield can be expected to increase.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (6)

A plurality of gate bus lines and gate pads disposed on the transparent insulating substrate to apply driving signals; A plurality of data bus lines and data pads arranged perpendicularly to the gate bus lines to define unit pixels and to apply graphic signals; A thin film transistor which is a switching element disposed on an area in which the gate bus line and the data bus line are vertically intersected and arranged; A pixel electrode electrically contacting the thin film transistor to form an electric field for twisting the liquid crystal; A first shorting bar and a second shorting bar arranged to apply a signal during TFT inspection while preventing line breaks due to static electricity outside the gate pad and the data pads; And Pad patterns arranged to electrically connect the first shorting bar, the even-numbered gate pads and the data pads, and electrically connect the second shorting bar, the odd-numbered gate pads and the data pads. LCD display device. The method of claim 1, And the gate pad, the data pads, the first shorting bar, and the second shorting bar are spaced apart from each other without being directly connected to each other. The method of claim 1, And the pad patterns are electrically connected to each other by a contact hole formed in the first shorting bar and the second shorting bar. Forming a gate bus line, a gate pad, and a first shorting bar on the transparent insulating substrate; Applying a gate insulating film on the transparent insulating substrate, and forming a thin film transistor which is a data bus line, a data pad, a second shorting bar, and a switching element so as to vertically intersect the gate bus line; Forming a contact hole on the drain electrode, the gate pad, the data pad, the first shorting bar, and the second shorting bar of the thin film transistor by applying and etching a passivation layer on the insulating substrate on which the thin film transistor is formed; And And depositing and etching an ITO metal film on the insulating substrate on which the contact hole is formed, thereby forming a pixel electrode, a gate pad pattern, and a data pad pattern. The method of claim 4, wherein And the first shorting bar, the second shorting bar, the gate pad, and the data pad are electrically connected to each other by the gate pad pattern and the data pad pattern in a bridge form. The method of claim 4, wherein And the gate pad pattern and the data pad pattern are deposited in contact holes formed on the first shorting bar and the second shorting bar and electrically contacted with each other.