KR100603833B1 - Array substrate with dual gate pad structure for Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a dual gate pad structure.

In the conventional dual-gate liquid crystal display array substrate, since the Vcom wirings connecting the common wirings are provided in different layers, it is impossible to perform a short test for determining whether the gate wiring and the common wiring are shorted after the gate process. Therefore, after completion of the data process, the short circuit between the gate wiring and the common wiring was examined. However, the array substrate that has undergone the gate process and the data process has already formed a thin film transistor, and in this step, when the short inspection of the common wiring and the gate wiring is performed to detect a defective array substrate in which the short occurs, the substrate is subjected to a subsequent process. It doesn't make progress, and it doesn't rework, so it doesn't help improve yield.

In the present invention, by providing an array substrate for a liquid crystal display device having a structure that allows a short inspection of the gate wiring and the common wiring after the completion of the gate process, a rework process is performed when a defect occurs due to a short after the gate process is performed. Yield reduction due to a short short circuit can be prevented.

Dual Gate Pad, Array Board, Short Inspection

Description

Array substrate with dual gate pad structure for Liquid crystal display device and method of fabricating the same}

1 is a schematic view of a liquid crystal display panel;

2 is a schematic plan view of a conventional array substrate for a transverse electric field type liquid crystal display device.

FIG. 3 is an enlarged view of one pixel area of FIG. 2; FIG.

4 is a plan view of an array substrate for a liquid crystal display device of a conventional dual gate pad structure.

5A and 5B are plan views showing a state in which a gate process and a data process are respectively completed in manufacturing the array substrate of FIG. 4.

6 is a plan view of an array substrate for a liquid crystal display device having a dual gate pad structure according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line A-A of FIG. 6; FIG.

8 is a cross-sectional view taken along the line B-B of FIG. 6.

9A and 9B are plan views showing a state in which a gate process and a data process are respectively completed in manufacturing the array substrate of FIG. 6.

10 is a plan view of an array substrate for a dual gate pad structure liquid crystal display device according to a modification of the present invention;

<Brief description of the main parts of the drawing>

140: array substrate 143: gate wiring

149: common wiring 153: common electrode

162: pixel electrode 173: second Vcom wiring

181: gate connection wiring 191, 193: contact hole

DPA: data pad portion GLL1: first gate link wiring

GP1: first gate pad GPA1, GPA2: first and second gate pad portions

AA: display area NA1 to NA4: first to fourth non-display area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display (LCD), and more particularly, to a wiring structure of an array substrate.

In general, the liquid crystal display device is a device using the optical anisotropy of the liquid crystal.

That is, the liquid crystal display device is a device for representing an image by using a characteristic that can control the light according to the intensity of the electric field and the light is adjusted according to the molecular arrangement of the liquid crystal when the voltage is applied, comprising a common electrode The lower substrate includes an upper substrate and a pixel electrode, and a liquid crystal layer filled between the two substrates.

A liquid crystal display device will be described in more detail with reference to the drawings.

1 is a view schematically showing a general liquid crystal display device.

As shown in the drawing, a general liquid crystal display device 1 includes a black matrix 7 formed between a color filter 5 and each of the color filters 5 on the transparent insulating substrate, and the color filter 5 and the black matrix ( 7) the upper substrate 3 having the common electrode 9 deposited thereon, the pixel region P defined by the intersection of the gate wiring 13 and the data wiring 15, and the pixel region P. And a lower substrate 11 formed of a pixel electrode 17 and a switching element T formed therein, and a liquid crystal 19 is filled between the upper substrate 3 and the lower substrate 11.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and includes a gate line 13 and a data line 15 passing through the plurality of thin film transistors. Is formed.

A general liquid crystal display having the above-described structure is a method of driving a liquid crystal by an electric field applied up and down by applying a voltage to a common electrode of an upper substrate and a pixel electrode of a lower substrate, and has excellent characteristics such as transmittance and aperture ratio. The disadvantage is that the viewing angle is narrow.

Accordingly, in order to overcome this problem, a transverse field type liquid crystal display device in which the common electrode and the pixel electrode are formed on one substrate and the liquid crystal is driven by a horizontal electric field has been proposed.

FIG. 2 is a schematic plan view of an array substrate for a general transverse electric field type liquid crystal display device, and FIG. 3 is an enlarged view of one pixel area.

As shown in the drawing, in the display area AA displaying an image on the array-type liquid crystal display array substrate 40, the gate line 43 in the horizontal direction and the data line 46 in the vertical direction intersect with each other. P is defined, and a thin film transistor which is a switching element connected to the gate line 43 and the data line 46 at the intersection of the gate line 43 and the data line 46 in the pixel region P; Tr) is formed.

In addition, the pixel region P has a common wiring 49 extending in the horizontal direction at regular intervals in parallel with the gate wiring 43, and a plurality of common electrodes branched from the common wiring 49. 53 extends in the longitudinal direction.

In addition, in the pixel region P, a plurality of pixel electrodes 62 having a vertical direction and arranged to be alternately arranged at a predetermined interval from the common electrode 53 are formed, and the pixel electrode 62 is a thin film transistor Tr. )

In the non-display area NA on the outside of the display area AA, a gate pad part GPA connected to the gate line 43 formed in the display area AA on one side and connected to an external driving circuit is provided. A data pad which is formed in the non-display area NA on the upper side of the display area AA and is connected to an external data driving circuit (not shown) and is connected to the data line 46 formed in the display area AA. A part DPA is formed.

In addition, one end of the data pad part DPA is positioned outside the display area AA, and a Vcom wiring 72 for applying a DC common voltage is formed in parallel with the data line 46. The Vcom wiring is formed. 72 is connected to one end of the common line 49 formed to cross the pixels located in the same row in parallel with the gate line 43.

However, in the liquid crystal display device having the above-described structure, as the liquid crystal display device becomes larger and larger, the length of the gate wiring increases, causing signal delay due to wiring resistance, resulting in a decrease in display quality. Therefore, in order to solve the problem of signal demonstration according to the wiring resistance, a liquid crystal display device having a dual gate structure capable of applying the same signal voltage at both ends of the gate wiring has been proposed.

4 is a plan view of an array substrate for a liquid crystal display device having a conventional dual gate pad structure.

As illustrated, the array substrate 140 of the dual gate structure for the liquid crystal display device has gate pad portions GPA1 and GPA2 for applying a gate signal from the outside to the gate wiring 143. It is characterized in that it is formed in each of the non-display areas NA1 and NA2 on both sides of the right side, and the structure of the other display areas AA is the same as that of the general liquid crystal display array substrate having the gate pad part on one side. The detailed structural description is omitted since it has been described.

The array substrate 140 of the dual gate pad structure for the liquid crystal display device simultaneously inputs the same gate signal at both ends with respect to the gate wiring 143, so that the wiring resistance of the liquid crystal display device is higher than that of the conventional liquid crystal display device having the gate signal input at one end thereof. It is possible to prevent some signal delays.

5A and 5B are plan views illustrating an array substrate in a state where a gate process and a data process are respectively completed in manufacturing the array substrate of FIG. 4.

In the gate layer forming step of manufacturing the array substrate 140 having the dual gate pad structure for the liquid crystal display device, the gate link wirings GLL1 and GLL2 including the gate wiring 143 positioned in the display area AA and The gate pad GP is formed of the same metal material at the same time, and the common wiring 149 is formed at a predetermined interval in parallel with the gate wiring 143, and the common wiring 149 is formed in each pixel P. A branched common electrode (the common electrode is shown in only one pixel region in the drawing) 153 is formed. In this case, referring to FIG. 5, which is a plan view of an array substrate having only a gate layer step, each gate line 143 forms a parallel structure by forming gate connection lines 181 and 182 connecting the gate pad GP. It is characterized by being connected to. This is to enable the inspection process to be carried out later only by connecting one terminal, and to prevent damage failure caused by static electricity generated during the process by forming an equipotential between each wiring 143. The gate connection lines 181 and 182 may form respective independent gate lines 143 by removing portions connected between gate pads immediately before completion of the liquid crystal panel.

In this case, in the liquid crystal display device having the above-described structure, in particular, in the transverse electric field type liquid crystal display device, a short occurs frequently between the gate wiring 143 and the common wiring 149 formed to be spaced apart from the gate wiring 143 by a predetermined distance. There is. Therefore, a short test should be performed to determine whether a short has occurred between the common wiring 149 and the gate wiring 143. In the above-described conventional structure, since the gate wiring 143 is all connected, the gate pads GP are connected. The test signal can be input simply by connecting one end of the tester to any one of the gate pads. However, each common wiring 149 has no Vcom wiring connecting the common wiring 149 itself. There is a problem that one end of each of the wirings 149 should be brought into contact with one end of the tester.

Therefore, a short test cannot be performed after the gate process step. As shown in FIG. 5B, the Vcom wirings 172 and 173 and the Vcom wirings 172 and 173 which connect the common wiring 149 by performing a data process are performed. After the Vcom input terminal CP is formed at one end, that is, after completion of the thin film transistor Tr, the gate wiring 143 connected to the Vcom input terminal CP at one end of the Vcom wirings 172 and 173. Short inspection of the common wiring 149 and the gate wiring 143 can be performed using the gate pad GP at one end.

However, the array substrate that has undergone the gate process and the data process has already formed a thin film transistor, and in this step, when the short inspection of the common wiring and the gate wiring is performed to detect a defective array substrate in which the short occurs, the substrate is subjected to a subsequent process. It doesn't make progress, and it doesn't rework, so it doesn't help improve yield.

Accordingly, the present invention provides an array substrate for a liquid crystal display device having a structure that allows a short inspection of the gate wiring and the common wiring after the completion of the gate process, thereby reworking the process when a defect occurs due to a short after the gate process. It aims at preventing the yield fall by short-circuit.

According to an exemplary embodiment of the present invention, an array substrate for a dual gate pad structure liquid crystal display device includes first and second gate pad portions having a central display area and first and second gate pad parts defined at left and right sides of the display area. A non-display area, a third non-display area having a data pad portion defined above the display area, and a fourth non-display area defined below; A gate wiring provided in the display area on the substrate in a horizontal direction; A common wiring provided at a predetermined interval apart from the gate wiring; A first gate link interconnection directly connected to one end of the gate interconnection with the same material as the gate interconnection in one of the first and second non-display regions; The first Vcom wiring, which is a metal material forming the common wiring in the non-display region in which the first gate link wiring is not formed, among the first and second non-display regions, is directly connected to one end of the plurality of common wirings and extends in the vertical direction. and; A gate insulating film formed over the gate wiring, the common wiring, the first gate link wiring, and the first Vcom wiring; A plurality of data wires disposed in the display area in the vertical direction over the gate insulating film to define a plurality of pixel areas crossing the plurality of gate wires; A second Vcom wire formed of the same material on the same layer as the data wire and connected to one end of a plurality of common wires not directly connected to the first Vcom wire through a contact hole; A second gate link wire connected to the other end of the gate wire directly connected to the first gate link wire through the second contact hole on the gate insulating layer; And a thin film transistor provided at an intersection point with the gate line and the data line.

In this case, the plurality of pixel regions may further include a plurality of common electrodes branched from the common wiring.

The pixel electrodes may further include pixel electrodes connected to the thin film transistors between the common lines.

The gate wiring, the common wiring, the first gate link wiring, and the first Vcom wiring are formed of the same metal material on the same layer, and the first and second gates are formed at one end of the first and second gate link wirings. The pad is further provided.

A method of manufacturing an array substrate for a dual gate pad structure liquid crystal display device according to the present invention includes a first display portion and a second non-display portion in which a first and a second gate pad portion are defined at left and right sides of a central display area and the display area. A third non-display area in which a data pad part is defined above the display area, and a fourth non-display area in the lower part of the display area; and a gate line in a horizontal direction in a horizontal direction, and a predetermined distance from the gate wire. A first wiring which is directly connected to one end of the gate wiring by a common wiring spaced apart from and parallel to the gate wiring and the same material as the gate wiring in one of the first and second non-display areas A gate link wiring and a non-display region in which the first gate link wiring is not formed among the first and second non-display regions, and directly at one end of the common wiring. (A) forming a first Vcom wire connected to each other and extending in a longitudinal direction, a first gate pad at one end of the first gate link wire, and a gate connection wire connecting all of the first gate pads; (B) forming a gate insulating film on the entire surface of the gate wiring; A vertically disposed display area on the gate insulating layer, the data line crossing the gate line to define a pixel area, and one end of a common line not directly connected to the first Vcom line and a first contact hole; (C) forming a second Vcom wiring, and a second gate link wiring, the second gate link wiring being connected to the other end other than one end of the gate wiring directly connected to the first gate link wiring through a second contact hole. Include.

In addition, after step (a), performing a short inspection of the gate wirings connected through the gate connection wirings and the common wirings connected by the first Vcom wirings; Reworking the substrate on which the defect has occurred during the short inspection; And performing the step (a) on the reworked substrate.

In addition, after step (b), the method may further include forming a contact hole in the gate insulating layer.
In addition, the step (a) further comprises the step of forming a gate electrode at the intersection with the gate line and the data line, the step (c) is a step of forming a semiconductor layer, and forming a source and drain electrode It further comprises a step.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

6 is a plan view of an array substrate for a liquid crystal display device having a dual gate pad structure according to an embodiment of the present invention, and FIGS. 7 and 8 are cross-sectional views taken along the lines A-A and B-B, respectively. 7 and 8, the pixel electrode, the common electrode, and the thin film transistor included in the pixel area in the display area are omitted.

First, for convenience of description in the drawings, the non-display areas positioned on the left and right sides of the display area AA on the array substrate 240 based on the display area AA displaying the center image are respectively arranged in a first ratio. Defined as the display area NA1 and the second non-display area NA2, and the gate pad part GPA configured in the first and second non-display areas NA1 and NA2 is respectively defined by the first gate pad part GPA1 and the first gate pad part GPA1. It is defined as a second gate pad part GPA2. The non-display areas above and below the display area AA are defined as third and fourth non-display areas NA3 and NA4, respectively. In this case, the data pad part DPA is defined in the third non-display area NA3.

As illustrated, the first gate pad part GPA1 and the second gate pad part GPA2 are provided on the left and right sides of the display area AA in the center of the array substrate 240. A plurality of gate lines 243 are formed in the display area in the horizontal direction with the GPA1 and the second gate pad part GPA2 interposed therebetween. In this case, each of the gate pads GP in the first and second gate pad portions GPA1 and GPA2 and the gate lines 243 in the display area AA are connected to the first and second gate link lines GLL1 and GLL2, respectively. And a gate pad GP in the first gate pad part GPA1 positioned in the first non-display area NA1 and a gate wire 243 provided in the display area AA. The first gate link wiring GLL1 may include a gate pad GP in the second gate pad portion GPA2 positioned in the second non-display area NA2, and a second gate link wiring GLL2 connecting the gate pad GP to the gate wiring 243. And different layers).

In addition, a data pad part DPA is provided in the third non-display area NA3 on the array substrate 240, and a plurality of data pads DP are provided in the data pad part DPA. A plurality of data lines 246 connected to the data link lines DLL connected to the data pads DP and disposed in the vertical direction in the display area AA to cross the gate lines 243 to define the pixel P. And a thin film transistor Tr, which is a switching element, is formed at an intersection point of the gate line 243 and the data line 246. In the display area AA, the common wiring 249 is formed to be parallel to the gate wiring 243 at predetermined intervals from the gate wiring 243, and the common wiring 249 is formed in each pixel area P. FIG. A plurality of common electrodes 253 branched from are formed.

In addition, the first and second Vcom wirings 272 and 273 respectively include data in the first and second non-display areas NA1 and NA2 between the first and second gate pad parts GPA1 and GPA2 and the display area AA. The first and second Vcom wires 272 and 273 are formed parallel to the wire 246, and both ends of the common wire 249 are formed across the pixels P positioned in the same row of the display area AA. Each is connected. In this case, the first and second Vcom wirings 272 and 273 are formed on different layers.

In more detail, the formation structure of each wiring is demonstrated with reference to FIGS.

7 and 8 are cross-sectional views taken along the lines A-A and B-B, respectively.

First, referring to FIG. 7, the first gate link wiring GLL1, the gate wiring 243, the first Vcom wiring 272, the common wiring 249, and the data wiring 246 of the first gate pad part GPA1. In the following description, a first gate link line GLL1 connected to a gate pad (not shown) is formed on a substrate 241, and the common gate is spaced apart from the first gate link line GLL1 by a predetermined distance. The wiring 249 and the gate wiring 243 are formed at predetermined intervals, respectively. In this case, the first gate link wiring GLL1 and the gate wiring 243 do not appear to be connected in the drawing, but are actually connected as shown in FIG. 6 and are formed on the substrate 241. The gate wiring 243, the first gate link wiring GLL1, and the common wiring 249 are formed of the same metal material.

Next, a gate insulating film 251 is formed on the entire surface of the first gate link wiring GLL1, the common wiring 249, and the gate wiring 243. The gate insulating film 251 is formed on the gate insulating film 251 and the common wiring 249. The first Vcom wiring 272 is in contact with each other through the contact hole 291, and the data wiring 246 is formed at a predetermined interval from the first Vcom wiring 272. In addition, a protective layer 260 is formed on an entire surface of the first Vcom wiring 272 and the data wiring 246.

On the other hand, referring to FIG. 8, which is a cross-sectional view cut around the second Vcom wiring 273 and the second gate link wiring GLL2, the gate wiring 243 is disposed in the display area AA on the substrate 241 as shown. The second non-display area NA2 has a common wiring 249 and a second Vcom wiring 273 connected to one end of the common wiring 249. In this case, the gate wiring 243, the common wiring 249, and the second Vcom wiring 273 are formed of the same metal material.

Next, a gate insulating film 251 is formed on an entire surface of the gate wiring 243, the common wiring 249, and the second Vcom wiring 273, and the display area AA and the second insulating film are formed on the gate insulating film 251. The second gate link line GLL2 is formed at the boundary of the non-display area NA2 to contact the lower gate line 243 through the contact hole 293. In addition, a protective layer 260 is formed on an entire surface of the second gate link wiring GLL2.

Therefore, comparing FIGS. 7 and 8, the first gate link wiring GLL1 connecting the first gate pad (not shown) and the gate wiring 243 and the first gate pad (not shown) and the gate electrode 243. ) And the common wiring 249 and the second Vcom wiring 273 connected to the common wiring 249 are formed by a gate process on the substrate 241 among the layers of the array substrate 240. The gate pad (not shown), the second gate link wire (GLL2) connecting the second gate pad (not shown) and the gate wiring 243, the data wiring 246 and the first Vcom wiring 272 are gate insulating films. It can be seen that 251 is formed by the data process.

As described above, the first gate link wiring, the first gate pad, the second gate link wiring, and the second gate pad, which are respectively connected to the gate wiring, are formed in different layers, and at the same time, common wiring formed in each pixel in the display area. The first and second Vcom wires respectively connected to both ends of the first and second Vcom wires are formed in different layers so that the short test between the common wire and the gate wire can be performed after the gate process is performed.

Next, the manufacturing method and the short inspection process will be described with reference to the plan view of the array substrate having completed the gate process only.

FIG. 9A illustrates a state in which a gate process is completed in an array substrate for a dual gate pad structure liquid crystal display according to an exemplary embodiment of the present invention. As shown in FIG. 6, for convenience of description, the display area AA and the first to fourth non-display areas NA1 to NA4 are defined in the central part of the array substrate 240 based on the central part of the array substrate 240. The first and second gate pad parts GPA1 and GPA2 and the data pad part DPA are defined in the first to third non-display areas NA1 to NA3.

In order to manufacture the array substrate 240 according to the present invention, when a series of gate processes such as metal material deposition, photoresist coating, exposure, photoresist development, metal material etching, and photoresist strip are completed, The gate wiring 243 and the gate wiring 243 at predetermined intervals from the gate wiring 243 and the first gate link wiring GLL1 connecting the one end of the gate wiring 243 and the first gate pad GP1. ) And a second Vcom wire 273 connected to one end of the common wire 249. In this case, each of the first gate pads GP1 of the first gate pad part GPA1 is connected to each other by the gate connection line 281, and the common line 249 in the display area AA may also be formed. 2 Vcom wiring (273) is characterized in that all connected. Accordingly, only one gate pad of the plurality of first gate pads GP1 and the second Vcom formed in the first gate pad part GPA1 with respect to whether a short between the gate line 243 and the common line 249 occurs. The second Vcom terminal CP, which is connected to one end of the wiring 273 and is formed on the data pad part DPA, may be contacted with two terminals of a short checker (not shown), respectively, to easily determine whether a short is generated. have.

In the conventional structure, since the Vcom wiring connected to each common wiring is not provided in the gate layer, in order to perform the short inspection, the terminals of the short inspection apparatus must be brought into contact with one end of the common wiring provided for each pixel row. However, although the short inspection could not be performed after the gate process step, in the present invention, after completion of the gate process, the gate wiring 243 connected to all the gate layers and the second Vcom wiring 273 connecting both the common wiring 249 are formed. Thus, the Vcom terminal CP at one end of the second Vcom wiring 273 and one of the first gate pads GP1 at one end of the first gate link wiring GLL1 connected to the gate wiring are connected to the short tester terminal. Short inspection can be performed.

As described above, since the short inspection is performed and the array substrate in which the defect is generated has only one step as a metal material on the substrate, it is relatively easy to rework. Thus, the reworking process is performed to remove all the wiring of the metal material and then reinsert it. The gate process described above is performed. Therefore, the production yield of the final array substrate can be improved.

Next, the data process after the gate process will be described with reference to 9b, which is a plan view of the array substrate having completed the data process.

Next, when the above-described gate process is completed, as shown in FIG. 9B, an inorganic insulating material is deposited on the entire surface of the substrate to form a gate insulating film (not shown). Thereafter, a portion of the gate insulating layer (not shown) is patterned to form contact holes 291 and 293.

The contact holes 291 and 293 are formed at one end of the gate line 243 not connected to the first gate link line GLL1 and at one end of the common line 249 positioned in the first non-display area NA1. One end of the gate line 243 and the common line 249 are exposed.

Next, a data process is performed on the gate insulating layer (not shown), and a plurality of data wires 246 intersecting the gate wires 243 and data link wires connected to one end of the data wires 246 in the display area are formed. DLL, the data pad DP, and the first non-display area NA1 through the contact hole 291 to contact one end of the common line 249, respectively, and are parallel to the data line. A plurality of second gate link lines GLL2 connected to one end of the gate line 243 and the contact hole 293 are formed at the same time as the wiring 272. In this case, the data line 246 is formed by connecting all of the data pads DP formed at one end of the data link line DLL connected to one end of the data line 246 by the data connection line 283. Since all data lines 246 form an equipotential by the data connection lines 289, damage due to static electricity generated in a subsequent process may be prevented.

Next, a plurality of common electrodes 253 branched from the common wiring 249 are formed in each pixel area P as the data process proceeds. In addition, the thin film transistor Tr formed of a gate electrode (not shown), a semiconductor layer (not shown), and a source and drain electrode (not shown) at an intersection point of the gate line 243 and the data line 246. A protective layer (not shown) is formed on the thin film transistor Tr by a process, and a pixel electrode 262 is formed between the common electrode 253 on the protective layer (not shown). In this case, the pixel electrode 262 is connected to the thin film transistor Tr through a drain contact hole (not shown) formed in the protective layer (not shown).

The gate connection wirings 281 and 282 and the data connection wirings 283 are later removed in a liquid crystal panel (not shown) forming process, and finally, the gate wirings 243 and the data wirings 246 that are electrically separated from each other are formed. do.

The manufacturing method of the array substrate by this invention is completed by the method mentioned above.

Next, referring to FIG. 10 as a modified example of the above-described embodiment, as shown, the array substrate 340 according to the modified example includes the second gate pad GP2 and the second gate pad GP2 in the second gate pad portion GPA2. The second gate link wiring GLL2, the gate wiring 343, the common wiring 349, and the first Vcom wiring 372 connected to the common wiring 349 in the first non-display area NA1 are first subjected to a gate process. By forming the symmetrical structure with respect to the display area compared to the above-described embodiment of the present invention (Fig. 9), one pad of the second gate pad GP2 and the first Vcom wiring 372 are simply formed after the gate process. By connecting the first Vcom terminal CP1 formed at one end to two terminals (not shown) of the short tester (not shown), it is possible to inspect whether the short between the gate wiring 343 and the common wiring 349 is short. The rest of the structure is the same as that in the embodiment, and thus the description is omitted.

An array substrate for a liquid crystal display device of a dual gate type according to the present invention may be formed of a first gate link line, a first gate pad, and a gate line connected to the gate line in the first gate pad part using the same material as that of the gate line. After the gate process, a common wiring formed at a predetermined interval is formed and a second Vcom wiring and a Vcom terminal are formed at one end of the second Vcom wiring in the second non-display area where the second gate pad portion is formed. Short inspection between common wirings can be performed.

Therefore, it is possible to determine whether or not a short defect occurs in the array substrate by a short inspection after the gate process, and since the array substrate in which the short defect has occurred has only completed the gate process, the gate material is simply removed by the rework process. It is effective in improving a yield by putting into a process.

Claims (9)

First and second non-display areas in which first and second gate pad portions are defined to the left and right sides of the display area and a third non-display area in which data pad portions are defined above the display area. A substrate, wherein a fourth non-display area is defined; A gate wiring provided in the display area on the substrate in a horizontal direction; A common wiring provided at a predetermined interval apart from the gate wiring; A first gate link interconnection directly connected to one end of the gate interconnection with the same material as the gate interconnection in one of the first and second non-display regions; The first Vcom wiring, which is a metal material forming the common wiring in the non-display region in which the first gate link wiring is not formed, among the first and second non-display regions, is directly connected to one end of the plurality of common wirings and extends in the vertical direction. and; A gate insulating film formed over the gate wiring, the common wiring, the first gate link wiring, and the first Vcom wiring; A plurality of data wires disposed in the display area in the vertical direction over the gate insulating film to define a plurality of pixel areas crossing the plurality of gate wires; A second Vcom wire formed of the same material on the same layer as the data wire and connected to one end of a plurality of common wires not directly connected to the first Vcom wire through a contact hole; A second gate link wire connected to the other end of the gate wire directly connected to the first gate link wire through the second contact hole on the gate insulating layer; A thin film transistor provided at an intersection point with the gate line and the data line Array substrate for a dual gate pad structure liquid crystal display device comprising a. The method of claim 1, And a plurality of common electrodes branched from common wirings in the plurality of pixel regions. The method of claim 2, And a pixel electrode connected to the thin film transistor between the plurality of common electrodes in the pixel region. The method of claim 1, And the gate wiring, the common wiring, the first gate link wiring, and the first Vcom wiring are formed of the same metal material on the same layer. The method of claim 1, And a first gate gate and a second gate pad at one end of each of the first and second gate link wires. First and second non-display areas in which first and second gate pad parts are defined to the left and right sides of the display area, a third non-display area in which a data pad part is defined to the upper side of the display area, and a lower side of the display area. A fourth non-display area defined by the gate wiring in the horizontal direction, a common wiring parallel to the gate wiring spaced apart from the gate wiring by a predetermined distance, and the first and second ratios. A first gate link wiring directly connected to one end of the gate wiring using the same material as the gate wiring in one of the non-display regions of the display region, and a first gate link among the first and second non-display regions; A first Vcom wiring directly connected to one end of the common wiring in a non-display area where no wiring is formed and extending in a longitudinal direction, and one end of the first gate link wiring; (A) forming a first gate pad and a gate connection line connecting all of the first gate pads to each other; (B) forming a gate insulating film on the entire surface of the gate wiring; A vertically disposed display area on the gate insulating layer, the data line crossing the gate line to define a pixel area, and one end of a common line not directly connected to the first Vcom line and a first contact hole; (C) forming a second gate link wiring, wherein the second gate link wiring is connected to the other end other than one end of the gate wiring directly connected to the first gate link wiring through a second contact hole. Method of manufacturing an array substrate for a dual gate pad structure liquid crystal display device comprising a. The method of claim 6, after step (a), performing a short inspection on the gate wirings connected through the gate connection wirings and the common wirings connected by the first Vcom wirings; Reworking the substrate on which the defect has occurred during the short inspection; Performing step (a) on the reworked substrate Method of manufacturing an array substrate for a dual gate pad structure liquid crystal display device further comprising. The method of claim 6, The step (b) further comprises forming the first and second contact holes in the gate insulating film. The method of claim 6, The step (a) further includes the step of forming a gate electrode at the intersection with the gate wiring and the data wiring, The method (c) may further include forming a semiconductor layer and forming source and drain electrodes, wherein the array substrate for a dual gate pad structure liquid crystal display device is formed.

Images