KR102077327B1 - Circuit for preventing static electricity and display device comprising the same - Google Patents

Abstract

The present invention provides an antistatic circuit and a display device including the same, specifically, the antistatic circuit includes a driving circuit for driving a display unit for displaying an image, and at least one clock signal wire for transmitting a clock signal to the driving circuit. An antistatic circuit of a display device, wherein the antistatic circuit includes at least one transistor electrically connected to each of the at least one clock signal wire, one electrode and a predetermined electrode commonly connected to the source electrode and the drain electrode of the transistor. At least one capacitor including the other electrode is applied a fixed voltage of.

Description

Antistatic circuit and display device including the same {CIRCUIT FOR PREVENTING STATIC ELECTRICITY AND DISPLAY DEVICE COMPRISING THE SAME}

The present invention relates to an antistatic circuit and a display device including the same.

BACKGROUND ART Generally, flat panel displays such as organic light emitting diode display devices have been expanded in application due to features such as light weight, thinness, low power driving, full color, and high resolution. Currently, organic light emitting display devices are increasingly used in computers, laptops, telephones, TVs, and audio / video devices.

The organic light emitting diode display displays an image according to data by adjusting an amount of driving current transmitted to the organic light emitting diode according to an image data signal applied to each of a plurality of pixels arranged in a matrix.

On the other hand, a glass substrate is mainly used as a substrate of the display device. Since the glass substrate is an insulator, static electricity generated during the panel manufacturing process is charged on the glass substrate, and dust or the like is easily attached, which causes process defects. Since the element may be destroyed, the anti-static measures are generally provided in the flat panel display panel.

As a related art, there is a method of inserting an electrostatic shield wire or inserting a resistor into an edge of a display panel. In addition, there is a method of installing an antistatic circuit using a diode between the wiring for supplying a power voltage for driving the display panel and the wiring for supplying a signal required for lighting inspection.

However, in the recent trend of large display panels being produced, the generation of static electricity is significantly higher in processes and modules than in small and medium display panels. Therefore, there is a limit to preventing the static electricity of the large display panel only by using the electrostatic shield wiring or the resistance as in the prior art. In addition, even when an antistatic circuit is installed, bursting damage frequently occurs on the antistatic circuit itself due to a high potential difference when static electricity is generated, resulting in short-circuit (short) damage, which causes defects in driving of the entire display panel. There is concern.

Therefore, a study on the robust design of the electrostatic robustness of the display panel that can effectively prevent the generation of static electricity of the large display panel while preventing the driving failure and damage of the display panel of the organic light emitting diode display from the burst damage of the antistatic circuit is needed.

Problems to be solved by the embodiment of the present invention to prevent the inflow and generation of static electricity in the display panel to prevent the malfunction of the display panel due to the static electricity, breakage, and process failure of the display device.

In addition, an object of the present invention is to provide a display panel having excellent quality by solving the problem of driving failure caused by the inflow of static electricity in the display device by providing an antistatic design circuit that can be effectively applied to a large display panel.

An antistatic circuit according to an embodiment of the present invention for solving the above problems includes a display circuit including a driving circuit for driving a display unit for displaying an image and at least one clock signal wire for transmitting a clock signal to the driving circuit. In an antistatic circuit of a device, the antistatic circuit comprises at least one transistor electrically connected to each of the at least one clock signal wires, and one electrode and a predetermined fixing commonly connected to the source and drain electrodes of the transistor. At least one capacitor including the other electrode to which the voltage is applied.

Each of the at least one clock signal line is connected to a gate electrode of each of the at least one transistor through a gate metal line. However, the present invention is not limited thereto, and the clock signal wire and the gate electrode of the transistor may be electrically connected to each other.

The transistor includes a semiconductor layer including a predetermined impurity doped region doped with semiconductor impurities and an intrinsic semiconductor region not doped with semiconductor impurities, and a gate electrode layer formed over the semiconductor layer with a gate insulating layer interposed therebetween. . At this time, the electrostatic current flowing through the at least one clock signal wire opens or shorts the gate insulating layer of the transistor.

The impurity doped region of the semiconductor layer is formed to face the first impurity doped region and the first impurity doped region and is electrically connected to the first impurity doped region in a region not overlapping with the gate electrode layer. Impurity doped region.

When the gate insulating layer is shorted, the introduced electrostatic current may be accumulated in a capacitor including one electrode electrically connected to an impurity doped region of the semiconductor layer.

According to another aspect of the present invention, there is provided a display device including a plurality of pixels, wherein each of the plurality of pixels emits light according to a data voltage according to an image data signal to display an image. A driving circuit unit for driving a display unit, at least one clock signal line for transmitting a clock signal to the driving circuit unit, at least one transistor electrically connected to each of the at least one clock signal line, and a source electrode and a drain of the transistor An antistatic circuit includes at least one capacitor including one electrode commonly connected to an electrode and another electrode to which a predetermined fixed voltage is applied.

In this case, the antistatic circuit may be provided between the at least one clock signal wire and the driving circuit unit.

Each of the at least one clock signal line may be connected to a gate electrode of each transistor of the antistatic circuit through a gate metal line.

The transistor includes a semiconductor layer comprising a predetermined impurity doped region doped with semiconductor impurities and an intrinsic semiconductor region not doped with semiconductor impurities, and a gate electrode layer formed over the semiconductor layer with a gate insulating layer interposed therebetween. The one electrode of the capacitor may be electrically connected to the impurity doped region.

The gate insulating layer of the transistor may be opened or shorted by an electrostatic current flowing through at least one clock signal line.

When the gate insulating layer is shorted, the introduced electrostatic current may be accumulated in a capacitor including one electrode electrically connected to an impurity doped region of the semiconductor layer.

According to the present invention, it is possible to prevent the inflow and generation of static electricity to the display panel, thereby preventing the display panel from malfunctioning, damage, and process defect of the display device.

In addition, by adding an anti-static design circuit that can be effectively applied to large display panels that generate more static electricity than the existing anti-static small and medium size display panels, the display device efficiently solves the problem of poor driving caused by static electricity inflow, thereby providing excellent display quality. A panel and a display device including the display panel can be provided.

1 is a schematic view illustrating an antistatic circuit structure of a display panel according to an exemplary embodiment of the present disclosure.
FIG. 2 is a circuit diagram illustrating a portion A of the antistatic circuit of FIG. 1, according to an embodiment of the present disclosure. FIG.
Figure 3 is an internal configuration briefly showing an enlarged cross-sectional structure of the B-B 'portion in the antistatic circuit of Figure 1 according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In order to clearly describe the embodiments of the present invention, parts irrelevant to the description are omitted, and like reference numerals designate like elements throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

1 is a schematic diagram illustrating an antistatic circuit structure of a display panel according to an exemplary embodiment.

Referring to FIG. 1, an antistatic circuit of a display panel according to an exemplary embodiment is provided in a display device. In an embodiment, the antistatic circuit is provided in a display device including a display panel (display unit) including a plurality of pixels for displaying an image and a driving circuit for driving the display panel. In more detail, the driving circuit may be provided between the plurality of clock signal lines CL1 to CL4 for transmitting a clock signal to the driving circuit. In FIG. 1, one side of a plurality of clock signal wires is provided.

That is, the antistatic circuit according to an exemplary embodiment of the present disclosure may provide a predetermined clock signal to a driving circuit or a data source output circuit for transmitting a gate signal or a scan signal to a pixel portion including a plurality of pixels for displaying an image on a display panel. Each of the clock signal wires may be electrically connected to each other to prevent static electricity (ESD) flowing through the clock signal wires.

Referring to FIG. 1, an antistatic circuit according to an embodiment of the present invention includes an antistatic transistor and a capacitor connected to the clock signal lines CL1 to CL4, respectively.

That is, the capacitor includes a capacitor having at least one antistatic transistor electrically connected to each of the plurality of clock signal wires for transmitting the plurality of clock signals, and one electrode electrically connected to the source and drain electrodes of the antistatic transistor.

In the embodiment of FIG. 1, the antistatic circuit exemplifies three lines of an antistatic transistor and a capacitor. However, the present disclosure is not limited thereto, and the antistatic circuit may include a plurality of antistatic transistors and capacitors connected to a plurality of clock signal wires. . In FIG. 1, the antistatic transistor T1 of the first line has a source electrode 1S and a drain electrode 1D connected to each other in the same layer, and a gate electrode having a gate insulating layer (not shown) interposed therebetween. (1G) is included. The source electrode 1S and the drain electrode 1D of the antistatic transistor T1 of the first line are connected to each other at the lower side, and are spaced apart from each other at the upper side where the gate electrode 1G is stacked.

The gate electrode 1G of the antistatic transistor T1 is electrically connected to each other through the corresponding clock signal line CL3 and the gate metal line GL1. The clock signal line CL3, the gate metal line GL1, and the plurality of contact holes CH are electrically connected to each other, and the gate metal line GL1 extends to one side of the clock signal line to prevent the antistatic transistor T1. The gate electrode 1G is electrically connected to the contact hole.

In addition, the source electrode 1S and the drain electrode 1D connected to each other at the lower side of the antistatic transistor T1 are connected to one electrode CE1 of the capacitor C1 of the first line in the same layer. The capacitor C1 of the first line includes one electrode CE1 connected to the source electrode 1S and the drain electrode 1D of the antistatic transistor T1, an insulating layer stacked thereon (not shown), and It is composed of other electrodes FE stacked above. As shown in FIG. 1, the other electrode FE is one conductive layer, which is the other electrode of all the capacitors C1 to C3 constituting the antistatic circuit. A predetermined fixed voltage is applied through the other electrode FE, and one electrode of the plurality of capacitors constituting the antistatic circuit is fixed to the voltage value of the fixed voltage.

In the embodiment of FIG. 1, an antistatic transistor and a capacitor connected to the clock signal wires are formed in each line in the above-described form. That is, the antistatic transistor T2 and the capacitor C2 are connected to the clock signal line CL2, and the antistatic transistor T3 and the capacitor C3 are connected to the clock signal line CL1.

Gate metal lines GL1 to GL3 connecting the clock signal lines CL1 to CL3 and the antistatic circuit are connected to transfer clock signals to a driving circuit such as a data source output circuit, a gate driver, or a scan driver. Wiring. By constructing an antistatic circuit of the present invention connected to these gate metal wirings GL1 to GL3 between the clock signal wiring and the driving circuit, the gates of the gate metal wirings when the antenna rules are not followed in the panel process. An antistatic circuit connected to the metal wiring may be used to prevent static electricity flowing through the clock signal wiring.

Here, the non-observance of the antenna rule means that the area of the gate metal wiring extending and arranged in the display panel is larger than the gate electrode area of the transistor connected to the gate metal wiring by a predetermined ratio or more.

Referring to the operation of the antistatic circuit of the present invention, for example, as shown in Fig. 1, when the static electricity (ESD) is introduced from the outside through the clock signal line CL2, the gate metal wiring GL2 violating the antenna rules. Burn by using the gate insulating layer of the antistatic transistor T2 connected to)) to prevent static electricity from being transferred to other circuit elements inside the display panel. That is, by adding a transistor that is not related to the circuit operation of the image display inside the display panel, when static electricity flows through some of the plurality of clock signal wires, high or low electrostatic current is induced to the added antistatic transistor. The driving circuit of the display panel can be protected by burning down the gate insulating layer having the smallest thickness among the antistatic transistors.

An embodiment of the present invention is not necessarily limited to the embodiment of FIG. 1, and at least one antistatic circuit may be formed on a gate metal line connecting the clock signal line and the driving circuit.

In order to induce an electrostatic current transmitted from the outside to the antistatic transistor, as shown in FIG. 1, the other electrode FE of the capacitor connected to the source electrode and the drain electrode of the antistatic transistor is applied with a fixed voltage. One electrode of the capacitor is connected to the source electrode and the drain electrode of the antistatic transistor, but the other electrode FE is connected to the source of the fixed voltage in order to prevent short between both electrodes of the capacitor during the induction of static electricity.

Here, the meaning of burning the gate insulating layer of the antistatic transistor by inducing an electrostatic current may vary depending on the amount of the electrostatic current at the high or low level, but may affect the gate insulating layer of the antistatic transistor to be electrically open. Or short.

When the antistatic transistor is opened, electricity is not conducted as in the case of a wired wire, so external static electricity does not affect the operation of the circuit elements inside the display panel. In addition, when the antistatic transistor is shorted, an excessive amount of current flows through the antistatic transistor, but the capacitor accumulates on one electrode of the capacitor connected to the source-drain electrode of the antistatic transistor, so the capacitor is The charged voltage is maintained by a difference from the fixed voltage of the other electrode. As a result, external static electricity may be prevented from entering the internal driving circuit of the display panel via the clock signal wiring and the gate metal wiring.

A circuit diagram showing an A portion of the antistatic circuit of FIG. 1 according to an embodiment of the present invention is shown in FIG. 2.

The antistatic circuit of the present invention indicates that a plurality of transistors and capacitors of the base unit are included based on at least one transistor and a capacitor connected to each of the gate metal lines electrically connected to the plurality of clock signal wires.

Therefore, the portion A is a basic unit of the antistatic circuit according to an embodiment of the present invention, and is an antistatic circuit connected to one of the plurality of clock signal wires (CL3 in FIG. 1). That is, the portion A includes the antistatic transistor T1 and the capacitor C1 of the first line connected to the gate metal line GL1 connected to the clock signal line CL3 in FIG. 1.

The antistatic transistor T1 is connected to the gate metal line GL1 and receives a clock signal or an electrostatic voltage flowing from the outside, and a source electrode commonly connected to the first node N1. 1S and the drain electrode 1D.

The capacitor C1 includes one electrode connected to the first node N1 and the other electrode connected to a source for transmitting a fixed voltage VDH.

The capacitor C1 accumulates excessive electrostatic current in one electrode when a gate insulating layer, which is a lower layer of the gate electrode, is shorted when an electrostatic current introduced from the outside is induced to the gate electrode 1G of the antistatic transistor T1. . The battery is charged and maintained at a voltage value corresponding to a difference from the fixed voltage VDH applied to the other electrode. Then, since static electricity flowing in the antistatic circuit can be accumulated, the static electricity does not affect other circuit elements of the display panel, thereby protecting the display device from static electricity.

In another case, when the electrostatic current introduced from the outside is induced to the gate electrode 1G of the antistatic transistor T1, the other circuit of the display panel is not electrically conducted when the gate insulating layer, which is a lower layer of the gate electrode, is opened. The devices are not affected by static electricity.

3 is an internal configuration diagram schematically illustrating an enlarged cross-sectional structure of a portion B-B 'of the antistatic circuit of FIG. 1, according to an embodiment of the present disclosure.

Although not shown in FIG. 3, an insulating substrate may be disposed at the bottom of the cross-sectional structure of the portion B-B 'according to each structural means.

That is, a buffer layer made of an insulating substrate, silicon oxide, or the like may be formed at the lowermost portions of the antistatic transistor T2 and the capacitor C2. It will be omitted.

In addition, the B-B 'line is a line extending from the clock signal line CL2 and passing through two clock signal lines CL3 and CL4, but for convenience of description, the clock is not electrically connected to the antistatic transistor T2 of FIG. 3. The display of the signal wires CL3 and CL4 is omitted.

Referring to FIG. 3, first, the semiconductor layer SCL of the antistatic transistor T2 is formed. It may be composed of polysilicon (polycrystalline silicon, Poly-Si).

The gate insulating layer 20 is formed on the semiconductor layer SCL. Although the material of the gate insulating layer 20 is not particularly limited, inorganic materials such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), and the like, mixed materials of these inorganic materials, organic materials such as polyvinylphenol (PVP) and polyimide (polyimide) It may be made of. In general, since the thickness of the gate insulating layer 20 is the thinnest, the gate insulating layer 20 may be burnt by an antistatic transistor and may be electrically opened or shorted.

After the gate insulation layer 20 is formed, the gate electrode layer 50 is patterned on the region where the semiconductor layer SCL is formed.

After the gate electrode layer 50 is patterned, impurities are doped using the gate electrode layer 50 as an anti-doping film. In the embodiment of FIG. 3, p-type impurities are doped to form p-type impurity doped regions 11 and 12. Done. Then, the intrinsic semiconductor layer region 10 which is not doped with impurities is formed in the semiconductor layer SCL under the region where the gate electrode layer 50 is formed.

The p-type impurity doped regions 11 and 12 may be formed as source and drain electrodes, respectively. Although not shown in FIG. 3, the p-type impurity doped regions 11 and 12 may be formed at different positions of the antistatic transistor T2. 12 may be connected to each other to form a common node. The conductive layer 70 of the capacitor C2 is formed at the same layer as the common node, that is, the interconnected p-type impurity doped regions 11 and 12, and the p-type impurity doped region (1) is formed as one electrode CE2 of the capacitor. 11 and 12).

The clock signal line 40 may be formed by patterning a predetermined region after forming the gate insulating layer 20. However, this is one embodiment and may be formed by a process separate from the antistatic circuit.

The clock signal wire 40 is a metal wire that transfers a clock signal from the controller to the drive circuit. The materials constituting these metal wirings are not limited, but may be conductive materials or alloys thereof. In particular, it may be composed of a metal material such as molybdenum (Mo), tantalum (Ta), cobalt (Co) or an alloy thereof.

Meanwhile, after the gate electrode layer 50 is formed, an interlayer insulating layer 30 may be formed thereon. In the embodiment of FIG. 3, the interlayer insulating layer 30 is formed to extend over the clock signal line 40, but is not necessarily limited thereto.

The constituent material of the interlayer insulating layer 30 is not particularly limited, but like the gate insulating layer 20, inorganic materials such as silicon oxide (SiO ₂ ), silicon nitride (SiNx), and the like, mixed materials of these inorganic materials, and polyvinylphenol (PVP). It may be made of an organic material such as polyimide. The interlayer insulating layer 30 may be formed of at least two layers rather than a single layer as shown in FIG. 3. In addition, the interlayer insulating layer 30 may be made of the same insulating material as the gate insulating layer 20, but may be configured differently.

After the interlayer insulating layer 30 is formed, a portion of the clock signal line 40 and the gate electrode layer 50 are exposed by patterning, and then the gate metal line 60 (GL2) is formed. The material constituting the gate metal line 60 (GL2) is not particularly limited, but may be a conductive metal material. In particular, the conductive material may include titanium (Ti), aluminum (Al), and alloys thereof (Ti / Al / Ti).

The gate metal line 60 (GL2) electrically connects the clock signal line 40 and the gate electrode layer 50 through contact holes between the clock signal line 40 and the gate electrode layer 50 that are patterned and exposed. .

Thus, the electrostatic current flowing from the clock signal wire 40 is transferred to the gate electrode layer 50. Then, the gate insulating layer 20 between the gate electrode layer 50 and the semiconductor layer SCL is burnt due to static electricity, thereby being electrically opened or shorted.

Meanwhile, the capacitor C2 forms the conductive layer of the one electrode 70 and then stacks the insulating layer 80. And a conductive layer is formed as the other electrode 90 on it. A fixed voltage is applied to the other electrode 90. Therefore, when the gate insulating layer 20 of the antistatic transistor T2 is shorted by the electrostatic current, the capacitor C2 connected to the source electrode and the drain electrode, which are the impurity doped regions 11 and 12 of the semiconductor layer SCL, is connected. The electrostatic current collects on one electrode 70 so that static electricity does not flow into other circuit elements of the display panel.

In the embodiment of FIG. 3, the films that may be formed on the gate metal wiring 60 (GL2) and the other electrode 90 of the capacitor C2 are generally used during the manufacturing of a display panel such as an interlayer insulating layer and a protective layer. Since it may be a known film formed by the description thereof will be omitted.

DETAILED DESCRIPTION OF THE INVENTION The detailed description of the invention and the drawings so far referred to are merely illustrative of the invention, which is used only for the purpose of illustrating the invention and is intended to limit the scope of the invention as defined in the meaning or claims. It is not. Therefore, one of ordinary skill in the art can easily select and replace therefrom. Those skilled in the art can also omit some of the components described herein without adding performance degradation or add components to improve performance. In addition, those skilled in the art may change the order of the method steps described herein according to the process environment or equipment. Therefore, the scope of the present invention should be determined not by the embodiments described, but by the claims and their equivalents.

CL1, CL2, CL3, CL4: Clock Signal Wiring
GL1, GL2, GL3: Gate Metal Wiring
T1, T2, T3: Antistatic Transistors
C1, C2, C3: Capacitor
10: intrinsic semiconductor layer region
11, 12: p-type impurity doped region
20: gate insulating layer 30: interlayer insulating layer
40: clock signal wiring 50: gate electrode layer
60: gate metal wiring 70: capacitor one electrode
80: insulation layer 90: capacitor other electrode

Claims (14)

A display unit including a plurality of pixels and displaying an image, a non-display unit around the display unit,
A driving circuit unit disposed on the non-display unit and driving the display unit;
At least one clock signal wire which transfers a clock signal to the driving circuit unit, and
At least one transistor including at least one transistor electrically connected to the at least one clock signal wire and a gate electrode, one electrode commonly connected to the source and drain electrodes of the transistor, and at least one other electrode to which a predetermined fixed voltage is applied. A first circuit comprising a capacitor of
Display device comprising a. The method of claim 1,
The first circuit is located on the non-display portion,
Display device. The method of claim 1,
Each of the at least one clock signal wire is connected to a gate electrode of each of the transistors of the first circuit via a metal wire;
Display device. The method of claim 3,
The metal wiring includes the same material as the gate electrode;
Display device The method of claim 1,
The transistor,
A semiconductor layer comprising a predetermined impurity doped region doped with a semiconductor impurity and an intrinsic semiconductor region not doped with the semiconductor impurity, and a gate electrode layer formed over the semiconductor layer with a gate insulating layer interposed therebetween,
One electrode of the capacitor is electrically connected to the impurity doped region,
Display device. The method of claim 5,
The impurity doped region of the semiconductor layer is
A first impurity doped region, and a second impurity doped region formed to face the first impurity doped region and electrically connected to the first impurity doped region in a region not overlapping with the gate electrode layer,
Display device. The method of claim 5,
The gate insulating layer of the transistor is opened or shorted by an electrostatic current flowing through at least one clock signal wire,
Display device. The method of claim 7, wherein
When the gate insulating layer is shorted, the introduced electrostatic current is accumulated in a capacitor including one electrode electrically connected to an impurity doped region of the semiconductor layer.
Display device. A first circuit of a display device comprising a driving circuit for driving a display unit for displaying an image and at least one clock signal wire for transmitting a clock signal to the driving circuit.
At least one transistor electrically connected to each of the at least one clock signal wire and a gate electrode, and
At least one capacitor including one electrode commonly connected to the source and drain electrodes of the transistor and the other electrode to which a predetermined fixed voltage is applied;
The first circuit comprising a. The method of claim 9,
Each of the at least one clock signal wire is connected to a gate electrode of each of the at least one transistor through a metal wire;
First circuit. The method of claim 10,
The metal wiring includes the same material as the gate electrode;
First circuit. The method of claim 9,
The transistor,
A semiconductor layer comprising a predetermined impurity doped region doped with a semiconductor impurity and an intrinsic semiconductor region not doped with the semiconductor impurity, and a gate electrode layer formed over the semiconductor layer with a gate insulating layer interposed therebetween,
Electrostatic current flowing through the at least one clock signal wire opens or shorts the gate insulating layer of the transistor,
First circuit. The method of claim 12,
The impurity doped region of the semiconductor layer is
A first impurity doped region, and a second impurity doped region formed to face the first impurity doped region and electrically connected to the first impurity doped region in a region not overlapping with the gate electrode layer,
First circuit. The method of claim 12,
When the gate insulating layer is shorted, the introduced electrostatic current is accumulated in a capacitor including one electrode electrically connected to an impurity doped region of the semiconductor layer.
First circuit.

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