JP4481638B2 - 垂直接触型積層チップ - Google Patents

垂直接触型積層チップ Download PDF

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Publication number
JP4481638B2
JP4481638B2 JP2003507891A JP2003507891A JP4481638B2 JP 4481638 B2 JP4481638 B2 JP 4481638B2 JP 2003507891 A JP2003507891 A JP 2003507891A JP 2003507891 A JP2003507891 A JP 2003507891A JP 4481638 B2 JP4481638 B2 JP 4481638B2
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JP
Japan
Prior art keywords
contact surface
chip
contact
chip layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003507891A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004531083A (ja
JP2004531083A5 (https=
Inventor
グラッスル，トーマス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giesecke and Devrient GmbH
Original Assignee
Giesecke and Devrient GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giesecke and Devrient GmbH filed Critical Giesecke and Devrient GmbH
Publication of JP2004531083A publication Critical patent/JP2004531083A/ja
Publication of JP2004531083A5 publication Critical patent/JP2004531083A5/ja
Application granted granted Critical
Publication of JP4481638B2 publication Critical patent/JP4481638B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Crushing And Grinding (AREA)
  • Battery Mounting, Suspending (AREA)
  • Bipolar Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2003507891A 2001-06-21 2002-06-20 垂直接触型積層チップ Expired - Fee Related JP4481638B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10130864A DE10130864A1 (de) 2001-06-21 2001-06-21 Vertikal kontaktierte, übereinander gestapelte Chips
PCT/EP2002/006861 WO2003001597A2 (de) 2001-06-21 2002-06-20 Vertikal kontaktierte, übereinander gestapelte chips

Publications (3)

Publication Number Publication Date
JP2004531083A JP2004531083A (ja) 2004-10-07
JP2004531083A5 JP2004531083A5 (https=) 2009-01-08
JP4481638B2 true JP4481638B2 (ja) 2010-06-16

Family

ID=7689553

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003507891A Expired - Fee Related JP4481638B2 (ja) 2001-06-21 2002-06-20 垂直接触型積層チップ

Country Status (6)

Country Link
EP (1) EP1402575B1 (https=)
JP (1) JP4481638B2 (https=)
AT (1) ATE414328T1 (https=)
AU (1) AU2002316990A1 (https=)
DE (2) DE10130864A1 (https=)
WO (1) WO2003001597A2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8124429B2 (en) 2006-12-15 2012-02-28 Richard Norman Reprogrammable circuit board with alignment-insensitive support for multiple component contact types
WO2008137511A1 (en) 2007-05-04 2008-11-13 Crossfire Technologies, Inc. Accessing or interconnecting integrated circuits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61206249A (ja) * 1985-03-11 1986-09-12 Hitachi Ltd 積層半導体集積回路装置
EP0481703B1 (en) * 1990-10-15 2003-09-17 Aptix Corporation Interconnect substrate having integrated circuit for programmable interconnection and sample testing
US5424589A (en) * 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
DE4314907C1 (de) * 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
DE19702121C1 (de) * 1997-01-22 1998-06-18 Siemens Ag Verfahren zur Herstellung von vertikalen Chipverbindungen
DE19813239C1 (de) * 1998-03-26 1999-12-23 Fraunhofer Ges Forschung Verdrahtungsverfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur und vertikale integrierte Schaltungsstruktur
JP2001127243A (ja) * 1999-10-26 2001-05-11 Sharp Corp 積層半導体装置

Also Published As

Publication number Publication date
DE10130864A1 (de) 2003-01-02
EP1402575A2 (de) 2004-03-31
JP2004531083A (ja) 2004-10-07
AU2002316990A1 (en) 2003-01-08
WO2003001597A2 (de) 2003-01-03
EP1402575B1 (de) 2008-11-12
ATE414328T1 (de) 2008-11-15
WO2003001597A3 (de) 2003-12-18
DE50213010D1 (de) 2008-12-24

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