JP4460669B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4460669B2
JP4460669B2 JP07509799A JP7509799A JP4460669B2 JP 4460669 B2 JP4460669 B2 JP 4460669B2 JP 07509799 A JP07509799 A JP 07509799A JP 7509799 A JP7509799 A JP 7509799A JP 4460669 B2 JP4460669 B2 JP 4460669B2
Authority
JP
Japan
Prior art keywords
wiring
insulating film
film
semiconductor device
young
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07509799A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000269337A (ja
JP2000269337A5 (https=
Inventor
祥代 伊藤
正彦 蓮沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP07509799A priority Critical patent/JP4460669B2/ja
Priority to TW089104379A priority patent/TW490710B/zh
Priority to KR10-2000-0013954A priority patent/KR100429750B1/ko
Priority to US09/531,011 priority patent/US6414394B1/en
Publication of JP2000269337A publication Critical patent/JP2000269337A/ja
Priority to US10/085,067 priority patent/US6580171B2/en
Publication of JP2000269337A5 publication Critical patent/JP2000269337A5/ja
Application granted granted Critical
Publication of JP4460669B2 publication Critical patent/JP4460669B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP07509799A 1999-03-19 1999-03-19 半導体装置 Expired - Fee Related JP4460669B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP07509799A JP4460669B2 (ja) 1999-03-19 1999-03-19 半導体装置
TW089104379A TW490710B (en) 1999-03-19 2000-03-10 Semiconductor device
KR10-2000-0013954A KR100429750B1 (ko) 1999-03-19 2000-03-20 반도체 장치
US09/531,011 US6414394B1 (en) 1999-03-19 2000-03-20 Semiconductor device
US10/085,067 US6580171B2 (en) 1999-03-19 2002-03-01 Semiconductor wiring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07509799A JP4460669B2 (ja) 1999-03-19 1999-03-19 半導体装置

Publications (3)

Publication Number Publication Date
JP2000269337A JP2000269337A (ja) 2000-09-29
JP2000269337A5 JP2000269337A5 (https=) 2006-04-27
JP4460669B2 true JP4460669B2 (ja) 2010-05-12

Family

ID=13566336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07509799A Expired - Fee Related JP4460669B2 (ja) 1999-03-19 1999-03-19 半導体装置

Country Status (4)

Country Link
US (2) US6414394B1 (https=)
JP (1) JP4460669B2 (https=)
KR (1) KR100429750B1 (https=)
TW (1) TW490710B (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002164428A (ja) * 2000-11-29 2002-06-07 Hitachi Ltd 半導体装置およびその製造方法
JP2002299441A (ja) * 2001-03-30 2002-10-11 Jsr Corp デュアルダマシン構造の形成方法
JP4731456B2 (ja) * 2006-12-19 2011-07-27 富士通セミコンダクター株式会社 半導体装置
EP2443653A1 (en) * 2009-06-19 2012-04-25 Imec Crack reduction at metal/organic dielectric interface
TWI414047B (zh) * 2010-03-17 2013-11-01 財團法人工業技術研究院 電子元件封裝結構及其製造方法
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9397051B2 (en) * 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
JP6540650B2 (ja) * 2016-10-19 2019-07-10 株式会社村田製作所 半導体装置およびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3092675B2 (ja) * 1990-09-28 2000-09-25 東ソー株式会社 オキシナイトライドガラス及びその製造方法
US5689136A (en) * 1993-08-04 1997-11-18 Hitachi, Ltd. Semiconductor device and fabrication method
JPH07326671A (ja) 1994-05-31 1995-12-12 Texas Instr Inc <Ti> 半導体装置の製造方法
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US5945203A (en) * 1997-10-14 1999-08-31 Zms Llc Stratified composite dielectric and method of fabrication
US6001747A (en) * 1998-07-22 1999-12-14 Vlsi Technology, Inc. Process to improve adhesion of cap layers in integrated circuits
US6037668A (en) * 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure

Also Published As

Publication number Publication date
JP2000269337A (ja) 2000-09-29
US6580171B2 (en) 2003-06-17
KR20000076915A (ko) 2000-12-26
KR100429750B1 (ko) 2004-05-03
US20020130421A1 (en) 2002-09-19
US6414394B1 (en) 2002-07-02
TW490710B (en) 2002-06-11

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