JP4450130B2 - Bonding structure using conductive metal - Google Patents
Bonding structure using conductive metal Download PDFInfo
- Publication number
- JP4450130B2 JP4450130B2 JP2000220921A JP2000220921A JP4450130B2 JP 4450130 B2 JP4450130 B2 JP 4450130B2 JP 2000220921 A JP2000220921 A JP 2000220921A JP 2000220921 A JP2000220921 A JP 2000220921A JP 4450130 B2 JP4450130 B2 JP 4450130B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- electrode
- bonding
- conductor
- electrode land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は、導体金属を用いた接合構造に関し、特に、金属バンプを介して半導体基板の電極ランド部等と半導体素子等とを接合するバンプボンディング法や、半導体素子の電極ランド等とリードフレームの電極ランド等とをワイヤを介して接合するワイヤボンディング法等に用いて好適である。
【0002】
【従来の技術】
基板と半導体素子等の電子部品とを導体金属部材であるバンプやワイヤを介して電気的に接続したり、基板とリードフレームとをワイヤを介して電気的に接続したりするマイクロ接合法では、接合部における双方の金属又は一方の金属を溶融させずに、金属を拡散させることにより接合する。この接合では、接合部に拡散層が形成されて接合が行われており、その様な接合方法としては、マイクロバンプを用いたボンディング法やワイヤボンディング法がある。
【0003】
図5は、一般的なマイクロバンプを用いたボンディングの構造を示す概略断面図である。図5に示すように、基板101に形成された電極ランド102上に金属バンプ103が形成され、この金属バンプ103を介して電子部品104と電極ランド102とが接合されている。この場合、通常、電極ランド102と金属バンプ103とは異なる金属であり、電極ランド102と金属バンプ103とは熱圧着や超音波振動等によって、電極ランド102の金属と金属バンプ103の金属とが拡散されて接合されている。
【0004】
この様な、金属同士を拡散により接合する場合には、金属間の接合を容易にするために、接合部において互いに拡散性の高い金属を組み合わせるのが一般的である。図6は、基板101と電子部品104との接合において、互いに拡散性の高い金属を電極ランド102と金属バンプ103の金属として組み合わせた場合(例えば、電極ランド102がAl等、金属バンプ103がAu等)の接合構造を示す概略断面図であって、(a)は接合直後の状態であり、(b)は製品使用時における高温環境下に保持した後の状態である。
【0005】
図6(a)に示すように、拡散性の高い金属を組み合わせているため、たとえ低い加熱温度や振動エネルギーで接合しても、接合直後から良好に接合するために必要な拡散層105の厚さL1を有することができ、接合性に優れている。その反面、図6(b)に示すように、製品使用時の高温環境下では拡散層105が成長し過ぎて過大な厚さL2になり、合金層が形成されて接合部が脆くなったり、ボイド106が形成されて接合部が破壊されたりする。その結果、接合部分の長期信頼性が損なわれやすい。
【0006】
そこで、製品の高温使用環境下での信頼性を高めるために、接合部において拡散性の低い金属を組み合わせる方法がある。図7は、この拡散性の低い金属を組み合わせた場合(例えば、電極ランド102がCu等、金属バンプ103がAu等)の接合構造を示す概略断面図であって、(a)は接合直後の状態であり、(b)は製品使用時における高温環境下に保持した後の状態である。
【0007】
図7(a)に示すように、拡散性の低い金属を用いているため、接合直後においては拡散層105の厚さL3が非常に薄くて接合性に劣るため、接合時の歩留りが低下してしまう。しかし、図7(b)に示すように、拡散層105の成長が遅いため、製品使用時の高温下で拡散層105が接合性を維持するのに適正な厚さL4である時間が長く、長期信頼性に優れている。
【0008】
【発明が解決しようとする課題】
つまり、拡散による金属間の接合においては、拡散性の高い金属を組み合わせた場合は、接合時の金属間の接合性が良く生産性に優れるが、製品使用時の信頼性は拡散性の低い金属を組み合わせた場合よりも劣る。一方、拡散性の低い金属を組み合わせた場合は、接合時の金属間の接合性が低いため、拡散性の高い金属を組み合わせた場合よりも生産性が劣るが、製品使用時の信頼性は優れている。
【0009】
本発明は、上記問題点に鑑み、導体金属を用いた接合において、生産性と製品使用時の信頼性とが共に優れた接合構造を提供することを目的とする。
【0010】
上記目的を達成するため、請求項1に記載の発明では、表面側に導体金属からなる電極ランド(21、22)を形成した第1の部材(1)と、導体金属部材(3、7)を介して電極ランドと接合した第2の部材(5)とを備える導体金属を用いた接合構造において、導体金属部材を、金を主成分とする金属とし、1つの導体金属部材に対応する電極ランドを、アルミニウムを主成分とする金属、錫、及び、半田のうちのいずれか1種類よりなる第1の電極ランド(21)と、銅を主成分とする金属、ニッケルを主成分とする金属、パラジウム、及び、白金のうちのいずれか1種類よりなる第2の電極ランド(22)との2種類から構成し、第1の電極ランドと導体金属部材との金属の拡散性を第2の電極ランドと導体金属部材との金属の拡散性より高くし、第1の電極ランドおよび第2の電極ランドと1つの導体金属部材とを接合していることを特徴としている。
【0011】
本発明では、導体金属部材を、金を主成分とする金属とし、導体金属部材との拡散性が高い第1の電極ランド(21)により、接合時における電極ランドと導体金属部材との接合性を良好に確保し、導体金属部材との拡散性が低い第2の電極ランド(22)により、製品使用時における電極ランドと導体金属部材との接合性を良好に確保することができる。従って、生産性と製品使用時の信頼性とが共に優れた接合構造を提供することができる。
【0012】
また、請求項2に記載の発明のように、請求項1の発明の導体金属を用いた接合構造を半導体装置に適用することができる。
【0015】
また、請求項3に記載の発明のように、請求項1又は2の発明において、導体金属部材としては、金属バンプ(3)又は、ボンディングワイヤ(7)を適用することができる。
【0016】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【0017】
【発明の実施の形態】
(第1実施形態)
以下、図に示す実施形態について説明する。本実施形態は、半導体基板と半導体素子との接合を金属バンプを用いて行う場合に本発明を適用したものとして説明する。図1は本実施形態の半導体装置における接合構造を示す概略断面図であって、(a)は接合直後の状態であり、(b)は製品使用時における高温環境下に保持した後の状態である。
【0018】
図1に示すように、半導体基板(本発明でいう、第1の部材)1の表面側に対して、導体金属である金属膜からなる2種類の電極ランド21、22が形成されている。また、2種類の電極ランド21、22の各々と接合するように導体金属部材としての金属バンプ3が形成されている。
【0019】
この電極ランド21、22と金属バンプ3とは、電極ランド21、22と金属バンプ3の一方或は双方の金属が溶融されずに固相接合されている。つまり、電極ランド21、22と金属バンプ3との境界において、電極ランド21、22に含まれる金属と金属バンプ3に含まれる金属とが相互に拡散して拡散層41、42が形成されている。
【0020】
また、金属バンプ3上には半導体素子(本発明でいう、第2の部材)5が搭載されており、金属バンプ3と半導体素子5における図示しない導体部とが電気的に接続されている。
【0021】
次に、この2種類の電極ランド21、22について説明する。2種類の電極ランド21、22は、各々の電極ランド21、22の金属と金属バンプ3の金属との拡散性が異なる。2種類の電極ランド21、22のうち、第1の電極ランド21は金属バンプ3との金属の拡散性が高く、第2の電極ランド22は金属バンプ3との金属の拡散性が低い。この様な、金属バンプ3と第1及び第2の電極ランド21、22との材質の組み合わせの例を、図2に示す。
【0022】
図2に示すように、金属バンプ3として、純度98%以上のAu(金)を用いる場合は、第1の電極ランド21として、純Al(アルミニウム)やAlを主成分とし、Al以外の成分が3%以下の合金、或はSn(錫)や半田を用いることができる。また、第2の電極ランド22として、純Cu(銅)やCuを主成分とし、Cu以外の成分が3%以下の合金、或は、純Ni(ニッケル)やNiを主成分とし、Ni以外の成分が15%以下の合金、又はPd(パラジウム)やPt(白金)を用いることができる。
【0023】
また、金属バンプ3として、Snや半田を用いる場合は、第1の電極ランド21として、純度98%以上のAuを用いることができ、第2の電極ランド22として、純NiやNiを主成分とし、Ni以外の成分が15%以下の合金を用いることができる。
【0024】
次に、この様な接合構造を形成する方法について一例を示す。まず、半導体基板1上に印刷等により第1及び第2の電極ランド21、22を形成する。その後、第1及び第2の電極ランド21、22上に、金属バンプ3を形成するためのワイヤを備えたキャピラリを用意し、キャピラリの先端でワイヤの先端部にボール部を形成する。そして、ボール部を第1及び第2の電極ランド21、22に熱圧着したり超音波圧着したりして金属バンプ3を形成する。続いて、金属バンプ3に半導体素子5を搭載することにより、図1に示す半導体装置における接合構造が完成する。
【0025】
ところで、本実施形態によれば、金属バンプ3との金属の拡散性が異なる2種類の電極ランド21、22を用いているため、接合の初期においても製品使用時においても、良好な接合性を確保することができる。以下に、この接合性の確保について詳しく述べる。
【0026】
図1(a)に示すように、接合の初期では、第2の電極ランド22と金属バンプ3との境界においては、第2の電極ランド22と金属バンプ3との間の金属の拡散性が低いため、拡散層42の厚さが薄くて接合が不十分である。しかし、第1の電極ランド21と金属バンプ3との境界においては、第1の電極ランド21と金属バンプ3との間の金属の拡散性が高いため、接合時の加熱温度や振動エネルギーが低くても、良好な接合が得られる程度に拡散層41の厚さを確保することができる。その結果、接合の初期において良好に接合を確保することができ、生産性に優れている。
【0027】
また、製品使用時における高温環境下では、第1及び第2の電極ランド21、22と金属バンプ3との間の金属の拡散が進行する。この際、金属の拡散性が高い第1の電極ランド21と金属バンプ3との間では拡散層41が成長し過ぎて、図1(b)に示すように、合金層を生成して脆くなったりボイド6を形成して接合部が破壊することがある。しかし、第2の電極ランド22と金属バンプ3との間では拡散層42の成長が遅いため、良好な接合が得られる程度に拡散層42の厚さを確保することができる。その結果、製品使用時の信頼性に優れている。
【0028】
このように、接合の初期においては第1の電極ランド21により、金属バンプ3と良好な接合を確保することができ、製品使用時においては遅効的に金属が拡散する第2の電極ランド22により、金属バンプ3との接合性を確保することができる。従って、生産性と製品使用時の信頼性とが共に優れた接合構造を提供することができる。
【0029】
なお、第1及び第2の電極ランド21、22と金属バンプ3との接合に必要な面積が確保されれば良く、第1及び第2の電極ランド21、22は正確に位置合わせする必要はない。図3に、第1及び第2の電極ランド21、22の配置の変形例を概略断面図で示す。図3(a)に示すように、第1及び第2の電極ランド21、22間に隙間があっても良い。また、図3(b)に示すように、第1の電極ランド21と第2の電極ランド22との間に段差があったり、図3(c)に示すように、一方の電極ランド21が他方の電極ランド22にかぶさっていても良い。図3(b)や(c)の場合は、接合時に金属バンプ3を塑性変形させれば良い。なお、図3では拡散層を省略している。
【0030】
(第2実施形態)
上記第1実施形態では、半導体基板1と半導体素子5との電気的な接続を金属バンプ3を用いて行う場合に本発明を適用したが、半導体基板等でワイヤボンディングする場合にも本発明を適用することができる。図4に、ワイヤボンディングを行う場合の接合構造を概略断面図にて示す。
【0031】
図4に示すように、図1と同様にして、半導体基板1上に第1の電極ランド21と第2の電極ランド22とが形成されている。そして、ボンディングワイヤ(本発明でいう導体金属部材)7のボール部7aが第1及び第2の電極ランド21、22の両方に接合されている。このように、ワイヤボンディングを行う場合にも、ボンディングワイヤ7との金属の拡散性が異なる第1及び第2の電極ランド21、22とボール部7aとを接合することにより、第1実施形態と同様の効果を発揮することができる。
【0032】
なお、ボンディングワイヤ7のボール部7aの材料は、図2に示した金属バンプ3の材料と同様のものを用いることができる。
【0033】
(他の実施形態)
上記各実施形態では、電極ランド21、22は半導体基板1上に形成されていたが、プリント基板、セラミック基板やリードフレーム等に形成された電極ランドにも本実施形態の構造を適用することができる。また、半導体素子だけではなく、一般的な電子部品を搭載する際にも適用することができる。
【0034】
また、上記各実施形態では、2種類の電極ランド21、22を形成する例について示したが、金属バンプ3やボンディングワイヤ7との金属の拡散性が異なる3種類以上の電極ランドを形成しても良い。
【0035】
また、本発明は、突起状の微細な金属を用いて電気的な接続を行う場合に広く適用することができ、例えば、TAB(tape automated bonding)用のバンプやフリップチップ用のバンプを用いる場合にも適用することができる。
【図面の簡単な説明】
【図1】第1実施形態の導体金属を用いた接合構造を示す概略断面図である。
【図2】金属バンプと電極ランドとの材質の組み合わせを示す図表である。
【図3】第1実施形態の導体金属を用いた接合構造の他の例を示す概略断面図である。
【図4】第2実施形態の導体金属を用いた接合構造を示す概略断面図である。
【図5】従来のマイクロバンプを用いた接合構造を示す概略断面図である。
【図6】拡散性の高い金属を組み合わせた場合の接合構造を示す概略断面図である。
【図7】拡散性の低い金属を組み合わせた場合の接合構造を示す概略断面図である。
【符号の説明】
1…半導体基板、3…金属バンプ、5…半導体素子、
7…ボンディングワイヤ、21…第1の電極ランド、22…第2の電極ランド。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bonding structure using a conductive metal, and in particular, a bump bonding method for bonding an electrode land portion of a semiconductor substrate and a semiconductor element via a metal bump, an electrode land of a semiconductor element, and a lead frame. It is suitable for use in a wire bonding method in which an electrode land or the like is bonded via a wire.
[0002]
[Prior art]
In the micro-joining method in which a substrate and an electronic component such as a semiconductor element are electrically connected via a bump or wire which is a conductive metal member, or a substrate and a lead frame are electrically connected via a wire, It joins by diffusing a metal, without melting both the metals in a joined part, or one metal. In this bonding, a diffusion layer is formed in the bonding portion and bonding is performed. As such a bonding method, there are a bonding method using a micro bump and a wire bonding method.
[0003]
FIG. 5 is a schematic cross-sectional view showing a bonding structure using a general micro bump. As shown in FIG. 5,
[0004]
When such metals are joined by diffusion, in order to facilitate joining between the metals, it is common to combine metals having high diffusibility at the joint. FIG. 6 shows a case where a metal having high diffusibility is combined as the metal of the
[0005]
As shown in FIG. 6 (a), since a highly diffusible metal is combined, the thickness of the
[0006]
Therefore, in order to increase the reliability of the product in a high temperature use environment, there is a method of combining a metal having low diffusibility at the joint. FIG. 7 is a schematic cross-sectional view showing a bonding structure when this low diffusion metal is combined (for example, the
[0007]
As shown in FIG. 7A, since a metal having low diffusibility is used, the thickness L3 of the
[0008]
[Problems to be solved by the invention]
In other words, when joining metals by diffusion, when a metal with high diffusibility is combined, the metal-to-metal joining at joining is good and the productivity is excellent, but the reliability at the time of use of the product is low. It is inferior to the case of combining. On the other hand, the combination of metals with low diffusibility is less productive than the combination of metals with high diffusibility because the bondability between metals during bonding is low, but the reliability when using the product is excellent. ing.
[0009]
In view of the above problems, an object of the present invention is to provide a joint structure in which both productivity and reliability during use of a product are excellent in joining using a conductor metal.
[0010]
To achieve the above object, according to the first aspect of the present invention, a first member (1) having electrode lands (21, 22) made of a conductive metal on the surface side, and a conductive metal member (3, 7). In a joint structure using a conductor metal comprising a second member (5) joined to an electrode land via an electrode, the conductor metal member is a metal whose main component is gold, and an electrode corresponding to one conductor metal member The land is a first electrode land (21) made of any one of a metal mainly composed of aluminum, tin, and solder, a metal mainly composed of copper, and a metal mainly composed of nickel. , Palladium, and the second electrode land (22) made of any one of platinum, and the metal diffusibility between the first electrode land and the conductive metal member is the second. Metal diffusion between electrode land and conductor metal member The first electrode land and the second electrode land are bonded to one conductor metal member.
[0011]
In the present invention, the conductive metal member is a metal mainly composed of gold, and the first electrode land (21) having high diffusibility with the conductive metal member is used to bond the electrode land and the conductive metal member at the time of bonding. The second electrode land (22) having a low diffusibility with the conductive metal member can ensure a good bondability between the electrode land and the conductive metal member during product use. Therefore, it is possible to provide a joint structure that is excellent in both productivity and reliability during product use.
[0012]
As in the invention described in claim 2, the junction structure using the conductor metal of the invention in
[0015]
Further, as in the third aspect of the invention, in the first or second aspect of the invention, the metal bump (3) or the bonding wire (7) can be applied as the conductive metal member.
[0016]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, embodiments shown in the drawings will be described. In the present embodiment, description will be made assuming that the present invention is applied to a case where a semiconductor substrate and a semiconductor element are bonded using metal bumps. FIG. 1 is a schematic cross-sectional view showing a junction structure in the semiconductor device of the present embodiment, where (a) is a state immediately after joining, and (b) is a state after being held in a high-temperature environment during product use. is there.
[0018]
As shown in FIG. 1, two types of electrode lands 21 and 22 made of a metal film, which is a conductor metal, are formed on the surface side of a semiconductor substrate (first member in the present invention) 1. Metal bumps 3 as conductive metal members are formed so as to be joined to each of the two types of electrode lands 21 and 22.
[0019]
The electrode lands 21 and 22 and the
[0020]
A semiconductor element (second member in the present invention) 5 is mounted on the
[0021]
Next, the two types of electrode lands 21 and 22 will be described. The two types of electrode lands 21 and 22 differ in the diffusibility between the metal of each
[0022]
As shown in FIG. 2, when Au (gold) having a purity of 98% or more is used as the
[0023]
When Sn or solder is used as the
[0024]
Next, an example of a method for forming such a joint structure is shown. First, the first and second electrode lands 21 and 22 are formed on the
[0025]
By the way, according to the present embodiment, since the two types of electrode lands 21 and 22 having different metal diffusibility with the
[0026]
As shown in FIG. 1A, at the initial stage of bonding, the metal diffusivity between the
[0027]
In addition, metal diffusion between the first and second electrode lands 21 and 22 and the
[0028]
As described above, the
[0029]
It is only necessary to secure an area necessary for joining the first and second electrode lands 21 and 22 and the
[0030]
(Second Embodiment)
In the first embodiment, the present invention is applied when the electrical connection between the
[0031]
As shown in FIG. 4, the
[0032]
The material of the
[0033]
(Other embodiments)
In each of the above embodiments, the electrode lands 21 and 22 are formed on the
[0034]
In each of the above embodiments, an example in which two types of electrode lands 21 and 22 are formed has been described. However, three or more types of electrode lands having different metal diffusivities with the
[0035]
In addition, the present invention can be widely applied to the case where electrical connection is performed using a fine metal in a protruding shape. For example, a bump for TAB (tape automated bonding) or a bump for flip chip is used. It can also be applied to.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a joint structure using a conductor metal according to a first embodiment.
FIG. 2 is a chart showing combinations of materials of metal bumps and electrode lands.
FIG. 3 is a schematic cross-sectional view showing another example of the joint structure using the conductor metal according to the first embodiment.
FIG. 4 is a schematic cross-sectional view showing a joint structure using a conductor metal according to a second embodiment.
FIG. 5 is a schematic cross-sectional view showing a bonding structure using a conventional micro bump.
FIG. 6 is a schematic cross-sectional view showing a joint structure in the case of combining highly diffusible metals.
FIG. 7 is a schematic cross-sectional view showing a joint structure in the case of combining low diffusion metals.
[Explanation of symbols]
DESCRIPTION OF
7: Bonding wire, 21: First electrode land, 22: Second electrode land
Claims (3)
前記導体金属部材が金を主成分とする金属であり、
1つの前記導体金属部材に対応する前記電極ランドが、アルミニウムを主成分とする金属、錫、及び、半田のうちのいずれか1種類よりなる第1の電極ランド(21)と、銅を主成分とする金属、ニッケルを主成分とする金属、パラジウム、及び、白金のうちのいずれか1種類よりなる第2の電極ランド(22)との2種類よりなり、前記第1の電極ランドと前記導体金属部材との金属の拡散性が前記第2の電極ランドと前記導体金属部材との金属の拡散性より高くされており、
前記第1の電極ランドおよび前記第2の電極ランドと前記1つの導体金属部材とが接合されていることを特徴とする導体金属を用いた接合構造。A first member (1) in which electrode lands (21, 22) made of a conductive metal are formed on the surface side, and a second member joined to the electrode lands via the conductive metal members (3, 7) ( 5) In a junction structure using a conductor metal comprising:
The conductor metal member is a metal mainly composed of gold;
The electrode land corresponding to one conductor metal member includes a first electrode land (21) made of any one of a metal mainly composed of aluminum, tin, and solder, and copper as a main component. And the second electrode land (22) made of any one of a metal containing nickel as a main component, palladium, and platinum, and the first electrode land and the conductor. The metal diffusibility with the metal member is higher than the metal diffusivity between the second electrode land and the conductor metal member,
Junction structure using a conductive metal, characterized in that said first electrode lands and the second electrode orchid de and the one conductive metal member is bonded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000220921A JP4450130B2 (en) | 2000-07-21 | 2000-07-21 | Bonding structure using conductive metal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000220921A JP4450130B2 (en) | 2000-07-21 | 2000-07-21 | Bonding structure using conductive metal |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002043365A JP2002043365A (en) | 2002-02-08 |
JP4450130B2 true JP4450130B2 (en) | 2010-04-14 |
Family
ID=18715436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000220921A Expired - Fee Related JP4450130B2 (en) | 2000-07-21 | 2000-07-21 | Bonding structure using conductive metal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4450130B2 (en) |
-
2000
- 2000-07-21 JP JP2000220921A patent/JP4450130B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2002043365A (en) | 2002-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4766725B2 (en) | Manufacturing method of electronic parts | |
US8298947B2 (en) | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles | |
JP2915888B1 (en) | Wiring board and manufacturing method thereof | |
JPH11219420A (en) | Ic card module, ic card and their manufacture | |
JPH11328352A (en) | Connection structure between antenna and ic chip, and ic card | |
US8399996B2 (en) | Chip carrier | |
US6080494A (en) | Method to manufacture ball grid arrays with excellent solder ball adhesion for semiconductor packaging and the array | |
JPH09162230A (en) | Electronic circuit device and its manufacturing method | |
JP4450130B2 (en) | Bonding structure using conductive metal | |
JP2001230270A (en) | Semiconductor device and its manufacturing method | |
JP4012527B2 (en) | Manufacturing method of electronic parts | |
JP3585806B2 (en) | Wiring board with pins | |
JPH11103160A (en) | Solder member and printed wiring board | |
JP2716355B2 (en) | Method for manufacturing semiconductor device | |
JP2894172B2 (en) | Semiconductor device | |
JPH11204941A (en) | Manufacture of circuit board | |
CN218101252U (en) | Pre-attached solder copper transition piece | |
JPH11260964A (en) | Semiconductor package | |
JP2830221B2 (en) | Mounting structure of hybrid integrated circuit | |
JP3947436B2 (en) | Semiconductor device | |
JP2002368038A (en) | Flip-chip mounting method | |
JP2010141112A (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP3622160B2 (en) | Ceramic substrate and manufacturing method thereof | |
JP2001291800A (en) | Package for electronic component | |
JPH11274347A (en) | Semiconductor package and method for forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060927 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080804 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090519 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090710 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100106 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100119 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130205 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140205 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |