JP2716355B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2716355B2 JP2716355B2 JP5318950A JP31895093A JP2716355B2 JP 2716355 B2 JP2716355 B2 JP 2716355B2 JP 5318950 A JP5318950 A JP 5318950A JP 31895093 A JP31895093 A JP 31895093A JP 2716355 B2 JP2716355 B2 JP 2716355B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pellet
- plating layer
- lead frame
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0133—Ternary Alloys
Landscapes
- Die Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
にに関し、特に化合物半導体ペレットをリードフレーム
にマウントする方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for mounting a compound semiconductor pellet on a lead frame.
【０００２】[0002]
【従来の技術】従来、化合物半導体ペレットをリードフ
レームにマウントする際、一つの例として図３に示す様
に化合物半導体ペレット（３３）の裏面にＴｉ−Ｐｔ−
Ａｕ層（３４）付け、リードフレーム（３１）のマウン
トする部分（３１´）に導電性樹脂例えば銀ペースト
（３２）を介し、化合物半導体ペレット（３３）をリー
ドフレームにマウントしていた。2. Description of the Related Art Conventionally, when a compound semiconductor pellet is mounted on a lead frame, as one example, as shown in FIG. 3, a Ti-Pt-
The compound semiconductor pellet (33) was mounted on the lead frame via the conductive resin, for example, the silver paste (32), on the portion (31 ') of the lead frame (31) to which the Au layer (34) was attached.
【０００３】また、別の例として金−錫合金を前記導電
性樹脂に代えてソルダーとして用いてマウントしてい
た。また、ソルダーを用いずにマウントする方法とし
て、図４のようにＮｉメッキ（４２）されたＣｕベース
（４１）に形成されたペレットマウント領域（半導体ペ
レットをマウントする領域）にＳｎメッキ層（４４）を
施し、さらに、その上に均一にＡｕメッキ層（４３）を
一様に施したパッケージを用い、そのＳｎメッキ層（４
４）が施されている部分に、半導体ペレット（４５）を
位置させ加熱することにより、Ｓｎ（４４）とＡｕ（４
３）が金ー錫合金となって溶融し、半導体ペレット（４
５）をパッケージに固着させる方法がある（例えば特開
平４−６２８５３）。一方バイポーラトランジスタ等Ｓ
ｉペレットにおいては、Ｓｉペレットの裏面に比較的厚
いＡｕメッキ層を形成し、マウント時の加熱により、Ａ
ｕメッキ層とＳｉペレット自体の共晶反応によりＡｕ−
Ｓｉ合金層を形成し、特にソルダーを用いずに通常マウ
ントを行っている。As another example, a gold-tin alloy has been used as a solder in place of the conductive resin and mounted. As a method of mounting without using a solder, as shown in FIG. 4, an Sn plating layer (44) is formed on a pellet mounting region (region for mounting a semiconductor pellet) formed on a Cu base (41) plated with Ni (42). ), And further, using a package in which an Au plating layer (43) is uniformly applied thereon, and using the Sn plating layer (4
The semiconductor pellets (45) are positioned and heated in the portion where 4) is applied, so that Sn (44) and Au (4
3) becomes a gold-tin alloy and melts, and the semiconductor pellet (4
5) is fixed to a package (for example, JP-A-4-62853). On the other hand, S such as a bipolar transistor
In the i-pellet, a relatively thick Au plating layer is formed on the back surface of the Si pellet, and A
Au-due to the eutectic reaction between the u-plated layer and the Si pellet itself
A Si alloy layer is formed, and mounting is usually performed without using solder.
【０００４】[0004]
【発明が解決しようとする課題】従来、ＧａＡｓペレッ
トにおけるＡｇペースト、Ａｕ−Ｓｎソルダーを用いた
マウントにおいては、Ａｇペースト、ソルダー量の多少
により、ペレットへのソルダーはい上がりで配線をショ
ートさせたり、ケース内でのソルダー流れによりボンデ
ィングができなくなる等の不良が発生している。また、
従来例（特開平４−６２８５３）における、ソルダーレ
スによる、ＧａＡｓペレットのマウント法については例
えば、図５の様にリードフレーム上に従来例（特開平４
−６２８５３）にある様なＳｎＡｎメッキ層を形成し、
マウントを実施した場合（Ａ部（５３））マウントステ
ージ（５１）の熱により、まだマウントを行わない隣の
Ｓｎ−Ａｎメッキ層（Ｂ部、（５３））においてペレッ
トマウント前にＡｕメッキ層とＳｎメッキ層が共晶反応
し溶融し表面が酸化し、次にチップをマウントする際、
信頼性の高いマウントが困難となる問題がある。Conventionally, in a mount using an Ag paste and an Au-Sn solder in a GaAs pellet, depending on the amount of the Ag paste and the amount of solder, the solder on the pellet rises and short-circuits the wire. Failures such as the inability to perform bonding due to solder flow in the case have occurred. Also,
Regarding a method of mounting a GaAs pellet by solderless in a conventional example (Japanese Patent Application Laid-Open No. 4-62853), for example, as shown in FIG.
-62853) to form a SnAn plating layer,
When mounting is performed (part A (53)), due to the heat of the mount stage (51), an Au plating layer is formed on the adjacent Sn-An plating layer (part B, (53)) which is not yet mounted before pellet mounting. When the Sn plating layer reacts and melts due to the eutectic reaction and the surface is oxidized, then when mounting the chip,
There is a problem that mounting with high reliability becomes difficult.
【０００５】また前記のごとくソルダーレスマウント方
式を用いているＳｉペレットのラインにおいてはＡｇペ
ースト、もしくはＡｕ−Ｓｎソルダー等を用いてマウン
トするＧａＡｓペレットはソルダーレスマウント方式を
用いているＳｉペレット対応の生産ラインへの展開が困
難であった。In the line of Si pellets using the solderless mounting method as described above, GaAs pellets mounted using an Ag paste or Au-Sn solder are compatible with Si pellets using the solderless mounting method. It was difficult to deploy to production lines.
【０００６】[0006]
【課題を解決するための手段】本発明は、半導体ペレッ
トの一表面に第１の金属層を設け、前記半導体ペレット
を支持する支持基体の一表面に前記第１の金属層と共晶
反応により共晶合金を形成する第２の金属層を設け、前
記半導体ペレットと前記支持基体との間に１層の共晶合
金のみ形成するように前記第１の金属層と前記第２の金
属層とを共晶反応を呈する温度にて接合させることを特
徴とする半導体装置の製造方法である。 According to the present invention, a first metal layer is provided on one surface of a semiconductor pellet.
A second metal layer that forms a eutectic alloy with the first metal layer and the eutectic reaction to one surface of a supporting substrate for supporting the provided pre
A single layer of eutectic between the semiconductor pellet and the supporting substrate
The first metal layer and the second gold are formed so that only gold is formed.
It is a manufacturing method of a semiconductor device according to claim that the genus layer Ru are bonded at a temperature exhibiting a eutectic reaction.
【０００７】[0007]
【作用】本発明によれば、半導体チップをリードフレー
ムにマウントする際、半導体チップ裏面に、第１の金属
層を設け、さらに、リードフレームのチップをマウント
する箇所の表面に第１の金属層と共晶反応により共晶合
金を形成する第２の金属層を設け、両者をその共晶反応
を呈する温度にて接合させ、ペレット、リードフレーム
間に共晶合金を形成させので、ソルダーレスマウントが
可能でソルダーのはい上がり、ソルダー流れ不良が撲滅
できるものであり、さらに、ペレット裏面のＡｕメッキ
層とリードフレームのＳｎメッキ層が接合し、加熱され
て共晶反応を程するので、従来例でみられたようなマウ
ント前のＡｕＳｎ合金の溶融、酸化が起こらず、信頼性
の高いマウントが実現されるものである。According to the present invention, when a semiconductor chip is mounted on a lead frame, a first metal layer is provided on the back surface of the semiconductor chip, and the first metal layer is formed on the surface of the lead frame where the chip is mounted. And a second metal layer that forms a eutectic alloy by a eutectic reaction, and the two are joined at a temperature that exhibits the eutectic reaction, and a eutectic alloy is formed between the pellet and the lead frame. It is possible to eliminate solder rising and solder flow failure. Furthermore, the Au plating layer on the back surface of the pellet and the Sn plating layer on the lead frame are joined and heated to perform the eutectic reaction. As a result, the AuSn alloy before mounting does not melt or oxidize, and a highly reliable mount is realized.
【０００８】またＳｉ対応のソルダーレスマウントライ
ンにも適用可能となり、従来困難であったソルダーレス
マウント方式を用いたＳｉチップ等の量産ラインにもＧ
ａＡｓペレットを適用できるものである。即ち、ＧａＡ
ｓペレット裏面のＡｕメッキ層とリードフレーム上のＳ
ｎメッキ層との間に共晶反応により、Ａｕ−Ｓｎ合金層
を形成させ、マウントするものである。Further, the present invention can be applied to a solderless mount line corresponding to Si, and can be applied to a mass production line of Si chips and the like using a solderless mount method, which has been difficult in the past.
aAs pellets can be applied. That is, GaA
Au plating layer on the back of the pellet and S on the lead frame
An Au-Sn alloy layer is formed by eutectic reaction with the n-plated layer and mounted.
【０００９】[0009]
【実施例】本発明について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
【実施例１】図１（ａ）は本発明において用いるリード
フレームの実施例の断面図である。まずリードフレーム
（１１）の例えばＦｅ，Ｎｉ合金の化合物半導体ペレッ
トを実装する部分（１１´）に、錫をマスクパターンを
用いてメッキし、Ｓｎメッキ層（１２）を設ける。さら
に化合物半導体ペレット（１３）裏面にＴｉ−Ｐｔ−Ａ
ｕスパッタ層（１５）を介しＡｕメッキ層（１４）を設
ける。Embodiment 1 FIG. 1A is a sectional view of an embodiment of a lead frame used in the present invention. First, tin is plated using a mask pattern on a portion (11 ') of a lead frame (11) on which compound semiconductor pellets of, for example, Fe and Ni alloys are mounted, to provide a Sn plating layer (12). Further, Ti-Pt-A is formed on the back surface of the compound semiconductor pellet (13).
An Au plating layer (14) is provided via a u-sputtering layer (15).
【００１０】次に図１（ｂ）は化合物半導体ペレットを
マウントした時の断面図である。リードフレーム（１
１）上のＳｎメッキ層（１２）と化合物半導体ペレット
（１３）の裏面のＡｕメッキ層（１４）を合わせ、セッ
トし、ＡｕとＳｎの共晶温度に加熱することにより、Ｓ
ｎ層（１２）とＡｕ層（１４）との間に共晶反応を起こ
させ、Ａｕ−Ｓｎ合金層（１６）を形成することにより
化合物半導体ペレット（１３）をリードフレーム（１１
´）上にマウントしている。本実施例によれば、ソルダ
ーレスマウントが可能でソルダーのはい上がり、ソルダ
ー流れ不良が撲滅し、さらに、ペレット裏面のＡｕメッ
キ層とリードフレームのＳｎメッキ層が接合し、加熱さ
れて共晶反応を程するので、従来例でみられたようなマ
ウント前のＡｕＳｎ合金の溶融、酸化が起こらず、信頼
性の高いマウントが実現される。またＳｉ対応のソルダ
ーレスマウントラインにも適用可能となり、従来困難で
あったソルダーレスマウント方式を用いたＳｉチップ等
の量産ラインにもＧａＡｓペレットを適用できる。Next, FIG. 1B is a sectional view when a compound semiconductor pellet is mounted. Lead frame (1
1) The upper Sn plating layer (12) and the Au plating layer (14) on the back surface of the compound semiconductor pellet (13) are put together, set, and heated to the eutectic temperature of Au and Sn to obtain S.
A eutectic reaction is caused between the n-layer (12) and the Au layer (14) to form an Au-Sn alloy layer (16), whereby the compound semiconductor pellet (13) is connected to the lead frame (11).
´) Mounted on top. According to the present embodiment, solderless mounting is possible, solder jumps up, solder flow failure is eliminated, and the Au plating layer on the back of the pellet and the Sn plating layer on the lead frame are joined and heated to cause eutectic reaction. Therefore, melting and oxidation of the AuSn alloy before mounting as in the conventional example do not occur, and a highly reliable mounting is realized. Further, the present invention can be applied to a solderless mount line corresponding to Si, and a GaAs pellet can be applied to a mass production line of a Si chip or the like using a solderless mount method, which has been difficult in the past.
【００１１】[0011]
【実施例２】また図２は、本発明の第２の実施例におけ
る平面図および断面図を示す。リードフレーム（２１）
のリードの部分にＳｎメッキ層（２２）を設ける。一方
化合物半導体ペレットの電極パッド領域に厚Ａｕメッキ
層（２３）を施し、この部分をリード上のＳｎメッキ領
域（２２）に合わせ、セットし、Ａｕ−Ｓｎ共晶反応温
度に加熱することで、両者の間に共晶合金層が形成さ
れ、リードとペレットが固着される。その後従来のモー
ルド技術を用いてモールド型半導体装置を製造できる。
この実施例の方法によれば、第１の実施例と同様、ソル
ダーに起因する不良をなくすことができ、さらにワイヤ
ーボンディングが不要となり、ボンディングのインダク
タンス成分が低減でき、高周波デバイスにも適用範囲が
広がりかつ組み立て工程の短縮につながる。Embodiment 2 FIG. 2 shows a plan view and a sectional view of a second embodiment of the present invention. Lead frame (21)
Is provided with a Sn plating layer (22) at the lead portion of FIG. On the other hand, a thick Au plating layer (23) is applied to the electrode pad region of the compound semiconductor pellet, and this portion is set and adjusted to the Sn plating region (22) on the lead, and heated to the Au-Sn eutectic reaction temperature. A eutectic alloy layer is formed between them, and the lead and the pellet are fixed. Thereafter, a molded semiconductor device can be manufactured by using a conventional molding technique.
According to the method of this embodiment, similarly to the first embodiment, it is possible to eliminate defects caused by solder, further eliminate the need for wire bonding, reduce the inductance component of bonding, and have a wide application range for high-frequency devices. Spreads and shortens the assembly process.
【００１２】[0012]
【発明の効果】以上、説明したように本発明によれば、
モールドＰＫＧリードフレームのペレットマウント部に
Ｓｎメッキ層、ＧａＡｓペレット裏面にＡｕメッキ層を
設けることによってＡｕ−Ｓｎ共晶反応による合金層を
形成させ、ソルダーレスマウントすることができ、従来
起こっていたソルダーはい上がり、ソルダー流れ不良な
どを撲滅でき、さらに従来適用できなかったソルダーレ
スマウント方式を用いたＳｉチップ用生産ライン等に、
ＧａＡｓペレットを適用可能となるという効果を奏する
ものである。As described above, according to the present invention,
By providing an Sn plating layer on the pellet mounting portion of the molded PKG lead frame and an Au plating layer on the back surface of the GaAs pellet, an alloy layer can be formed by an Au-Sn eutectic reaction, and solderless mounting can be performed. It can eradicate rising solder, poor solder flow, etc., and it can be applied to Si chip production line using solderless mounting method which could not be applied conventionally.
This has the effect that GaAs pellets can be applied.
【図１】本発明の第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明の第２の実施例の平面図、断面図。FIG. 2 is a plan view and a sectional view of a second embodiment of the present invention.
【図３】従来技術の断面図。FIG. 3 is a sectional view of a conventional technique.
【図４】ソルダーレスマウント方法の断面図。FIG. 4 is a sectional view of a solderless mounting method.
【図５】従来技術によるソルダーレスマウント方法を利
用したリードフレーム図。FIG. 5 is a lead frame diagram using a conventional solderless mounting method.
１１．リードフレーム １２．Ｓｎメッキ層 １３．化合物半導体ペレット １４．Ａｕメッキ層 １５．Ｔｉ−Ｐｔ−Ａｕ層 １６．Ａｕ−Ｓｎ合金層 ２１．リードフレーム ２２．Ｓｎメッキ層 ２３．電極パッド厚Ａｕメッキ層 ２４．化合物半導体ペレット ３１．リードフレーム ３３．化合物半導体ペレット ３４．Ｔｉ−Ｐｔ−Ａｕ層 ４１．Ｃｕベース ４２．Ｎｉメッキ ４３．Ａｕメッキ層 ４４．Ｓｎメッキ層 ４５．化合物半導体ペレット ５１．マウントステージ ５２．リードフレーム ５３．Ｓｎ−Ａｕメッキ層 ５４．化合物半導体ペレット 11. Lead frame 12. Sn plating layer 13. Compound semiconductor pellet 14. Au plating layer 15. 15. Ti-Pt-Au layer Au-Sn alloy layer 21. Lead frame 22. Sn plating layer 23. Electrode pad thickness Au plating layer 24. Compound semiconductor pellet 31. Lead frame 33. Compound semiconductor pellet 34. Ti-Pt-Au layer 41. Cu base 42. Ni plating 43. Au plating layer 44. Sn plating layer 45. Compound semiconductor pellet 51. Mount stage 52. Lead frame 53. Sn-Au plating layer 54. Compound semiconductor pellet
Claims (2)
を設け、前記半導体ペレットを支持する支持基体の一表
面に前記第１の金属層と共晶反応により共晶合金を形成
する第２の金属層を設け、前記半導体ペレットと前記支
持基体との間に１層の共晶合金のみ形成するように前記
第１の金属層と前記第２の金属層とを共晶反応を呈する
温度にて接合させることを特徴とする半導体装置の製造
方法。1. A semiconductor on a surface of the pellets providing a first metal layer, said semiconductor pellet the first metal layer and the eutectic alloy by eutectic reaction to one table <br/> surface of the support base for supporting the Forming a second metal layer for forming the semiconductor pellet;
So that only one layer of the eutectic alloy is formed between
The method of manufacturing a semiconductor device characterized by Ru are bonded at a temperature exhibiting a eutectic reaction between the first metal layer and the second metal layer.
せがＡｕ層とＳｎ層の組合せであることを特徴とする請
求項１に記載の半導体装置の製造方法。 Union according to claim 2, wherein said first metal layer and second metal layer
The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a combination of an Au layer and a Sn layer .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5318950A JP2716355B2 (en) | 1993-11-25 | 1993-11-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5318950A JP2716355B2 (en) | 1993-11-25 | 1993-11-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07147292A JPH07147292A (en) | 1995-06-06 |
| JP2716355B2 true JP2716355B2 (en) | 1998-02-18 |
Family
ID=18104806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5318950A Expired - Fee Related JP2716355B2 (en) | 1993-11-25 | 1993-11-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2716355B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1320889A1 (en) * | 2000-09-29 | 2003-06-25 | Infineon Technologies AG | Connecting device |
| JP3994980B2 (en) * | 2004-03-29 | 2007-10-24 | 株式会社日立製作所 | Device mounting substrate, manufacturing method thereof, and semiconductor device mounting method |
| CN102623364A (en) * | 2012-03-01 | 2012-08-01 | 长电科技（滁州）有限公司 | Eutectic process for coating tin on substrate and chip mounting method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0636417B2 (en) * | 1984-02-22 | 1994-05-11 | 住友電気工業株式会社 | Adhesive parts for semiconductor devices |
-
1993
- 1993-11-25 JP JP5318950A patent/JP2716355B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07147292A (en) | 1995-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100552353B1 (en) | Leadframe Semiconductor Integrated Circuit Device Using the Same and Method of and Process for Fabricating the Two | |
| JP3255646B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JP3461720B2 (en) | Resin-sealed semiconductor device | |
| US20080087996A1 (en) | Semiconductor device and manufacturing method of the same | |
| JP2016105503A (en) | Semiconductor device | |
| JPH11340409A (en) | Lead frame and its manufacture and resin encapsulated semiconductor device and its manufacture | |
| US5559316A (en) | Plastic-molded semiconductor device containing a semiconductor pellet mounted on a lead frame | |
| JP2001230360A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| KR20000048011A (en) | A semiconductor device | |
| JPH11354572A (en) | Semiconductor chip package and its manufacture | |
| JP2716355B2 (en) | Method for manufacturing semiconductor device | |
| EP0074378A1 (en) | Semiconductor device including plateless package | |
| JP3686047B2 (en) | Manufacturing method of semiconductor device | |
| JPH0817870A (en) | Semiconductor device | |
| JP3443406B2 (en) | Resin-sealed semiconductor device | |
| JP4066050B2 (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| JP2986661B2 (en) | Method for manufacturing semiconductor device | |
| JPH0525236Y2 (en) | ||
| JP4175339B2 (en) | Manufacturing method of semiconductor device | |
| JP2894172B2 (en) | Semiconductor device | |
| JP4764608B2 (en) | Semiconductor device | |
| JP2006216993A (en) | Resin sealed semiconductor device | |
| JPH11145363A (en) | Semiconductor device | |
| JPWO2005116300A1 (en) | Semiconductor component exterior palladium plating structure and method for manufacturing semiconductor device | |
| JPH09252020A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960924 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071107 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081107 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081107 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091107 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091107 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101107 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101107 Year of fee payment: 13 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101107 Year of fee payment: 13 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111107 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111107 Year of fee payment: 14 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121107 Year of fee payment: 15 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121107 Year of fee payment: 15 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131107 Year of fee payment: 16 |
|
| LAPS | Cancellation because of no payment of annual fees |