JP4433138B2 - Method for forming outer layer of electronic component - Google Patents

Description

【０００７】
▲２▼また、工程内での樹脂の硬化収縮等により個品の配列がゆがむので、上記の傾向は一層助長される。
【０００８】
▲３▼上記のために外層の平均厚さを厚く設定せざるを得ず、最終形状を同一に設定する場合、これにより部品の有効領域を小さくせざるを得ない。部品そのもののサイズが大きい場合は、これはさほど気にはならないが、部品の大きさが１００５タイプ（縦１mm、横０.５mm、厚さ０.５mm）、０６０３タイプ（縦０.６mm、横０.３mm、厚さ０.３mm）になると、部品の性能を決定する重要な要素になる。すなわち、外層の体積が大きくなり、正味の部品の体積が小さくなるので、例えばコイルを形成する場合を考えると、巻線の径が小さくなり、これにより、Ｑの低下及びインダクタンスの取得範囲の低下（シリーズ化の範囲の縮小）をきたす。
【０００９】
本発明は、上記の点に鑑み、薄く高精度で、高信頼性の外層を形成でき、これにより電子部品の有効領域（機能領域）を拡大し、性能の向上を図るとともに、それらを量産性良く実現可能な電子部品の外層形成方法を提供することを目的とする。
【００１０】
本発明のその他の目的や新規な特徴は後述の実施の形態において明らかにする。
【００１１】
【課題を解決するための手段】
上記目的を達成するために、本願請求項１の発明に係る電子部品の外層形成方法は、絶縁層と導体層とを積層した積層体に端子電極を設ける場合において、外層樹脂を設ける前の前記電子部品を複数形成した集合基板を用い、前記電子部品が一方向に多数配列された棒状電子部品配列体になるように、前記棒状電子部品配列体が前記集合基板の周縁部において連結状態を維持するスリット加工を施し、当該スリット加工後の前記集合基板における各電子部品の保護すべき導体層に電流を流して、当該導体層の露出部分を覆う外層樹脂を電着法で形成することを特徴としている。
【００１５】
本願請求項２の発明に係る電子部品の外層形成方法は、請求項１において、前記保護すべき導体層への給電を前記端子電極から行うことを特徴としている。
【００１７】
本願請求項３の発明に係る電子部品の外層形成方法は、請求項１又は２において、前記外層樹脂を設ける前の電子部品が導体パターンを有し、該導体パターンの一部をアルカリ可溶のマスキングで覆うことを特徴としている。
【００１８】
本願請求項４の発明に係る電子部品の外層形成方法は、請求項１，２又は３において、前記端子電極の形成面の全面に下地導体層を形成し、前記端子電極の形成領域を残してアルカリ可溶のマスキングで覆い、前記端子電極を電気めっきで形成することを特徴としている。
【００１９】
本願請求項５の発明に係る電子部品の外層形成方法は、請求項１，２，３又は４において、前記外層樹脂がポリイミド、エポキシ系又はアクリル系樹脂であることを特徴としている。
【００２０】
本願請求項６の発明に係る電子部品の外層形成方法は、請求項１，２，３，４又は５において、前記積層体に搭載部品を接合後、前記搭載部品の電極及び前記積層体への接合部を少なくとも覆うように前記外層樹脂を電着法で設けたことを特徴としている。
【００２１】
【発明の実施の形態】
以下、本発明に係る電子部品の外層形成方法の実施の形態を図面に従って説明する。
【００２２】
図１乃至図３を用いて本発明に係る電子部品の外層形成方法の第１の実施の形態を説明する。この第１の実施の形態はヘリカルコイルを内蔵した表面実装部品を作製する例である。
【００２３】
まず、図１（Ａ）のコア層形成工程にて、絶縁層１１と導体層１２とを交互に積層した積層体１０に対して、コア層形成のための角柱状の溝１３を積層方向（図のＹ方向）形成する。実際には図１のＸ方向（横方向）及びＹ方向に広がった集合基板を用いて処理を行う。図１はＸ方向に１列に個品が並んでいるが、実際にはＹ方向にも、適当な間隔（後述するＸ方向のダイシング幅以上）をおいて多数並んでいる。この溝１３は積層体１０のＸ方向に一定間隔をおいて複数形成される。絶縁層１１は絶縁樹脂層であり、導体層１２は例えば銅箔等を使用し、角柱状の溝１３を形成することにより、コ字型の導体層１２が一定間隔に並んだ配置となる。
【００２４】
そして、角柱状の溝１３内にコア層１４となる絶縁樹脂又は樹脂に磁性体粉を混入した複合材料を充填する。コア層１４に使用する樹脂は前記絶縁層１１と同様のものを使用可能である。
【００２５】
次に、図１（Ｂ）の橋架導体形成工程において、隣接するコ字型の導体層１２間を接続するための橋架導体２０を形成する。この橋架導体２０は、例えば、フォトリソグラフィー技術を利用したパターンめっき法、スパッタ等の薄膜工法等で形成する。この橋架導体２０の形成により、図２のように、コ字型の導体層１２と橋架導体２０とでヘリカルコイルが形成される。このヘリカルコイルは角柱状のコア層１４を周回することになる。
【００２６】
その後、図１（Ｃ）の上下保護層形成工程にて、上下保護層２１，２２を積層体１０の橋架導体２０を設けた面及び反対面に絶縁樹脂で形成する。この絶縁樹脂は前記絶縁層１１と同様のものを使用可能である。
【００２７】
それから、図１（Ｄ）のビアホール形成工程にて、ビアホール２３を保護層２１にレジストマスクを使用したサンドブラスト加工、レーザー加工等で形成する。ビアホール２３は図２のヘリカルコイルの端部を後工程で形成する端子電極４０に接続するためのものである。
【００２８】
次に、図１（Ｅ）の下地導体層形成工程にて、下地導体層３０を保護層２１上に形成する。下地導体層３０は例えば０.３μｍ厚の銅層であり、無電解めっき等で形成する。
【００２９】
それから、図１（Ｆ）のレジストパターン形成工程において、端子電極形成領域を除き下地導体層３０をレジストパターン３１で被覆する（アルカリ可溶のマスキングを形成する）。レジストパターン３１は例えばアルカリ可溶のフォトレジストとしてのドライフィルムの紫外線による露光現像で行うことができる。
【００３０】
そして、図１（Ｇ）の端子電極形成工程にて、下地導体層３０の露出した端子電極形成領域に電気めっきにより端子電極４０を形成する。なお、図示は省略するが、後工程で外層樹脂を電着する際に、端子電極４０に外層樹脂が電着しないように、端子電極４０を少なくとも覆うレジストを設ける。例えば端子電極４０の形成されている面にアルカリ可溶のドライフィルムを貼り付け、全面を紫外線で露光してレジスト（アルカリ可溶のマスキング）とする。この場合、ドライフィルムの厚さは端子電極４０の厚さの１.５倍以上が望ましい。
【００３１】
その後、図１（Ｈ）のスリット加工工程において、Ｙ方向のスリット４５をダイシングで形成し、Ｘ方向に連なっていた表面実装部品５０同士を切り離す。但し、実際に図３の集合基板６０で作製する場合、スリット４５の形成後もヘリカルコイルを内蔵した表面実装部品５０はＹ方向には連続しており、表面実装部品５０がＹ方向に多数配列された棒状電子部品配列体５１として残る。また、前記集合基板をスリット加工する際、図３のように、前記集合基板６０の周縁部６１は連結状態に残しておき、スリット４５を形成後においても前記棒状電子部品配列体５１が周縁部６１にて等間隔で一体に支持されるようにしておく。その後、スリット加工のためのダイシング時のバリを除去するために、ソフトエッチングを行う。このときのエッチング液組成は過硫酸ソーダ２００ｇ／Ｌ、硫酸２０ｍＬ／Ｌであり、処理条件は例えば２５℃で２分である。このとき電着工程の導通を確保するために、図３のスリット４５の外枠となる周縁部６１の一部にマスキングを施しておく。
【００３２】
次に、図１（Ｉ）の電着工程において、表面実装部品５０の両側面（図３の棒状電子部品配列体５１の両側面）、言い換えれば図３の集合基板６０のスリット４５に外層樹脂７０を電着法により付着させる。すなわち、電着液中に図３の集合基板６０を浸した状態において、下地導体層３０（端子電極４０）に直流電圧を印加し、下地導体層３０に電気接続している各導体層１２に電流を流して側面露出部分に外層樹脂７０を電着する。電着法で形成する外層樹脂７０としては、ポリイミド、エポキシ系、アクリル系のものが挙げられる。電着液の具体例として、日本ペイント社製の商品名「ＩＮＳＵＬＥＥＤ」（エポキシ系のカチオン電着樹脂）があり、この電着液の場合、処理条件は液温３０℃、印加電圧１〜５０Ｖ５秒、５０Ｖ２５秒である。その後、乾燥処理を行う。乾燥条件はコンベクションオーブン中で１００℃１０分である。なお、電着した硬化前の外層樹脂７０は乾燥温度（１００℃前後）で粘度が低下して適度の流動性を有し、また積層体１０における導体層１２の配列間隔は小さいため、導体層１２の露出部分に付着した外層樹脂７０はその流動性により表面実装部品５０の側面全面に広がり、表面張力で表面が平坦になるように流動する。
【００３３】
次に、図１（Ｊ）のレジスト剥離工程において、端子電極４０を覆っていたレジスト及び下地導体層３０を覆っていたレジストパターン３１を剥離する。レジストとしてドライフィルムを使用した場合、剥離条件は４０℃の水酸化ナトリウム３％液に５分間浸漬する。
【００３４】
レジスト剥離工程終了後、電着法で形成した外層樹脂７０の硬化を行う。硬化条件は日本ペイント社製の「ＩＮＳＵＬＥＥＤ」を使用した場合、コンベクションオーブン内で１６０℃、１時間である。
【００３５】
次に、図１（Ｋ）の下地導体層剥離工程において、下地導体層３０をエッチングする。エッチング条件はメルテックス社の商品名「エープロセス」を用いて室温で１分間である。このとき端子電極４０は、その表面に錫層もしくは金層等を予め電気めっきしておくことで、エッチングされないように設定できる。
【００３６】
最後に、Ｘ方向に平行にダイシングして個品の表面実装部品５０に分離する。これにより、絶縁層１１と導体層１２とを積層した積層体１０に端子電極４０を設けた電子部品であって、積層体１０の側面に露出した導体層１２を覆う外層樹脂７０を電着で設けた電子部品としての表面実装部品５０が得られる。
【００３７】
以下の表２は電着する外層樹脂７０の厚さを１０μｍ程度となるように設定したときの、素子１００個の外層厚さの分布を示し、ばらつきが小さく、外層樹脂７０の厚みを薄く形成できることが判る。但し、電着液：日本ペイント社製の「ＩＮＳＵＬＥＥＤ」、乾燥条件：コンベクションオーブン中で１００℃１０分、硬化条件：コンベクションオーブン内で１６０℃、１時間とした。
【００３８】
【表２】

【００３９】
また、以下の表３は電着する外層樹脂７０の厚さを１７μｍ程度となるように設定したときの、素子１００個の外層厚さの分布を示す。
【００４０】
【表３】

この表３では外層樹脂７０の乾燥工程の途中において図３の集合基板６０を上下反転している（外層樹脂の流動性で樹脂下部の厚みが大きくなるのを防止するため）。この表３の場合、素子１００個の全てが１７±２μｍの範囲に入っており、いっそうばらつきを小さくすることが可能である。
【００４１】
この第１の実施の形態によれば、▲１▼集合基板上に電子部品としての表面実装部品５０を縦横一定のピッチで作成し、▲２▼上記で側部の外層で覆われるべき導体層１２がダイシング後に露出するように設計し、▲３▼端子電極、又は端子電極に導通する下地電極層等から給電して電着法により側面に外層樹脂７０を付着形成するようにしたので、次の通りの効果を得ることができる。
【００４２】
（１）従来技術と比較して改良された点
▲１▼外層の厚さの精度の向上が可能である。例えば、絶縁層１１と導体層１２とを積層した積層体１０の側面に平均５０μｍ厚の外層を形成する場合、従来法では３０〜７０μｍにばらつくが、本実施の形態では表２、表３の結果からわかるようにばらつきを改善できる。
▲２▼積層体１０の側面に薄い外層が形成できる（表２のように１０μｍの外層形成可能）。
▲３▼上記の理由によって、外形寸法を同一とした場合には外層の体積を小さくでき、正味の部品の体積を増大させることが可能であり、ヘリカルコイルの巻線の径を大きくすることができ、これにより、Ｑの向上及びインダクタンスの取得範囲の拡大（シリーズ化の範囲の拡大）を図り得る。とくに、特性の向上はインダクタンス素子でチップサイズの小さい場合に顕著である。
【００４３】
（２）その他優れた点
▲１▼電着法であるため、導体の露出している部分に選択的に外層を形成出来る。
▲２▼アルカリ可溶のレジスト（感光性である必要はない）で容易にマスキングができ、電着後の乾燥工程の後で、容易に剥離できる。よって、端子電極４０等の導体部であるが絶縁層を形成したくない場所は選択的に電着による絶縁層を形成させないでおける。
▲３▼必要部分に選択的に絶縁層を形成出来るので材料効率に優れる。
▲４▼電着法で形成するので、タクトが短く（処理時間約１分）、量産性に優れる。
▲５▼電着法で形成するので外層はピンホールが少なく信頼性に富む。
▲６▼電着時の導体層１２への給電は、端子電極４０又は下地導体層３０（集合基板６０の周縁部６１に延長している）を利用して容易に行うことができ、端子電極４０は底面電極であり、マスキングが容易である。
【００４４】
図４で本発明の第２の実施の形態を説明する。この第２の実施の形態は、絶縁層８１と導体層８２との積層体としてのモジュール基板８０上に搭載部品９０，９５を装着した後、搭載部品９０，９５の電極９１，９６及びモジュール基板８０への接合部９２，９７にも電着で外層樹脂７０を設けている。
【００４５】
電着法で外層樹脂７０を形成する手順を説明すると、図４（Ａ）のように、搭載部品９０，９５を装着したモジュール基板８０をダイシングしてモジュール基板８０の側面に導体層８２を露出させる。その後、モジュール基板８０及び搭載部品９０，９５共に電着液中に浸し、導体層８２に電気接続する端子電極８３を通して通電することで、側面に露出した導体層８２を覆う外層樹脂７０を付着形成する。このとき、前記端子電極８３を通して前記搭載部品９０，９５の電極９１，９６及びモジュール基板８０への接合部９２，９７（モジュール基板８０側の導体パターンへのはんだ接続部分等）にも外層樹脂７０を付着形成できる。
【００４６】
なお、電着に際し、端子電極８３への電着を防止するために、第１の実施の形態と同様に端子電極８３を覆うようにドライフィルム等のレジストを設けておく。
【００４７】
この第２の実施の形態の場合、搭載部品９０，９５を搭載してから、電着法により外層樹脂７０を形成するため、搭載部品とモジュール基板８０の接合部で導体の露出している部分も保護層を形成出来る利点がある。なお、電着法で形成した外層樹脂７０の硬化処理時の最高温度は１６０℃程度であり、はんだ耐熱試験時の温度に比較してはるかに低く、搭載部品９０，９５には悪影響は無い。
【００４８】
なお、上記第１又は第２の実施の形態において、図３の集合基板６０の周縁部６１に延長している下地導体層３０を利用して、図１の各々の表面実装部品５０の導体層１２、図４の導体層８２等に通電することが可能であるが、下地導体層の無い場合には、各部品の端子電極を相互に接続するＹ方向の導体パターンで接続しておき、個品に分離するためのダイシング時に切り離す構成とすればよい。
【００４９】
上記第１又は第２の実施の形態の電着工程において、電着不要部分のマスキングはドライフィルムの他、粘着テープ、ＵＶ剥離シート、熱剥離シート、液状レジスト等を用いることができる。なかでもドライフィルムは形成が容易で、またアルカリ液で容易に剥離でき、さらに、エポキシ系のカチオン電着樹脂と組み合わせると、外層となる電着樹脂は未硬化状態でもアルカリ液の影響を受けないので好ましい。
【００５０】
上記第１の実施の形態では、ヘリカルコイルが電子部品の長手方向に巻かれた縦巻き構造であるが、ヘリカルコイルが電子部品の短手方向に巻かれた横巻き構造の場合にも、巻き径を大きくとれ、Ｑの増大、インダクタンスの取得範囲の拡大が可能である。また、第１の実施の形態では、積層体の導体層と橋架導体との組み合わせでヘリカルコイルを形成したが、導体層間の絶縁層にスルーホールを設けて複数の導体層でヘリカルコイルを構成しても本発明を適用可能である。
【００５１】
以上本発明の実施の形態について説明してきたが、本発明はこれに限定されることなく請求項の記載の範囲内において各種の変形、変更が可能なことは当業者には自明であろう。
【００５２】
【発明の効果】
以上説明したように、本発明によれば、絶縁層と導体層とを積層した積層体に端子電極を設けた電子部品の外層を形成する場合に、保護すべき導体層に電流を流して当該導体層の露出部分を覆う外層樹脂を電着法で設けたので、外層樹脂を薄くし、かつばらつきを少なくして形成可能である。このため、外層の体積を小さくでき、正味のインダクタンス素子、コンデンサ素子の体積を増大させることが可能である。例えば、インダクタンス素子の場合、ヘリカルコイルの巻線の径を大きくすることができ、これにより、Ｑの向上及びインダクタンスの取得範囲の拡大（シリーズ化の範囲の拡大）を図り得、またコンデンサ素子の場合には静電容量の増大を図り得る。また、電着法で形成した外層樹脂は肉厚が薄くともピンホールが少なく、信頼性が高い。
【図面の簡単な説明】
【図１】 本発明に係る電子部品の外層形成方法の第１の実施の形態であって、ヘリカルコイルを内蔵した表面実装部品を作製する例を示す説明図である。
【図２】第１の実施の形態において、コ字型導体層１２と橋架導体２０とでヘリカルコイルを構成していることを説明する斜視図である。
【図３】第１の実施の形態の製造過程で用いる集合基板の例を示す平面図である。
【図４】本発明の第２の実施の形態であって、モジュール基板上に搭載部品を装着した構成に適用した場合の断面図である。
【図５】従来技術による電子部品の外層形成方法を示す説明図である。
【符号の説明】
１，６０ 集合基板
２ 部品
１０ 積層体
１１ 絶縁層
１２ 導体層
１３ 溝
１４ コア層
２０ 橋架導体
２１，２２ 上下保護層
２３ ビアホール
３０ 下地導体層
３１ レジストパターン
４０ 端子電極
５０ 表面実装部品
５１ 電子部品配列体
６１ 周縁部
７０ 外層樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an outer layer forming method of the electronic components, particularly modules, such as surface mount components (SMD), the electronic component comprising a step of performing batch processing with a collective substrate in which at least two or more individual product can take for the outer layer forming method, a thin and can accurately form a high reliability of the outer layer, to a layer forming method with high mass productivity can be manufactured electronic components.
[0002]
[Prior art]
Conventionally, when a large number of surface-mounted components are manufactured collectively using a collective substrate, a space S (S = dicing width + 2 × outer layer thickness) in the vertical and horizontal directions of the collective substrate 1 as shown in FIG. The parts 2 are produced by aligning the parts 2 in the vertical and horizontal directions and separating them by a dicer as shown in FIG. In this case, the portion of the space S that remains without being diced becomes an outer layer (outermost protective layer) that covers the periphery of the component 2.
[0003]
Moreover, although it is not a well-known document, there exists following patent document 1 and 2 as a prior application which this applicant has proposed, and the electronic component which has a helical coil is described. In this case, slits are formed in the collective substrate to produce a component part in which the electronic components are arranged in a row, and after filling the slits with resin, the center of the slit filling resin is cut so that the electronic components are arranged in rows. The outer layer is formed on the side surface of the component part connected to the.
[0004]
[Patent Document 1]
Japanese Patent Application No. 2002-285824 [Patent Document 2]
Japanese Patent Application No. 2002-288681
[Problems to be solved by the invention]
The prior art shown in FIG. 5 has the following problems.
(1) Although the accuracy of dicing is about ± 20 μm, the accuracy of the thickness of the outer layer is poor. For example, when the average thickness of the outer layer is set to be about 50 μm, it becomes 30 to 70 μm and varies. Table 1 below shows the distribution of the outer layer thickness after dicing of 100 elements according to the prior art, and it can be seen that the variation is large.
[0006]
[Table 1]

[0007]
{Circle around (2)} Since the arrangement of individual products is distorted due to curing shrinkage of the resin in the process, the above tendency is further promoted.
[0008]
(3) For the above reasons, the average thickness of the outer layer has to be set thick, and when the final shape is set to be the same, the effective area of the component has to be reduced. If the size of the component itself is large, this is not a concern, but the size of the component is 1005 type (vertical 1 mm, horizontal 0.5 mm, thickness 0.5 mm), 0603 type (vertical 0.6 mm, horizontal) (0.3 mm, thickness 0.3 mm) becomes an important factor for determining the performance of the part. That is, since the volume of the outer layer is increased and the volume of the net component is reduced, for example, when a coil is formed, the diameter of the winding is reduced, thereby reducing Q and lowering the inductance acquisition range. (Reducing the range of series).
[0009]
In view of the above points, the present invention can form a thin, highly accurate and highly reliable outer layer, thereby expanding the effective area (functional area) of electronic components, improving performance, and mass-producing them. and to provide a better feasible outer layer forming method of the electronic components.
[0010]
Other objects and novel features of the present invention will be clarified in embodiments described later.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the method for forming an outer layer of an electronic component according to claim 1 of the present application provides the terminal electrode before providing the outer layer resin in the case where the terminal electrode is provided on the laminate in which the insulating layer and the conductor layer are laminated. Using a collective substrate on which a plurality of electronic components are formed, the rod-shaped electronic component array maintains a connected state at the peripheral portion of the collective substrate so that a large number of electronic components are arranged in one direction. subjected to slitting to, by applying a current to the conductive layer to be protected of each electronic component in the assembly substrate after the slitting, that you formed in the outer layer resin electrodeposition method for covering an exposed portion of the conductive layer It is a feature.
[0015]
According to a second aspect of the present invention, there is provided a method for forming an outer layer of an electronic component according to the first aspect , wherein power is supplied to the conductor layer to be protected from the terminal electrode.
[0017]
The electronic component outer layer forming method according to the invention of claim 3 is the electronic component according to claim 1 or 2 , wherein the electronic component before providing the outer layer resin has a conductor pattern, and a part of the conductor pattern is alkali-soluble. It is characterized by covering with masking.
[0018]
According to a fourth aspect of the present invention, there is provided a method for forming an outer layer of an electronic component according to the first, second, or third aspect, wherein a base conductor layer is formed on the entire surface of the terminal electrode, leaving a region for forming the terminal electrode. The terminal electrode is formed by electroplating with an alkali-soluble masking.
[0019]
According to a fifth aspect of the present invention, there is provided an electronic component outer layer forming method according to the first, second, third, or fourth aspect , wherein the outer layer resin is polyimide, epoxy, or acrylic resin.
[0020]
An electronic component outer layer forming method according to claim 6 of the present application is the electronic component outer layer forming method according to claim 1, 2, 3, 4 or 5 , wherein the mounting component is joined to the laminate, and then the electrode of the mounted component and the laminate are applied. The outer layer resin is provided by an electrodeposition method so as to cover at least the joint.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the outer layer forming method of the electronic components according to the present invention with reference to the accompanying drawings.
[0022]
The first embodiment of the outer layer forming method of the electronic components according to the present invention will be described with reference to FIGS. The first embodiment is an example in which a surface mount component incorporating a helical coil is manufactured.
[0023]
First, in the core layer forming step of FIG. 1A, a prismatic groove 13 for forming the core layer is formed in the stacking direction (in the stacking direction) on the stacked body 10 in which the insulating layers 11 and the conductor layers 12 are alternately stacked. (Y direction in the figure). Actually, the processing is performed using the collective substrate extending in the X direction (lateral direction) and the Y direction in FIG. In FIG. 1, the individual products are arranged in one row in the X direction, but in reality, a large number are arranged in the Y direction at an appropriate interval (more than the dicing width in the X direction described later). A plurality of the grooves 13 are formed at regular intervals in the X direction of the stacked body 10. The insulating layer 11 is an insulating resin layer, and the conductor layer 12 is made of, for example, copper foil. By forming the prismatic grooves 13, the U-shaped conductor layers 12 are arranged at regular intervals.
[0024]
Then, the prismatic grooves 13 are filled with an insulating resin to be the core layer 14 or a composite material in which magnetic powder is mixed into the resin. The resin used for the core layer 14 can be the same as that of the insulating layer 11.
[0025]
Next, in the bridge conductor forming step of FIG. 1B, a bridge conductor 20 for connecting the adjacent U-shaped conductor layers 12 is formed. The bridge conductor 20 is formed by, for example, a pattern plating method using a photolithography technique or a thin film method such as sputtering. By forming the bridge conductor 20, a helical coil is formed by the U-shaped conductor layer 12 and the bridge conductor 20 as shown in FIG. 2. The helical coil goes around the prismatic core layer 14.
[0026]
Thereafter, in the upper and lower protective layer forming step of FIG. 1C, the upper and lower protective layers 21 and 22 are formed of insulating resin on the surface of the laminated body 10 on which the bridge conductor 20 is provided and on the opposite surface. As this insulating resin, the same insulating resin as that of the insulating layer 11 can be used.
[0027]
Then, in the via hole forming step of FIG. 1D, the via hole 23 is formed by sand blasting using a resist mask for the protective layer 21, laser processing, or the like. The via hole 23 is for connecting the end of the helical coil of FIG. 2 to a terminal electrode 40 formed in a later step.
[0028]
Next, the base conductor layer 30 is formed on the protective layer 21 in the base conductor layer forming step of FIG. The underlying conductor layer 30 is a copper layer having a thickness of 0.3 μm, for example, and is formed by electroless plating or the like.
[0029]
Then, in the resist pattern forming step of FIG. 1 (F), the base conductor layer 30 is covered with the resist pattern 31 except for the terminal electrode formation region (alkali-soluble masking is formed). The resist pattern 31 can be formed by, for example, exposure and development with ultraviolet rays of a dry film as an alkali-soluble photoresist.
[0030]
Then, in the terminal electrode formation step of FIG. 1G, the terminal electrode 40 is formed by electroplating in the exposed terminal electrode formation region of the base conductor layer 30. In addition, although illustration is abbreviate | omitted, the resist which covers the terminal electrode 40 at least is provided so that outer layer resin may not be electrodeposited to the terminal electrode 40, when electrodepositing outer layer resin at a post process. For example, an alkali-soluble dry film is attached to the surface where the terminal electrode 40 is formed, and the entire surface is exposed to ultraviolet rays to form a resist (alkali-soluble masking). In this case, the thickness of the dry film is desirably 1.5 times or more the thickness of the terminal electrode 40.
[0031]
Thereafter, in the slit processing step of FIG. 1 (H), the slit 45 in the Y direction is formed by dicing, and the surface mount components 50 connected in the X direction are separated from each other. However, in the case of actually manufacturing with the collective substrate 60 of FIG. 3, even after the slit 45 is formed, the surface mount components 50 having the helical coils are continuous in the Y direction, and many surface mount components 50 are arranged in the Y direction. The bar-shaped electronic component array 51 is left as it is. In addition, when slitting the collective substrate, as shown in FIG. 3, the peripheral portion 61 of the collective substrate 60 is left in a connected state, and the rod-shaped electronic component array 51 is provided with a peripheral portion even after the slit 45 is formed. 61 so as to be integrally supported at equal intervals. Thereafter, soft etching is performed to remove burrs at the time of dicing for slit processing. The composition of the etching solution at this time is sodium persulfate 200 g / L, sulfuric acid 20 mL / L, and the processing conditions are, for example, 25 ° C. and 2 minutes. At this time, in order to ensure the continuity of the electrodeposition process, masking is applied to a part of the peripheral edge portion 61 which becomes the outer frame of the slit 45 in FIG.
[0032]
Next, in the electrodeposition process of FIG. 1 (I), the outer layer resin is formed on both side surfaces of the surface mount component 50 (both side surfaces of the rod-shaped electronic component array 51 of FIG. 3), in other words, the slit 45 of the collective substrate 60 of FIG. 70 is deposited by electrodeposition. That is, in a state where the collective substrate 60 of FIG. 3 is immersed in the electrodeposition liquid, a DC voltage is applied to the underlying conductor layer 30 (terminal electrode 40), and each conductor layer 12 electrically connected to the underlying conductor layer 30 is applied. An outer layer resin 70 is electrodeposited on the exposed side surface by passing an electric current. Examples of the outer layer resin 70 formed by the electrodeposition method include polyimide, epoxy, and acrylic resins. As a specific example of the electrodeposition liquid, there is a trade name “INSULED” (epoxy cationic electrodeposition resin) manufactured by Nippon Paint Co., Ltd. In the case of this electrodeposition liquid, the treatment conditions are a liquid temperature of 30 ° C. and an applied voltage of 1 to 50 V5. Second, 50V25 seconds. Then, a drying process is performed. The drying condition is 100 ° C. for 10 minutes in a convection oven. The outer layer resin 70 that has been electrodeposited is cured at a drying temperature (around 100 ° C.) and has an appropriate fluidity, and the arrangement interval of the conductor layers 12 in the laminate 10 is small. The outer layer resin 70 adhering to the exposed portion 12 spreads over the entire side surface of the surface mount component 50 due to its fluidity, and flows so that the surface becomes flat due to surface tension.
[0033]
Next, in the resist stripping step in FIG. 1J, the resist covering the terminal electrode 40 and the resist pattern 31 covering the base conductor layer 30 are stripped. When a dry film is used as the resist, the stripping condition is immersed in a 3% sodium hydroxide solution at 40 ° C. for 5 minutes.
[0034]
After completion of the resist stripping process, the outer layer resin 70 formed by the electrodeposition method is cured. When “INSULED” manufactured by Nippon Paint Co., Ltd. is used, the curing conditions are 160 ° C. and 1 hour in a convection oven.
[0035]
Next, in the base conductor layer peeling step in FIG. 1K, the base conductor layer 30 is etched. Etching conditions are 1 minute at room temperature using the trade name “A Process” manufactured by Meltex. At this time, the terminal electrode 40 can be set so as not to be etched by previously electroplating a tin layer or a gold layer on the surface thereof.
[0036]
Finally, dicing is performed in parallel with the X direction to separate the individual surface mount components 50. Thus, the electronic component in which the terminal electrode 40 is provided on the laminate 10 in which the insulating layer 11 and the conductor layer 12 are laminated, and the outer layer resin 70 covering the conductor layer 12 exposed on the side surface of the laminate 10 is electrodeposited. The surface mount component 50 as the provided electronic component is obtained.
[0037]
Table 2 below shows the distribution of the thickness of the outer layer of 100 elements when the thickness of the outer layer resin 70 to be electrodeposited is set to about 10 μm, the variation is small, and the thickness of the outer layer resin 70 is reduced. I understand that I can do it. However, electrodeposition solution: “INSULED” manufactured by Nippon Paint Co., Ltd., drying conditions: 100 ° C. for 10 minutes in a convection oven, curing conditions: 160 ° C. for 1 hour in a convection oven.
[0038]
[Table 2]

[0039]
Table 3 below shows the distribution of the thickness of the outer layer of 100 elements when the thickness of the outer layer resin 70 to be electrodeposited is set to be about 17 μm.
[0040]
[Table 3]

In Table 3, the assembly substrate 60 of FIG. 3 is turned upside down during the drying process of the outer layer resin 70 (in order to prevent the thickness of the resin lower portion from being increased due to the fluidity of the outer layer resin). In the case of Table 3, all 100 elements are in the range of 17 ± 2 μm, and the variation can be further reduced.
[0041]
According to the first embodiment, (1) surface mounting components 50 as electronic components are formed on a collective substrate at a constant vertical and horizontal pitch, and (2) the conductor layer to be covered with the outer layer on the side as described above. 12 is designed to be exposed after dicing, and (3) power is supplied from the terminal electrode or the base electrode layer conducting to the terminal electrode, and the outer layer resin 70 is formed on the side surface by electrodeposition. The effect of the street can be obtained.
[0042]
(1) Points improved over the prior art (1) The accuracy of the thickness of the outer layer can be improved. For example, when an outer layer having an average thickness of 50 μm is formed on the side surface of the laminate 10 in which the insulating layer 11 and the conductor layer 12 are laminated, the conventional method varies from 30 to 70 μm, but in this embodiment, the outer layers shown in Tables 2 and 3 are used. As can be seen from the results, variation can be improved.
(2) A thin outer layer can be formed on the side surface of the laminate 10 (an outer layer of 10 μm can be formed as shown in Table 2).
(3) For the above reasons, if the outer dimensions are the same, the outer layer volume can be reduced, the net part volume can be increased, and the helical coil winding diameter can be increased. In this way, Q can be improved, and the inductance acquisition range can be expanded (series expansion range can be expanded). In particular, the improvement in characteristics is significant when the inductance element is small and the chip size is small.
[0043]
(2) Other excellent points {circle around (1)} Since the electrodeposition method is used, an outer layer can be selectively formed on the exposed portion of the conductor.
(2) Masking can be easily performed with an alkali-soluble resist (not necessarily photosensitive), and can be easily removed after the drying step after electrodeposition. Therefore, an insulating layer formed by electrodeposition may not be selectively formed at a place where a conductor portion such as the terminal electrode 40 is not desired to form an insulating layer.
(3) Since an insulating layer can be selectively formed in a necessary portion, the material efficiency is excellent.
(4) Since it is formed by the electrodeposition method, the tact time is short (processing time is about 1 minute) and the mass productivity is excellent.
(5) Since it is formed by the electrodeposition method, the outer layer has few pinholes and is highly reliable.
(6) Power supply to the conductor layer 12 during electrodeposition can be easily performed using the terminal electrode 40 or the underlying conductor layer 30 (extending to the peripheral edge 61 of the collective substrate 60). Reference numeral 40 denotes a bottom electrode, which is easy to mask.
[0044]
A second embodiment of the present invention will be described with reference to FIG. In the second embodiment, after mounting components 90 and 95 are mounted on a module substrate 80 as a laminate of an insulating layer 81 and a conductor layer 82, electrodes 91 and 96 of the mounting components 90 and 95 and the module substrate are mounted. The outer layer resin 70 is also provided by electrodeposition on the joints 92 and 97 to 80.
[0045]
The procedure for forming the outer layer resin 70 by the electrodeposition method will be described. As shown in FIG. 4A, the module substrate 80 on which the mounting components 90 and 95 are mounted is diced to expose the conductor layer 82 on the side surface of the module substrate 80. Let Thereafter, the module substrate 80 and the mounting components 90 and 95 are both immersed in the electrodeposition solution and energized through the terminal electrode 83 electrically connected to the conductor layer 82, thereby forming the outer layer resin 70 covering the conductor layer 82 exposed on the side surface. To do. At this time, the outer layer resin 70 is also applied to the electrodes 91 and 96 of the mounting components 90 and 95 and the joint portions 92 and 97 to the module substrate 80 (solder connection portions to the conductor pattern on the module substrate 80 side) through the terminal electrode 83. Can be formed.
[0046]
In the case of electrodeposition, a resist such as a dry film is provided so as to cover the terminal electrode 83 as in the first embodiment in order to prevent electrodeposition on the terminal electrode 83.
[0047]
In the case of the second embodiment, after mounting components 90 and 95 are mounted, outer layer resin 70 is formed by an electrodeposition method, so that the conductor is exposed at the joint between the mounting component and module substrate 80. Has an advantage that a protective layer can be formed. The maximum temperature during the curing process of the outer layer resin 70 formed by the electrodeposition method is about 160 ° C., which is much lower than the temperature during the solder heat resistance test, and the mounted components 90 and 95 are not adversely affected.
[0048]
In the first or second embodiment, the conductor layer of each surface mount component 50 in FIG. 1 is used by using the base conductor layer 30 extending to the peripheral edge 61 of the collective substrate 60 in FIG. 12, the conductor layer 82 in FIG. 4 can be energized, but when there is no underlying conductor layer, the terminal electrodes of each component are connected with the Y-direction conductor pattern to connect them individually. What is necessary is just to set it as the structure cut | disconnected at the time of dicing for isolate | separating into goods.
[0049]
In the electrodeposition process of the first or second embodiment, the electrodeposition unnecessary portion can be masked by using a dry film, an adhesive tape, a UV release sheet, a heat release sheet, a liquid resist, or the like. In particular, dry films are easy to form and can be easily peeled off with an alkaline solution. Furthermore, when combined with an epoxy-based cationic electrodeposition resin, the outer electrodeposition resin is not affected by the alkali solution even in an uncured state. Therefore, it is preferable.
[0050]
In the first embodiment, the helical coil is a vertical winding structure in which the electronic coil is wound in the longitudinal direction of the electronic component. However, even in the case of a lateral winding structure in which the helical coil is wound in the short direction of the electronic component, the winding is performed. The diameter can be increased, Q can be increased, and the inductance acquisition range can be expanded. In the first embodiment, the helical coil is formed by a combination of the conductor layer and the bridge conductor of the laminated body. However, the helical coil is configured by a plurality of conductor layers by providing a through hole in the insulating layer between the conductor layers. However, the present invention is applicable.
[0051]
Although the embodiments of the present invention have been described above, it will be obvious to those skilled in the art that the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of the claims.
[0052]
【The invention's effect】
As described above, according to the present invention, when forming an outer layer of an electronic component in which a terminal electrode is provided on a laminate in which an insulating layer and a conductor layer are laminated, current is passed through the conductor layer to be protected. Since the outer layer resin covering the exposed portion of the conductor layer is provided by the electrodeposition method, the outer layer resin can be formed thin and with less variation. For this reason, the volume of the outer layer can be reduced, and the volume of the net inductance element and the capacitor element can be increased. For example, in the case of an inductance element, it is possible to increase the diameter of the helical coil winding, thereby improving Q and expanding the inductance acquisition range (expanding the range of series). In some cases, the capacitance can be increased. Further, the outer layer resin formed by the electrodeposition method has few pinholes even when the wall thickness is thin, and has high reliability.
[Brief description of the drawings]
[1] A first embodiment of the outer layer forming method of the electronic components according to the present invention, is an explanatory diagram showing an example of manufacturing a surface mount component with a built-in helical coils.
FIG. 2 is a perspective view for explaining that a helical coil is constituted by a U-shaped conductor layer 12 and a bridge conductor 20 in the first embodiment.
FIG. 3 is a plan view showing an example of an aggregate substrate used in the manufacturing process of the first embodiment.
FIG. 4 is a cross-sectional view showing a second embodiment of the present invention and applied to a configuration in which a mounting component is mounted on a module substrate.
FIG. 5 is an explanatory view showing a method for forming an outer layer of an electronic component according to a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,60 Collective board 2 Component 10 Laminated body 11 Insulating layer 12 Conductor layer 13 Groove 14 Core layer 20 Bridge conductors 21 and 22 Upper and lower protective layers 23 Via hole 30 Underlayer conductor layer 31 Resist pattern 40 Terminal electrode 50 Surface mount component 51 Electronic component arrangement Body 61 Perimeter 70 Outer layer resin

Claims (6)

In the outer layer forming method of the electronic component in which the terminal electrode is provided on the laminate in which the insulating layer and the conductor layer are laminated,
Using a collective substrate formed with a plurality of the electronic components before providing the outer layer resin,
The rod-shaped electronic component array is subjected to slit processing for maintaining a connected state at the peripheral edge of the collective substrate so that the electronic component is a rod-shaped electronic component array in which a large number of the electronic components are arrayed in one direction . wherein by applying a current to the conductive layer to be protected of each electronic component in the assembly substrate, the outer layer forming method of an electronic component, and forming at electrodeposition method an outer resin covering the exposed portion of the conductive layer. The outer layer forming method of the electronic component of claim 1, wherein performing the power supply to the protection to be conductive layer from said terminal electrodes. The electronic component outer layer forming method according to claim 1 or 2 , wherein the electronic component before the outer layer resin is provided has a conductor pattern, and a part of the conductor pattern is covered with alkali-soluble masking. The base conductor layer is formed on the entire surface of the forming surface of the terminal electrode, the covered with masking of the alkali-soluble leaving the formation region of the terminal electrode, according to claim 1, wherein forming the terminal electrodes by electroplating Method for forming an outer layer of electronic parts. The method for forming an outer layer of an electronic component according to claim 1, 2, 3, or 4 , wherein the outer layer resin is a polyimide, an epoxy resin, or an acrylic resin. Wherein after the joining of the mounting component in the laminate, the mounting parts of the electrodes and in the claims 1, 2, 3, 4 or 5, wherein the joint provided with the outer layer resin in the electrodeposition method so as to at least cover to the laminate Method for forming an outer layer of electronic parts.

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