JP4413223B2 - セラミックパッケージ - Google Patents
セラミックパッケージ Download PDFInfo
- Publication number
- JP4413223B2 JP4413223B2 JP2006348407A JP2006348407A JP4413223B2 JP 4413223 B2 JP4413223 B2 JP 4413223B2 JP 2006348407 A JP2006348407 A JP 2006348407A JP 2006348407 A JP2006348407 A JP 2006348407A JP 4413223 B2 JP4413223 B2 JP 4413223B2
- Authority
- JP
- Japan
- Prior art keywords
- mass
- substrate
- powder
- ceramic package
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Compositions Of Oxide Ceramics (AREA)
Description
純度99%以上、平均粒子径1.8μmのアルミナ粉末に対して、純度99%以上、平均粒子径4.5μmのMn2O3粉末、純度99%以上、平均粒子径1.0μmのSiO2粉末、純度99.9%以上、平均粒子径1.2μmのW粉末、純度99.9%以上、平均粒子径1.2μmのMo粉末、純度99.9%以上、平均粒子径0.7μmのMgCO3粉末、純度99%以上、平均粒子径1.3μmのCaCO3粉末、純度99%以上、平均粒子径1.0μmのSrCO3粉末、B2O3粉末、Cr2O3粉末及びCo3O4粉末、純度99%以上、平均粒子径1.2μmのTiO2粉末及びZrO2粉末を準備した。
純度99%以上、平均粒子径1.5μmのアルミナ粉末に対して、純度99%以上、平均粒子径0.6〜0.8μmのMn2O3粉末、純度99%以上、平均粒子径0.98μmの溶融SiO2粉末、純度99%以上、平均粒子径7.7μmのMgCO3粉末を表3の組成となるように混合した。
1a・・・基板底部
1b・・・基板堤部
2・・・導体層
2a・・・表面導体層
2b・・・裏面導体層
2c・・・内部導体層
3・・・メタライズ層
4・・・電子部品
5・・・導電性接着剤
6・・・半導体素子
7・・・ワイヤボンディング
8・・・メッキ層
9・・・ロウ材
10・・・金属製蓋体
d・・・基板堤部の幅
D・・・基板底部の厚み
t・・・パッケージ高さ
Claims (2)
- 絶縁基板と、該絶縁基板の内部及び表面の少なくとも一方に設けられた導体層とを具備するセラミックパッケージにおいて、前記絶縁基板が4質量%以上の焼結助剤を含み、Mnを酸化物(Mn2O3)換算で2〜8質量%、Siを酸化物換算で1〜6質量%の割合で含むとともに、Al2O3を主結晶相とし、MnAl2O4結晶を含む、3点曲げ強度が500MPa以上のアルミナ質焼結体(ただし、Mn2SiO4結晶を含むものを除く)からなることを特徴とするセラミックパッケージ。
- 前記絶縁基板が、電気素子を表面に実装するための基板底部及び該基板底部の外周に一体的に設けられた基板堤部を具備するとともに、前記基板堤部の幅が0.1〜0.3mm、前記基板底部の厚みが0.1〜0.3mm、パッケージ全体の高さが0.3〜0.6mmであることを特徴とする請求項1に記載のセラミックパッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006348407A JP4413223B2 (ja) | 2002-02-14 | 2006-12-25 | セラミックパッケージ |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002037181 | 2002-02-14 | ||
JP2006348407A JP4413223B2 (ja) | 2002-02-14 | 2006-12-25 | セラミックパッケージ |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002328647A Division JP3911470B2 (ja) | 2002-02-14 | 2002-11-12 | セラミックパッケージ及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007096349A JP2007096349A (ja) | 2007-04-12 |
JP4413223B2 true JP4413223B2 (ja) | 2010-02-10 |
Family
ID=37981573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006348407A Expired - Fee Related JP4413223B2 (ja) | 2002-02-14 | 2006-12-25 | セラミックパッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4413223B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016098767A1 (ja) * | 2014-12-16 | 2016-06-23 | 日本碍子株式会社 | セラミック素地及びその製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6298009B2 (ja) * | 2015-06-05 | 2018-03-20 | 日本特殊陶業株式会社 | セラミック基板及びセラミックパッケージ |
-
2006
- 2006-12-25 JP JP2006348407A patent/JP4413223B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016098767A1 (ja) * | 2014-12-16 | 2016-06-23 | 日本碍子株式会社 | セラミック素地及びその製造方法 |
JPWO2016098767A1 (ja) * | 2014-12-16 | 2017-09-28 | 日本碍子株式会社 | セラミック素地及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2007096349A (ja) | 2007-04-12 |
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