JP4969486B2 - 電子部品収納用パッケージ - Google Patents
電子部品収納用パッケージ Download PDFInfo
- Publication number
- JP4969486B2 JP4969486B2 JP2008043872A JP2008043872A JP4969486B2 JP 4969486 B2 JP4969486 B2 JP 4969486B2 JP 2008043872 A JP2008043872 A JP 2008043872A JP 2008043872 A JP2008043872 A JP 2008043872A JP 4969486 B2 JP4969486 B2 JP 4969486B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- electronic component
- coating layer
- insulating layer
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Description
る。したがって、より一層効果的に絶縁基体1の凹部2の内側面からのセラミック粒子Cの脱落が防止された電子部品収納用パッケージ9を提供することができる。
1a・・・・セラミック絶縁層
1b・・・・セラミックグリーンシート
2・・・・・凹部
3・・・・・セラミック被覆層
4・・・・・電子部品
5・・・・・配線導体
6・・・・・ボンディングワイヤ
9・・・・・電子部品収納用パッケージ
11〜13・・・分割積層体
C・・・・・セラミック粉末
P2,P3・打ち抜き加工する所定部位
Claims (2)
- 複数のセラミック絶縁層が積層されてなる絶縁基体の上面に、一部の前記セラミック絶縁層の中央部が厚み方向に貫通されて形成された電子部品収納用の凹部を有し、該凹部の内側面がセラミック被覆層で被覆されており、
該セラミック被覆層は、前記セラミック絶縁層のセラミック材料と同じセラミック材料を主成分としているとともに、前記セラミック絶縁層よりも多い割合でガラス成分を含有していることを特徴とする電子部品収納用パッケージ。 - 前記凹部の前記内側面の一部が破断面となっており、前記セラミック被覆層の厚さが、前記凹部の前記内側面の前記破断面となっている部分において他の部分よりも厚いことを特徴とする請求項1記載の電子部品収納用パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008043872A JP4969486B2 (ja) | 2008-02-26 | 2008-02-26 | 電子部品収納用パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008043872A JP4969486B2 (ja) | 2008-02-26 | 2008-02-26 | 電子部品収納用パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009206115A JP2009206115A (ja) | 2009-09-10 |
JP4969486B2 true JP4969486B2 (ja) | 2012-07-04 |
Family
ID=41148133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008043872A Expired - Fee Related JP4969486B2 (ja) | 2008-02-26 | 2008-02-26 | 電子部品収納用パッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4969486B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111134831A (zh) * | 2019-12-31 | 2020-05-12 | 上海交通大学 | 基于蜿蜒线的柔性mems可延展传感器及其制备方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3138377B2 (ja) * | 1993-11-22 | 2001-02-26 | 日本特殊陶業株式会社 | 集積回路用セラミックパッケージ本体 |
JP2002141430A (ja) * | 2000-10-31 | 2002-05-17 | Kyocera Corp | デジタルマイクロミラーデバイス収納用パッケージ |
JP2002141429A (ja) * | 2000-10-31 | 2002-05-17 | Kyocera Corp | デジタルマイクロミラーデバイス収納用パッケージ |
JP2006147729A (ja) * | 2004-11-17 | 2006-06-08 | Murata Mfg Co Ltd | セラミック多層基板及びその製造方法 |
JP2007318033A (ja) * | 2006-05-29 | 2007-12-06 | Kyocera Corp | 電子部品収納用パッケージおよび電子装置 |
-
2008
- 2008-02-26 JP JP2008043872A patent/JP4969486B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009206115A (ja) | 2009-09-10 |
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