JP4401023B2 - 遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション - Google Patents
遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション Download PDFInfo
- Publication number
- JP4401023B2 JP4401023B2 JP2000545191A JP2000545191A JP4401023B2 JP 4401023 B2 JP4401023 B2 JP 4401023B2 JP 2000545191 A JP2000545191 A JP 2000545191A JP 2000545191 A JP2000545191 A JP 2000545191A JP 4401023 B2 JP4401023 B2 JP 4401023B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon oxynitride
- deep
- metallization layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
- H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
- H10P76/2041—Photolithographic processes
- H10P76/2043—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
- H10W20/4405—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
- H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/952—Utilizing antireflective layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/065,352 | 1998-04-23 | ||
| US09/065,352 US6287959B1 (en) | 1998-04-23 | 1998-04-23 | Deep submicron metallization using deep UV photoresist |
| PCT/US1999/007361 WO1999054930A1 (en) | 1998-04-23 | 1999-04-01 | Deep submicron metallization using deep uv photoresist |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002512449A JP2002512449A (ja) | 2002-04-23 |
| JP2002512449A5 JP2002512449A5 (https=) | 2006-04-27 |
| JP4401023B2 true JP4401023B2 (ja) | 2010-01-20 |
Family
ID=22062123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000545191A Expired - Fee Related JP4401023B2 (ja) | 1998-04-23 | 1999-04-01 | 遠紫外線フォトレジストを用いたディープサブミクロンメタライゼーション |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6287959B1 (https=) |
| EP (1) | EP1080494A1 (https=) |
| JP (1) | JP4401023B2 (https=) |
| KR (1) | KR100562540B1 (https=) |
| WO (1) | WO1999054930A1 (https=) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331379B1 (en) * | 1999-09-01 | 2001-12-18 | Micron Technology, Inc. | Photo-lithography process using multiple anti-reflective coatings |
| DE10000004A1 (de) * | 2000-01-03 | 2001-05-17 | Infineon Technologies Ag | Verfahren zur Herstellung von Leitbahnen |
| US20020197835A1 (en) * | 2001-06-06 | 2002-12-26 | Sey-Ping Sun | Anti-reflective coating and methods of making the same |
| JP2003124189A (ja) * | 2001-10-10 | 2003-04-25 | Fujitsu Ltd | 半導体装置の製造方法 |
| US6613665B1 (en) * | 2001-10-26 | 2003-09-02 | Lsi Logic Corporation | Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface |
| JP2003209046A (ja) * | 2002-01-16 | 2003-07-25 | Mitsubishi Electric Corp | レジストパターン形成方法および半導体装置の製造方法 |
| KR100506943B1 (ko) * | 2003-09-09 | 2005-08-05 | 삼성전자주식회사 | 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들 |
| US7611758B2 (en) * | 2003-11-06 | 2009-11-03 | Tokyo Electron Limited | Method of improving post-develop photoresist profile on a deposited dielectric film |
| US7101787B1 (en) * | 2004-04-09 | 2006-09-05 | National Semiconductor Corporation | System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition |
| US10236398B2 (en) | 2015-07-06 | 2019-03-19 | Electronics And Telecommunications Research Institute | Method for manufacturing transparent electrode |
| US20170064821A1 (en) * | 2015-08-31 | 2017-03-02 | Kristof Darmawikarta | Electronic package and method forming an electrical package |
| US10964653B2 (en) * | 2017-09-28 | 2021-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a semiconductor device comprising top conductive pads |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010644A (ja) | 1983-06-30 | 1985-01-19 | Toshiba Corp | 半導体装置の製造方法 |
| JPH05190796A (ja) | 1991-07-30 | 1993-07-30 | Internatl Business Mach Corp <Ibm> | ダイナミック・ランダム・アクセス・メモリ・セル用誘電体皮膜およびその形成方法 |
| KR960005761A (ko) | 1994-07-27 | 1996-02-23 | 이데이 노부유끼 | 반도체장치 |
| US6577007B1 (en) | 1996-02-01 | 2003-06-10 | Advanced Micro Devices, Inc. | Manufacturing process for borderless vias with respect to underlying metal |
| US5858870A (en) | 1996-12-16 | 1999-01-12 | Chartered Semiconductor Manufacturing, Ltd. | Methods for gap fill and planarization of intermetal dielectrics |
-
1998
- 1998-04-23 US US09/065,352 patent/US6287959B1/en not_active Expired - Lifetime
-
1999
- 1999-04-01 WO PCT/US1999/007361 patent/WO1999054930A1/en not_active Ceased
- 1999-04-01 KR KR1020007011779A patent/KR100562540B1/ko not_active Expired - Fee Related
- 1999-04-01 JP JP2000545191A patent/JP4401023B2/ja not_active Expired - Fee Related
- 1999-04-01 EP EP99916346A patent/EP1080494A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999054930A1 (en) | 1999-10-28 |
| EP1080494A1 (en) | 2001-03-07 |
| JP2002512449A (ja) | 2002-04-23 |
| KR100562540B1 (ko) | 2006-03-22 |
| KR20010042954A (ko) | 2001-05-25 |
| US6287959B1 (en) | 2001-09-11 |
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