JP4395192B2 - 本体コンタクトを有する並列電界効果トランジスタ構造体 - Google Patents

本体コンタクトを有する並列電界効果トランジスタ構造体 Download PDF

Info

Publication number
JP4395192B2
JP4395192B2 JP2008506717A JP2008506717A JP4395192B2 JP 4395192 B2 JP4395192 B2 JP 4395192B2 JP 2008506717 A JP2008506717 A JP 2008506717A JP 2008506717 A JP2008506717 A JP 2008506717A JP 4395192 B2 JP4395192 B2 JP 4395192B2
Authority
JP
Japan
Prior art keywords
region
fet
gate conductor
conductor portion
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008506717A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008537339A (ja
JP2008537339A5 (enExample
Inventor
ワーノック、ジェームズ、ディー
スミス、ジョージ、イー、サード
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2008537339A publication Critical patent/JP2008537339A/ja
Publication of JP2008537339A5 publication Critical patent/JP2008537339A5/ja
Application granted granted Critical
Publication of JP4395192B2 publication Critical patent/JP4395192B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Landscapes

  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)
JP2008506717A 2005-04-15 2006-04-13 本体コンタクトを有する並列電界効果トランジスタ構造体 Expired - Fee Related JP4395192B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/907,796 US7084462B1 (en) 2005-04-15 2005-04-15 Parallel field effect transistor structure having a body contact
PCT/US2006/013987 WO2006113395A2 (en) 2005-04-15 2006-04-13 Parallel field effect transistor structure having a body contact

Publications (3)

Publication Number Publication Date
JP2008537339A JP2008537339A (ja) 2008-09-11
JP2008537339A5 JP2008537339A5 (enExample) 2009-08-27
JP4395192B2 true JP4395192B2 (ja) 2010-01-06

Family

ID=36710532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008506717A Expired - Fee Related JP4395192B2 (ja) 2005-04-15 2006-04-13 本体コンタクトを有する並列電界効果トランジスタ構造体

Country Status (8)

Country Link
US (1) US7084462B1 (enExample)
EP (1) EP1872402B1 (enExample)
JP (1) JP4395192B2 (enExample)
CN (1) CN100495704C (enExample)
AT (1) ATE454714T1 (enExample)
DE (1) DE602006011595D1 (enExample)
TW (1) TWI372461B (enExample)
WO (1) WO2006113395A2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8035140B2 (en) * 2007-07-26 2011-10-11 Infineon Technologies Ag Method and layout of semiconductor device with reduced parasitics
US8921190B2 (en) 2008-04-08 2014-12-30 International Business Machines Corporation Field effect transistor and method of manufacture
US7893494B2 (en) * 2008-06-18 2011-02-22 International Business Machines Corporation Method and structure for SOI body contact FET with reduced parasitic capacitance
CN102148158B (zh) * 2010-02-09 2013-03-27 中国科学院微电子研究所 一种体接触器件结构及其制造方法
CN103258813B (zh) * 2013-04-24 2016-08-24 上海华虹宏力半导体制造有限公司 部分耗尽soi mosfet的测试结构及其形成方法
US8933746B1 (en) 2013-07-10 2015-01-13 Astronics Advanced Electronic Systems Corp. Parallel FET solid state relay utilizing commutation FETs
FR3038775A1 (fr) 2015-07-09 2017-01-13 St Microelectronics Sa Prise de contact substrat pour un transistor mos dans un substrat soi, en particulier fdsoi
US10096708B2 (en) 2016-03-30 2018-10-09 Stmicroelectronics Sa Enhanced substrate contact for MOS transistor in an SOI substrate, in particular an FDSOI substrate
FR3053834B1 (fr) * 2016-07-05 2020-06-12 Stmicroelectronics Sa Structure de transistor
US10424664B2 (en) * 2016-12-14 2019-09-24 Globalfoundries Inc. Poly gate extension source to body contact
US11948978B2 (en) * 2020-04-24 2024-04-02 Qualcomm Incorporated Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage
CN112349784B (zh) * 2020-11-05 2022-07-29 武汉新芯集成电路制造有限公司 半导体器件及其制造方法
CN113327983B (zh) * 2021-05-26 2023-05-05 武汉新芯集成电路制造有限公司 半导体器件及其制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185280A (en) 1991-01-29 1993-02-09 Texas Instruments Incorporated Method of fabricating a soi transistor with pocket implant and body-to-source (bts) contact
USH1435H (en) * 1991-10-21 1995-05-02 Cherne Richard D SOI CMOS device having body extension for providing sidewall channel stop and bodytie
US5298773A (en) 1992-08-17 1994-03-29 United Technologies Corporation Silicon-on-insulator H-transistor layout for gate arrays
US5317181A (en) 1992-09-10 1994-05-31 United Technologies Corporation Alternative body contact for fully-depleted silicon-on-insulator transistors
US5635745A (en) * 1994-09-08 1997-06-03 National Semiconductor Corporation Analog multiplexer cell for mixed digital and analog signal inputs
US5821769A (en) 1995-04-21 1998-10-13 Nippon Telegraph And Telephone Corporation Low voltage CMOS logic circuit with threshold voltage control
US5821575A (en) 1996-05-20 1998-10-13 Digital Equipment Corporation Compact self-aligned body contact silicon-on-insulator transistor
JP3638377B2 (ja) 1996-06-07 2005-04-13 株式会社ルネサステクノロジ 半導体装置
US5811855A (en) 1997-12-29 1998-09-22 United Technologies Corporation SOI combination body tie
TW432545B (en) 1998-08-07 2001-05-01 Ibm Method and improved SOI body contact structure for transistors
US6387739B1 (en) 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
US6323522B1 (en) * 1999-01-08 2001-11-27 International Business Machines Corporation Silicon on insulator thick oxide structure and process of manufacture
US6154091A (en) 1999-06-02 2000-11-28 International Business Machines Corporation SOI sense amplifier with body contact structure
US6399989B1 (en) 1999-08-03 2002-06-04 Bae Systems Information And Electronic Systems Integration Inc. Radiation hardened silicon-on-insulator (SOI) transistor having a body contact
US6307237B1 (en) 1999-12-28 2001-10-23 Honeywell International Inc. L-and U-gate devices for SOI/SOS applications
US6255694B1 (en) 2000-01-18 2001-07-03 International Business Machines Corporation Multi-function semiconductor structure and method
US6433587B1 (en) 2000-03-17 2002-08-13 International Business Machines Corporation SOI CMOS dynamic circuits having threshold voltage control
JP4614522B2 (ja) 2000-10-25 2011-01-19 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5001494B2 (ja) 2001-08-28 2012-08-15 セイコーインスツル株式会社 絶縁性基板上に形成された電界効果トランジスタ
US6905919B2 (en) 2003-07-29 2005-06-14 Chartered Semiconductor Manufacturing Ltd. Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension

Also Published As

Publication number Publication date
WO2006113395A3 (en) 2007-03-08
EP1872402B1 (en) 2010-01-06
CN100495704C (zh) 2009-06-03
ATE454714T1 (de) 2010-01-15
JP2008537339A (ja) 2008-09-11
EP1872402A4 (en) 2008-06-11
TWI372461B (en) 2012-09-11
CN101142679A (zh) 2008-03-12
US7084462B1 (en) 2006-08-01
EP1872402A2 (en) 2008-01-02
DE602006011595D1 (de) 2010-02-25
WO2006113395A2 (en) 2006-10-26
TW200731531A (en) 2007-08-16

Similar Documents

Publication Publication Date Title
JP4360702B2 (ja) 半導体装置
US6005273A (en) Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors
US9178061B2 (en) Method for fabricating MOSFET on silicon-on-insulator with internal body contact
JP4395192B2 (ja) 本体コンタクトを有する並列電界効果トランジスタ構造体
US9837424B2 (en) Semiconductor device with anti-fuse memory element
EP1243028A1 (en) L- and u-gate devices for soi/sos applications
US20100320572A1 (en) Thin-Body Bipolar Device
US7824989B2 (en) Method for reducing overlap capacitance in field effect transistors
US9614516B2 (en) Devices for shielding a signal line over an active region
US12074205B2 (en) Transistor structure and related inverter
JP5153121B2 (ja) 電界効果トランジスタ・デバイスとその形成方法
TW200929522A (en) Semiconductor device
US20050127441A1 (en) Body contact layout for semiconductor-on-insulator devices
US20020053706A1 (en) Semiconductor device and signal processing system having SOI MOS transistor
US6225642B1 (en) Buried channel vertical double diffusion MOS device
JPH06209106A (ja) 半導体装置
KR950003238B1 (ko) 다중-전극을 이용한 논리소자의 구조
KR20010107571A (ko) 자체-접속 바디 결합부를 갖는 soi nfet
JPH05283684A (ja) Mos型トランジスタ及びゲ−トアレ−
JP2004055940A (ja) 横型mosトランジスタ

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081222

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090123

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20090529

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090529

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20090529

RD12 Notification of acceptance of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7432

Effective date: 20090529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20090529

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20090701

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090701

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20090714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090724

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20090807

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090807

TRDD Decision of grant or rejection written
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20091009

RD14 Notification of resignation of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7434

Effective date: 20091009

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091009

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091016

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121023

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121023

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131023

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees