JP4348015B2 - データ依存型電圧バイアス・レベルのための回路 - Google Patents

データ依存型電圧バイアス・レベルのための回路 Download PDF

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Publication number
JP4348015B2
JP4348015B2 JP2000583167A JP2000583167A JP4348015B2 JP 4348015 B2 JP4348015 B2 JP 4348015B2 JP 2000583167 A JP2000583167 A JP 2000583167A JP 2000583167 A JP2000583167 A JP 2000583167A JP 4348015 B2 JP4348015 B2 JP 4348015B2
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JP
Japan
Prior art keywords
signal
voltage
level
dac
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2000583167A
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English (en)
Japanese (ja)
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JP2002530921A5 (https=
JP2002530921A (ja
Inventor
ジョンソン,ルーク・エイ
シュワルツロウ,ジョン・ケイ
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2002530921A publication Critical patent/JP2002530921A/ja
Publication of JP2002530921A5 publication Critical patent/JP2002530921A5/ja
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Publication of JP4348015B2 publication Critical patent/JP4348015B2/ja
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/124Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
    • H03M1/1295Clamping, i.e. adjusting the DC level of the input signal to a predetermined value

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Dc Digital Transmission (AREA)
JP2000583167A 1998-11-12 1999-11-05 データ依存型電圧バイアス・レベルのための回路 Expired - Fee Related JP4348015B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/191,075 1998-11-12
US09/191,075 US6075476A (en) 1998-11-12 1998-11-12 Method and circuit for data dependent voltage bias level
PCT/US1999/026257 WO2000030261A1 (en) 1998-11-12 1999-11-05 Circuit for data dependent voltage bias level

Publications (3)

Publication Number Publication Date
JP2002530921A JP2002530921A (ja) 2002-09-17
JP2002530921A5 JP2002530921A5 (https=) 2006-12-21
JP4348015B2 true JP4348015B2 (ja) 2009-10-21

Family

ID=22704038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000583167A Expired - Fee Related JP4348015B2 (ja) 1998-11-12 1999-11-05 データ依存型電圧バイアス・レベルのための回路

Country Status (7)

Country Link
US (2) US6075476A (https=)
JP (1) JP4348015B2 (https=)
KR (1) KR100569749B1 (https=)
CN (1) CN1160865C (https=)
AU (1) AU1471000A (https=)
DE (1) DE19983726B4 (https=)
WO (1) WO2000030261A1 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075476A (en) * 1998-11-12 2000-06-13 Intel Corporation Method and circuit for data dependent voltage bias level
JP2002107424A (ja) * 2000-10-02 2002-04-10 Hitachi Ltd 半導体集積回路
US6518893B1 (en) 2001-08-24 2003-02-11 Xilinx, Inc. Method and apparatus for multilevel signal operation
KR101119107B1 (ko) * 2005-12-08 2012-03-16 엘지전자 주식회사 이동통신용 단말
US7233274B1 (en) * 2005-12-20 2007-06-19 Impinj, Inc. Capacitive level shifting for analog signal processing
US7656226B2 (en) * 2006-03-31 2010-02-02 Intel Corporation Switched capacitor equalizer with offset voltage cancelling
US7649388B2 (en) * 2006-03-31 2010-01-19 Intel Corporation Analog voltage recovery circuit
US9207116B2 (en) 2013-02-12 2015-12-08 Gentex Corporation Light sensor
US8717070B1 (en) * 2013-03-12 2014-05-06 Cypress Semiconductor Corporation Multifunctional configurable analog circuit block, methods, and integrated circuit devices having the same
CN105247827B (zh) 2013-06-27 2019-06-25 英特尔公司 低功率均衡器及其训练
KR102349415B1 (ko) * 2017-08-07 2022-01-11 삼성전자주식회사 펄스 진폭 변조 송신기 및 펄스 진폭 변조 수신기
CN115278402B (zh) * 2022-07-27 2023-09-01 南京慧尔视智能科技有限公司 一种信息采集设备及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034746A (en) * 1988-09-21 1991-07-23 International Business Machines Corporation Analog-to-digital converter for computer disk file servo position error signal
US5371552A (en) * 1991-10-31 1994-12-06 North American Philips Corporation Clamping circuit with offset compensation for analog-to-digital converters
JP3353260B2 (ja) * 1994-09-30 2002-12-03 シャープ株式会社 インターフェイス回路
US6075476A (en) * 1998-11-12 2000-06-13 Intel Corporation Method and circuit for data dependent voltage bias level

Also Published As

Publication number Publication date
KR100569749B1 (ko) 2006-04-11
CN1333949A (zh) 2002-01-30
CN1160865C (zh) 2004-08-04
JP2002530921A (ja) 2002-09-17
US6342848B1 (en) 2002-01-29
KR20010080431A (ko) 2001-08-22
DE19983726T1 (de) 2001-10-04
US6075476A (en) 2000-06-13
AU1471000A (en) 2000-06-05
DE19983726B4 (de) 2011-04-14
WO2000030261A1 (en) 2000-05-25

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