JP4307370B2 - 薄膜トランジスター及びその製造方法 - Google Patents
薄膜トランジスター及びその製造方法 Download PDFInfo
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- JP4307370B2 JP4307370B2 JP2004377840A JP2004377840A JP4307370B2 JP 4307370 B2 JP4307370 B2 JP 4307370B2 JP 2004377840 A JP2004377840 A JP 2004377840A JP 2004377840 A JP2004377840 A JP 2004377840A JP 4307370 B2 JP4307370 B2 JP 4307370B2
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- 239000010409 thin film Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000013078 crystal Substances 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 45
- 239000004065 semiconductor Substances 0.000 claims description 40
- 239000010408 film Substances 0.000 claims description 39
- 239000003054 catalyst Substances 0.000 claims description 33
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000002425 crystallisation Methods 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 230000008025 crystallization Effects 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000005401 electroluminescence Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 130
- 238000001069 Raman spectroscopy Methods 0.000 description 5
- 238000011109 contamination Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Condensed Matter Physics & Semiconductors (AREA)
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- Crystallography & Structural Chemistry (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
11、47 半導体層パターン
12、48 ソース領域
13、49 ドレーン領域
14、50 チャンネル層
15、51 ジャンクション領域
16、52 ゲート絶縁膜
17、53 ゲート電極
18 層間絶縁膜
19 ソース電極
20 ドレーン電極
21 トラップ
41 非晶質シリコン層
42 第1のキャッピング層パターン
43 チャンネル形成部
44 第2ののキャッピング層
45 金属触媒
46 シード
Claims (23)
- 基板と、
前記基板上に形成された半導体層パターンと、
前記半導体層パターン上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、を含み、
前記半導体層パターン内にはシード又は結晶粒境界が存在するが、ジャンクション領域にはシード又は結晶粒境界が存在せず、
チャンネル領域にシードが存在せず、
前記シードは、前記ジャンクション領域からコンタクトホール方向に1〜3μm離隔された所に形成されることを特徴とする薄膜トランジスター。 - 前記半導体層パターン内に存在する結晶粒境界は、前記半導体層パターンのソース/ドレイン領域及び/又はチャンネル層に存在し、
前記シードはソース領域またはドレイン領域に存在することを特徴とする請求項1に記載の薄膜トランジスター。 - 前記ジャンクション領域は、ジャンクションからソース領域又はドレイン領域に1μmまで形成されることを特徴とする請求項1に記載の薄膜トランジスター。
- 前記ジャンクション領域の結晶化比率は、0.7〜0.9であることを特徴とする請求項1に記載の薄膜トランジスター。
- 前記基板と前記半導体層パターンとの間に形成されたバッファー層をさらに含むことを特徴とする請求項1に記載の薄膜トランジスター。
- 前記バッファー層は、シリコン窒化膜又はシリコン酸化膜からなることを特徴とする請求項5に記載の薄膜トランジスター。
- 前記薄膜トランジスターは、液晶表示素子又は有機電界発光素子として使用されることを特徴とする請求項1に記載の薄膜トランジスター。
- 基板上に非晶質シリコン層を形成する段階と、
前記非晶質シリコン層を結晶化しパターニングして半導体層パターンを形成する段階と、
前記半導体層パターン上にゲート絶縁膜を形成する段階と、
前記ゲート絶縁膜上にゲート電極を形成する段階と、を含み、
前記半導体層パターン内にはシード又は結晶粒境界が存在するが、ジャンクション領域にはシード又は結晶粒境界が存在せず、
チャンネル領域にシードが存在せず、
前記シードは、前記ジャンクション領域からコンタクトホール方向に1〜3μm離隔された所に形成されることを特徴とする薄膜トランジスターの製造方法。 - 前記半導体層パターン内に存在する結晶粒境界は、前記半導体層パターンのソース/ドレイン領域及び/又はチャンネル層に存在し、
前記シードはソース領域またはドレイン領域に存在することを特徴とする請求項8に記載の薄膜トランジスターの製造方法。 - 前記半導体層パターンを形成する段階は、前記非晶質シリコン層上に第1のキャッピング層を形成した後にパターニングする段階と、
前記第1のキャッピング層パターン上及び該第1のキャッピング層パターンが除去されて露出された非晶質シリコン上に第2のキャッピング層を形成する段階と、
前記第2のキャッピング層上に金属触媒層を形成する段階と、
前記金属触媒を拡散させる段階と、
前記非晶質シリコン層を結晶化して多結晶シリコン層を形成する段階と、を含むことを特徴とする請求項8に記載の薄膜トランジスターの製造方法。 - 前記第1のキャッピング層は、前記シードが前記ジャンクション領域からコンタクトホール方向に1〜3μm離隔された所に形成されるようにパターニングすることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記第1のキャッピング層パターンは、シリコン窒化膜又はシリコン酸化膜からなることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記第2のキャッピング層は、シリコン窒化膜又はシリコン酸化膜からなることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記第1のキャッピング層パターンは、第2のキャッピング層より厚いことを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記第1のキャッピング層パターンは、第2のキャッピング層より高密度であることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記第1のキャッピング層又は第2のキャッピング層は、プラズマ強化化学気相蒸着(PECVD)法を用いて形成することを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記金属触媒は、ニッケルであることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記金属触媒層は、プラズマ化学気相法(CVD)又はスパッター方法を用いて形成することを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記金属触媒の拡散は、熱処理により行われることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記熱処理は、200〜700℃で行われることを特徴とする請求項19に記載の薄膜トランジスターの製造方法。
- 前記非晶質シリコン層の結晶化は、熱処理により行われることを特徴とする請求項10に記載の薄膜トランジスターの製造方法。
- 前記熱処理は、400〜1000℃で行われることを特徴とする請求項21に記載の薄膜トランジスターの製造方法。
- 前記基板と前記非晶質シリコン層との間にバッファー層を形成する段階をさらに含むことを特徴とする請求項8に記載の薄膜トランジスターの製造方法。
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KR100712101B1 (ko) * | 2004-06-30 | 2007-05-02 | 삼성에스디아이 주식회사 | 박막트랜지스터 및 그의 제조 방법 |
KR100611659B1 (ko) * | 2004-07-07 | 2006-08-10 | 삼성에스디아이 주식회사 | 박막트랜지스터 및 그의 제조 방법 |
KR100770268B1 (ko) * | 2006-05-18 | 2007-10-25 | 삼성에스디아이 주식회사 | 박막트랜지스터의 제조방법 |
KR100770269B1 (ko) | 2006-05-18 | 2007-10-25 | 삼성에스디아이 주식회사 | 박막트랜지스터의 제조방법 |
KR100796613B1 (ko) * | 2006-12-18 | 2008-01-22 | 삼성에스디아이 주식회사 | 레이저를 이용한 다결정 실리콘 결정화 방법 및 그를이용한 박막 트랜지스터의 제조 방법 |
KR100796614B1 (ko) * | 2006-12-19 | 2008-01-22 | 삼성에스디아이 주식회사 | 박막트랜지스터의 제조방법 |
JPWO2009128465A1 (ja) * | 2008-04-16 | 2011-08-04 | 日本電気株式会社 | サービス変更部品生成システム、方法及びプログラム |
KR101125565B1 (ko) * | 2009-11-13 | 2012-03-23 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그를 구비하는 유기전계발광표시장치 및 그들의 제조방법 |
KR102245780B1 (ko) * | 2014-11-03 | 2021-04-29 | 삼성디스플레이 주식회사 | 레이저 결정화 시스템, 레이저 결정화방법 및 표시장치의 제조방법 |
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JP2814049B2 (ja) * | 1993-08-27 | 1998-10-22 | 株式会社半導体エネルギー研究所 | 半導体装置およびその作製方法 |
JP3844526B2 (ja) | 1994-04-13 | 2006-11-15 | 株式会社半導体エネルギー研究所 | 結晶性珪素膜作製方法 |
US6326248B1 (en) * | 1994-06-02 | 2001-12-04 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating semiconductor device |
JP3662479B2 (ja) | 1994-06-22 | 2005-06-22 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP3227392B2 (ja) | 1996-09-27 | 2001-11-12 | シャープ株式会社 | 半導体装置およびその製造方法 |
JPH10199807A (ja) | 1996-12-27 | 1998-07-31 | Semiconductor Energy Lab Co Ltd | 結晶性珪素膜の作製方法 |
KR100340124B1 (ko) * | 1998-02-10 | 2003-01-29 | 주승기 | 박막트랜지스터 제조방법 |
US6278130B1 (en) * | 1998-05-08 | 2001-08-21 | Seung-Ki Joo | Liquid crystal display and fabricating method thereof |
JP2000133807A (ja) * | 1998-10-22 | 2000-05-12 | Seiko Epson Corp | 多結晶シリコン薄膜トランジスタ |
KR100387122B1 (ko) * | 2000-09-15 | 2003-06-12 | 피티플러스(주) | 백 바이어스 효과를 갖는 다결정 실리콘 박막 트랜지스터의 제조 방법 |
KR100439345B1 (ko) * | 2000-10-31 | 2004-07-07 | 피티플러스(주) | 폴리실리콘 활성층을 포함하는 박막트랜지스터 및 제조 방법 |
KR100378259B1 (ko) * | 2001-01-20 | 2003-03-29 | 주승기 | 결정질 활성층을 포함하는 박막트랜지스터 제작 방법 및장치 |
JP4358998B2 (ja) * | 2001-02-01 | 2009-11-04 | 株式会社日立製作所 | 薄膜トランジスタ装置およびその製造方法 |
US6426246B1 (en) * | 2001-02-21 | 2002-07-30 | United Microelectronics Corp. | Method for forming thin film transistor with lateral crystallization |
KR100380758B1 (ko) | 2001-07-11 | 2003-04-18 | (주)동광알파 | 디지털 스위칭수단을 포함하는 전기작동식 도어잠금장치 |
KR100473996B1 (ko) | 2002-01-09 | 2005-03-08 | 장 진 | 비정질 실리콘의 결정화 방법 |
KR100470274B1 (ko) * | 2002-11-08 | 2005-02-05 | 진 장 | 덮개층을 이용한 비정질 물질의 상 변화 방법 |
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2004
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- 2004-12-22 US US11/017,667 patent/US7825411B2/en not_active Expired - Fee Related
- 2004-12-27 JP JP2004377840A patent/JP4307370B2/ja not_active Expired - Fee Related
- 2004-12-31 CN CNB2004100758877A patent/CN100448029C/zh not_active Expired - Fee Related
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US7825411B2 (en) | 2010-11-02 |
JP2006013425A (ja) | 2006-01-12 |
CN1713397A (zh) | 2005-12-28 |
KR100623689B1 (ko) | 2006-09-19 |
US20050285110A1 (en) | 2005-12-29 |
US7601565B2 (en) | 2009-10-13 |
CN100448029C (zh) | 2008-12-31 |
KR20050122136A (ko) | 2005-12-28 |
US20060183273A1 (en) | 2006-08-17 |
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