JP4298539B2 - 電力用半導体装置の製造方法 - Google Patents
電力用半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 151
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000000034 method Methods 0.000 title claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000005304 joining Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 38
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 description 23
- 238000000576 coating method Methods 0.000 description 23
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 230000005684 electric field Effects 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は本実施の形態に係る電力用半導体装置の中核部分の構造を示す上面図である。図2は図1のA1−A1線断面図である。
図3は、本実施の形態に係る電力用半導体装置の中核部分を示す上面図である。図4は図3のA2−A2線断面図を示している。本実施の形態においては、半導体チップ1のリードフレーム2との接合とは反対側の面の外周部を覆うように表面コート膜4が形成されている。その他の構成は実施の形態1と同様であり、同一の構成には同一の符号を付し、重複する説明は省略する。
図5は本実施の形態に係る電力用半導体装置の中核部分を示す図である。図6は、図5のA3−A3線断面図を示している。本実施の形態では、実施の形態1又は2において、環状体3の内周側面9の少なくとも一部を半導体チップ1の外周側面8に隣接するようにしている。
図7は、本実施の形態に係る電力用半導体装置の中核部分を示す上面図である。図8は、図7のB1−B1線断面図を示している。本実施の形態では、リードフレーム2に、溝部7が形成されている。溝部7の深さは、半導体チップ1の高さと同等若しくは深くなるように形成されている。図8の例では、溝部7の深さは半導体チップ1の高さと同等になるように構成されている。この溝部7は、例えばプレス加工法若しくはエッチング法等により形成される。
図10は本実施の形態に係る電力用半導体装置の中核部分を示す図である。図11は、図10のB2−B2線断面図を示している。本実施の形態においては、半導体チップ1の接合とは反対側の面の外周部を覆うように表面コート膜4が形成されている。その他の構成は実施の形態4と同様であり、同一の構成には同一の符号を付し、重複する説明は省略する。
図12は、本実施の形態に係る電力用半導体装置の中核部分を示す上面図である。また、図13は図12のC1−C1線断面図を示している。
図14は、本実施の形態に係る電力用半導体装置の中核部分を示す上面図である。また、図15は、図14のC2−C2線断面図を示している。本実施の形態は実施の形態2と実施の形態4の組み合わせであって、実施の形態2又は実施の形態4と同一の構成には同一の符号を付し重複する説明は省略する。
本実施の形態では、実施の形態1から実施の形態6において表面コート材が硬化した後に環状体3(例えば図1参照)を取り外すことを特徴としている。
本実施の形態では、実施の形態1〜2又は実施の形態5〜6において、環状体3(例えば図1参照)をプラスチック製としている。
Claims (4)
- (a)リードフレームの主面に形成された溝部内に半導体チップを接合する工程と、
(c1)前記半導体チップの電極と外部電極とを配線する工程と、
(c2)前記溝部を囲うように環状体を前記リードフレームの主面に配置する工程と、
(d)前記半導体チップの接合とは反対側の面の外周部を覆うように表面コート膜を形成する工程と、
(e)前記環状体を取り外す工程とを備えることを特徴とする電力用半導体装置の製造方法。 - (a)リードフレームの半導体チップ接合領域に半導体チップを接合する工程と、
(b)前記半導体チップ接合領域を囲うように前記リードフレームの主面に環状体を配置する工程と、
(c)前記半導体チップの電極と外部電極とを配線する工程と、
(d)前記半導体チップの接合とは反対側の面の外周部を覆うように表面コート膜を形成する工程と、
(e)前記環状体を取り外す工程とを備えることを特徴とする電力用半導体装置の製造方法。 - 前記工程(a)若しくは前記工程(b)は、前記環状体の内周側面の少なくとも一部が前記半導体チップの外周側面に隣接するように、前記半導体チップ若しくは前記環状体を配置することを特徴とする請求項1又は2に記載の電力用半導体装置の製造方法。
- 前記工程(d)は、前記半導体チップの少なくとも表面のうち接合されていないところの全体を覆うように表面コート膜を形成することを特徴とする請求項1から3の何れか1つに記載の電力用半導体装置の製造方法。
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JP4298539B2 true JP4298539B2 (ja) | 2009-07-22 |
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