JP4268726B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4268726B2
JP4268726B2 JP15191399A JP15191399A JP4268726B2 JP 4268726 B2 JP4268726 B2 JP 4268726B2 JP 15191399 A JP15191399 A JP 15191399A JP 15191399 A JP15191399 A JP 15191399A JP 4268726 B2 JP4268726 B2 JP 4268726B2
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JP
Japan
Prior art keywords
circuit
clock signal
clock
power supply
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15191399A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000339959A (ja
JP2000339959A5 (enExample
Inventor
甚吾 中西
博之 牧野
勉 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP15191399A priority Critical patent/JP4268726B2/ja
Priority to US09/437,739 priority patent/US6278303B1/en
Publication of JP2000339959A publication Critical patent/JP2000339959A/ja
Publication of JP2000339959A5 publication Critical patent/JP2000339959A5/ja
Application granted granted Critical
Publication of JP4268726B2 publication Critical patent/JP4268726B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Power Sources (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP15191399A 1999-05-31 1999-05-31 半導体装置 Expired - Fee Related JP4268726B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15191399A JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置
US09/437,739 US6278303B1 (en) 1999-05-31 1999-11-10 Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191399A JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置

Publications (3)

Publication Number Publication Date
JP2000339959A JP2000339959A (ja) 2000-12-08
JP2000339959A5 JP2000339959A5 (enExample) 2006-06-15
JP4268726B2 true JP4268726B2 (ja) 2009-05-27

Family

ID=15528946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191399A Expired - Fee Related JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置

Country Status (2)

Country Link
US (1) US6278303B1 (enExample)
JP (1) JP4268726B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4008583B2 (ja) * 1998-07-22 2007-11-14 株式会社沖データ 電子機器
KR100543934B1 (ko) * 2000-05-31 2006-01-23 주식회사 하이닉스반도체 반도체 메모리 장치에서 어드레스 및 데이터 억세스타임을 고속으로 하는 제어 및 어드레스 장치
JP2002093167A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
US7177208B2 (en) * 2005-03-11 2007-02-13 Micron Technology, Inc. Circuit and method for operating a delay-lock loop in a power saving manner
JP4862588B2 (ja) * 2006-09-27 2012-01-25 ソニー株式会社 クロック制御回路および半導体集積回路
KR100917630B1 (ko) * 2008-04-30 2009-09-17 주식회사 하이닉스반도체 지연 고정 루프 회로
KR101027688B1 (ko) 2009-09-30 2011-04-12 주식회사 하이닉스반도체 반도체 장치
KR101253443B1 (ko) * 2011-06-09 2013-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
US9438254B1 (en) * 2015-05-21 2016-09-06 Stmicroelectronics International N.V. Charge pump circuit for a phase locked loop

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025720A (en) * 1975-05-30 1977-05-24 Gte Automatic Electric Laboratories Incorporated Digital bit rate converter
US5339278A (en) * 1993-04-12 1994-08-16 Motorola, Inc. Method and apparatus for standby recovery in a phase locked loop
JP3048495B2 (ja) 1994-01-07 2000-06-05 沖電気工業株式会社 クロック回路
US5703537A (en) * 1996-07-03 1997-12-30 Microclock Incorporated Phase-locked loop clock circuit for generation of audio sampling clock signals from video reference signals
KR100295045B1 (ko) * 1998-06-23 2001-07-12 윤종용 지연동기루프(dll)를구비한반도체메모리장치

Also Published As

Publication number Publication date
US6278303B1 (en) 2001-08-21
JP2000339959A (ja) 2000-12-08

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