JP4267655B2 - 電子回路、該電子回路として構成された差分送信機、及び、自己直列終端送信機を形成する方法(振幅制御、プリ・エンファシス制御及びスルー・レート制御のためのセグメント化と振幅精度及び高電圧保護のための電圧調整とを有する自己直列終端シリアル・リンク送信機) - Google Patents
電子回路、該電子回路として構成された差分送信機、及び、自己直列終端送信機を形成する方法(振幅制御、プリ・エンファシス制御及びスルー・レート制御のためのセグメント化と振幅精度及び高電圧保護のための電圧調整とを有する自己直列終端シリアル・リンク送信機) Download PDFInfo
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- JP4267655B2 JP4267655B2 JP2006284417A JP2006284417A JP4267655B2 JP 4267655 B2 JP4267655 B2 JP 4267655B2 JP 2006284417 A JP2006284417 A JP 2006284417A JP 2006284417 A JP2006284417 A JP 2006284417A JP 4267655 B2 JP4267655 B2 JP 4267655B2
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- segment
- pull
- input
- buffer
- transmitter
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- 238000000034 method Methods 0.000 title claims description 15
- 230000011218 segmentation Effects 0.000 title description 7
- 239000000872 buffer Substances 0.000 claims description 68
- 230000003111 delayed effect Effects 0.000 claims description 17
- 230000000295 complement effect Effects 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 238000013461 design Methods 0.000 description 14
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
- H03K17/163—Soft switching
- H03K17/164—Soft switching using parallel switching arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/263,138 US7307447B2 (en) | 2005-10-27 | 2005-10-27 | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007124644A JP2007124644A (ja) | 2007-05-17 |
| JP2007124644A5 JP2007124644A5 (enExample) | 2008-12-11 |
| JP4267655B2 true JP4267655B2 (ja) | 2009-05-27 |
Family
ID=38003123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006284417A Expired - Fee Related JP4267655B2 (ja) | 2005-10-27 | 2006-10-18 | 電子回路、該電子回路として構成された差分送信機、及び、自己直列終端送信機を形成する方法(振幅制御、プリ・エンファシス制御及びスルー・レート制御のためのセグメント化と振幅精度及び高電圧保護のための電圧調整とを有する自己直列終端シリアル・リンク送信機) |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7307447B2 (enExample) |
| JP (1) | JP4267655B2 (enExample) |
| CN (1) | CN100571226C (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9160403B2 (en) | 2012-06-26 | 2015-10-13 | Fujitsu Limited | Signal transmission circuit, signal transmission system, and signal transmission method |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005024643B4 (de) * | 2005-05-25 | 2013-09-05 | Krohne S.A. | Abtastschaltung |
| JP2007036848A (ja) * | 2005-07-28 | 2007-02-08 | Ricoh Co Ltd | ドライバ回路 |
| JP5465376B2 (ja) * | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置、およびドライバ制御方法 |
| US7995660B2 (en) * | 2007-10-31 | 2011-08-09 | International Business Machines Corporation | Receiver termination circuit for a high speed direct current (DC) serial link |
| US7936180B2 (en) * | 2008-02-01 | 2011-05-03 | Mediatek Inc. | Serial link transmitter |
| US7511530B1 (en) * | 2008-07-25 | 2009-03-31 | International Business Machines Corporation | Nodal charge compensation for SST driver having data mux in output stage |
| JP5540479B2 (ja) * | 2008-08-26 | 2014-07-02 | 株式会社リコー | ドライバ回路 |
| KR20110003725A (ko) * | 2009-07-06 | 2011-01-13 | 삼성전자주식회사 | 출력 전압의 스윙 폭을 제어하는 송수신기 및 그 방법 |
| JP5615367B2 (ja) * | 2009-09-14 | 2014-10-29 | ラムバス・インコーポレーテッド | 高分解能出力ドライバ |
| US8395411B2 (en) * | 2010-10-08 | 2013-03-12 | Qualcomm Incorporated | Constant impedance line driver with digitally controlled edge rate |
| US8451031B2 (en) | 2010-11-11 | 2013-05-28 | Advanced Micro Devices, Inc. | Adjustable finite impulse response transmitter |
| US8432184B2 (en) * | 2011-04-22 | 2013-04-30 | Mark Lasky | Termination device and system and method for termination for an alarm system peripheral device |
| US8760188B2 (en) * | 2011-06-30 | 2014-06-24 | Silicon Image, Inc. | Configurable multi-dimensional driver and receiver |
| US8878568B1 (en) * | 2011-09-12 | 2014-11-04 | Semtech Corporation | High-speed SSR transmit driver |
| US8410818B1 (en) * | 2012-02-14 | 2013-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | High speed communication interface with an adaptive swing driver to reduce power consumption |
| KR101874584B1 (ko) | 2012-04-03 | 2018-07-04 | 삼성전자주식회사 | 전압 방식 구동기 |
| US8618833B1 (en) | 2012-06-19 | 2013-12-31 | International Business Machines Corporation | Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization |
| US9048824B2 (en) * | 2012-12-12 | 2015-06-02 | Intel Corporation | Programmable equalization with compensated impedance |
| US8989254B2 (en) | 2012-12-21 | 2015-03-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Single serdes transmitter driver design for both ethernet and peripheral component interconnect express applications |
| US8929040B2 (en) | 2013-01-31 | 2015-01-06 | International Business Machines Corporation | ESD protection device for SST transmitter |
| US9419736B2 (en) * | 2013-03-15 | 2016-08-16 | Gigoptix-Terasquare Korea Co., Ltd. | Low-power CML-less transmitter architecture |
| US8912819B2 (en) * | 2013-03-18 | 2014-12-16 | Mediatek Inc. | Termination circuits capable of receiving data signals in different formats for performing impedance matching |
| KR101427517B1 (ko) | 2013-03-18 | 2014-08-07 | 고려대학교 산학협력단 | 데이터 송신 방법 및 장치 |
| US9337807B2 (en) * | 2014-09-30 | 2016-05-10 | Qualcomm Incorporated | Output driver circuit with auto-equalization based on drive strength calibration |
| WO2017173118A1 (en) * | 2016-03-30 | 2017-10-05 | Jariet Technologies, Inc. | Hybrid digital-to-analog conversion systems |
| US10583461B2 (en) | 2017-07-06 | 2020-03-10 | Texas Instruments Incorporated | Configurable pulser circuit operable across a range of supply voltages |
| US10192590B1 (en) * | 2017-10-19 | 2019-01-29 | Globalfoundries Inc. | Differential voltage generator |
| US10892759B1 (en) * | 2020-02-19 | 2021-01-12 | Amazing Microelectronic Corp. | Bus driver module with controlled circuit and transition controlled circuit thereof |
| US11764733B2 (en) * | 2021-09-23 | 2023-09-19 | Qualcomm Incorporated | C-PHY receiver with self-regulated common mode servo loop |
| JP2024007690A (ja) | 2022-07-06 | 2024-01-19 | 富士通株式会社 | 光送信機 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5194761A (en) * | 1989-06-26 | 1993-03-16 | Dallas Semiconductor Corp. | Waveshaping subsystem using converter and delay lines |
| GB2305082B (en) * | 1995-09-06 | 1999-10-06 | At & T Corp | Wave shaping transmit circuit |
| US5986489A (en) * | 1996-04-03 | 1999-11-16 | Cypress Semiconductor Corp. | Slew rate control circuit for an integrated circuit |
| JPH1125678A (ja) * | 1997-06-27 | 1999-01-29 | Samsung Electron Co Ltd | 出力ドライバ及び半導体メモリ装置 |
| KR100318685B1 (ko) * | 1997-08-22 | 2002-02-19 | 윤종용 | 프로그래머블임피던스콘트롤회로 |
| DE19919140B4 (de) * | 1998-04-29 | 2011-03-31 | National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara | Niederspannungs-Differenzsignaltreiber mit Vorverstärkerschaltung |
| US6313682B1 (en) * | 1999-12-08 | 2001-11-06 | Analog Devices, Inc. | Pulse generation circuit and method with transmission pre-emphasis |
| US6268750B1 (en) * | 2000-01-11 | 2001-07-31 | Agilent Technologies, Inc. | Flattened resistance response for an electrical output driver |
| US6256235B1 (en) * | 2000-06-23 | 2001-07-03 | Micron Technology, Inc. | Adjustable driver pre-equalization for memory subsystems |
| US6353346B1 (en) * | 2000-10-06 | 2002-03-05 | National Semiconductor Corporation | Apparatus and method for a programmable adaptive output driver |
| US6704818B1 (en) * | 2000-12-29 | 2004-03-09 | Intel Corporation | Voltage-mode driver with pre-emphasis, slew-rate control and source termination |
| US6707324B1 (en) * | 2002-11-20 | 2004-03-16 | Via Technologies, Inc. | Low ground bounce output driver |
| US6771097B1 (en) * | 2003-04-22 | 2004-08-03 | Broadcom Corporation | Series terminated CMOS output driver with impedance calibration |
| US7164600B2 (en) * | 2004-12-10 | 2007-01-16 | Micron Technology Inc | Reducing DQ pin capacitance in a memory device |
| TWI277302B (en) * | 2004-12-28 | 2007-03-21 | Ind Tech Res Inst | Clock and data recovery circuit |
-
2005
- 2005-10-27 US US11/263,138 patent/US7307447B2/en active Active
-
2006
- 2006-10-18 JP JP2006284417A patent/JP4267655B2/ja not_active Expired - Fee Related
- 2006-10-20 CN CNB2006101371216A patent/CN100571226C/zh active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9160403B2 (en) | 2012-06-26 | 2015-10-13 | Fujitsu Limited | Signal transmission circuit, signal transmission system, and signal transmission method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100571226C (zh) | 2009-12-16 |
| US20070103186A1 (en) | 2007-05-10 |
| CN1956427A (zh) | 2007-05-02 |
| JP2007124644A (ja) | 2007-05-17 |
| US7307447B2 (en) | 2007-12-11 |
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