JP4266502B2 - 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 - Google Patents

半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 Download PDF

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JP4266502B2
JP4266502B2 JP2000247159A JP2000247159A JP4266502B2 JP 4266502 B2 JP4266502 B2 JP 4266502B2 JP 2000247159 A JP2000247159 A JP 2000247159A JP 2000247159 A JP2000247159 A JP 2000247159A JP 4266502 B2 JP4266502 B2 JP 4266502B2
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layer
dual damascene
copper
metal layer
damascene opening
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Expired - Fee Related
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Japanese (ja)
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JP2001176879A (ja
JP2001176879A5 (enExample
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メイ・シェン・チョウ
ポール・ウォク・キュン・ホー
サブハッシュ・ギュプタ
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チャータード・セミコンダクター・マニュファクチャリング・リミテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2000247159A 1999-09-07 2000-08-17 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 Expired - Fee Related JP4266502B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/390783 1999-09-07
US09/390,783 US6251786B1 (en) 1999-09-07 1999-09-07 Method to create a copper dual damascene structure with less dishing and erosion

Publications (3)

Publication Number Publication Date
JP2001176879A JP2001176879A (ja) 2001-06-29
JP2001176879A5 JP2001176879A5 (enExample) 2007-10-04
JP4266502B2 true JP4266502B2 (ja) 2009-05-20

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Family Applications (1)

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JP2000247159A Expired - Fee Related JP4266502B2 (ja) 1999-09-07 2000-08-17 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法

Country Status (4)

Country Link
US (1) US6251786B1 (enExample)
EP (1) EP1083596B1 (enExample)
JP (1) JP4266502B2 (enExample)
SG (1) SG121686A1 (enExample)

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US6368953B1 (en) 2000-05-09 2002-04-09 International Business Machines Corporation Encapsulated metal structures for semiconductor devices and MIM capacitors including the same
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US6709874B2 (en) * 2001-01-24 2004-03-23 Infineon Technologies Ag Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
US6586326B2 (en) * 2001-03-13 2003-07-01 Lsi Logic Corporation Metal planarization system
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KR100435784B1 (ko) * 2001-12-21 2004-06-12 동부전자 주식회사 반도체 소자의 금속배선 형성 방법
KR100444301B1 (ko) * 2001-12-29 2004-08-16 주식회사 하이닉스반도체 질화막 ｃｍｐ를 이용한 다마신 금속 게이트 형성 방법
JP4088120B2 (ja) * 2002-08-12 2008-05-21 株式会社ルネサステクノロジ 半導体装置
US6670274B1 (en) * 2002-10-01 2003-12-30 Taiwan Semiconductor Manufacturing Company Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure
US6940108B2 (en) * 2002-12-05 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Slot design for metal interconnects
US7825516B2 (en) * 2002-12-11 2010-11-02 International Business Machines Corporation Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
KR20040060563A (ko) * 2002-12-30 2004-07-06 동부전자 주식회사 반도체 소자 제조방법 및 구조
US7294241B2 (en) * 2003-01-03 2007-11-13 Chartered Semiconductor Manufacturing Ltd. Method to form alpha phase Ta and its application to IC manufacturing
US20040185992A1 (en) * 2003-03-18 2004-09-23 Tisdale Lucien E. Method and apparatus for making a packaging article and packaging article made by the method and apparatus
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US20050079703A1 (en) * 2003-10-09 2005-04-14 Applied Materials, Inc. Method for planarizing an interconnect structure
US7183199B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of reducing the pattern effect in the CMP process
US20050139292A1 (en) * 2003-12-31 2005-06-30 Suresh Ramarajan Method and apparatus for minimizing thickness-to-planarity and dishing in CMP
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US20060205204A1 (en) * 2005-03-14 2006-09-14 Michael Beck Method of making a semiconductor interconnect with a metal cap
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
KR100729126B1 (ko) * 2005-11-15 2007-06-14 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그 형성 방법
US7432205B2 (en) * 2005-12-15 2008-10-07 United Microelectronics Corp. Method for controlling polishing process
CN100477120C (zh) * 2005-12-30 2009-04-08 联华电子股份有限公司 抛光工艺的控制方法
US7863183B2 (en) * 2006-01-18 2011-01-04 International Business Machines Corporation Method for fabricating last level copper-to-C4 connection with interfacial cap structure
US7619310B2 (en) * 2006-11-03 2009-11-17 Infineon Technologies Ag Semiconductor interconnect and method of making same
US7893459B2 (en) 2007-04-10 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structures with reduced moisture-induced reliability degradation
US20090039512A1 (en) * 2007-08-08 2009-02-12 International Business Machines Corporation Electromigration resistant interconnect structure
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US8629063B2 (en) 2011-06-08 2014-01-14 International Business Machines Corporation Forming features on a substrate having varying feature densities
KR102085086B1 (ko) 2013-10-29 2020-03-05 삼성전자주식회사 반도체 장치 및 그 제조방법
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Also Published As

Publication number Publication date
US6251786B1 (en) 2001-06-26
EP1083596B1 (en) 2012-08-22
JP2001176879A (ja) 2001-06-29
EP1083596A1 (en) 2001-03-14
SG121686A1 (en) 2006-05-26

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