JP4249684B2 - 半導体記憶装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 188
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Description
T.Ohsawa他IEEE Journal of Solid-State Circuits vol.37,no.11(2002)pp.1510−1522
順方向、或いは逆方向バイアスが印加されるようにすることによって、チャネル領域4に対して多数キャリアを注入、又は放出するようにしてもよい。
憶装置は、ソース/ドレイン層25をチャネル領域4の両端に設けるのではなく、チャネル領域4の下部に設けた点で、上述の実施例1の半導体記憶装置と異なるが、これ以外の構成は同じであり、同一構成部分には同一符号を付して説明は省略する。
記憶装置Hのソース/ドレイン層5、6(25)は、相互接続されて列毎に共通であるSL線(以下、単に「SL」と言う、又SL−1は第1番目のSLで、SL−Nは第N番目のSLを示す)に接続されている。又半導体記憶装置Hの2つのゲート電極9、10(29、30)のうち、一方のゲート電極10(30)は、列毎に共通であるFGL線(以下、単に「FGL」と言う、又FGL−1は第1番目のFGLで、FGL−Nは第N番目のFGLを示す)に接続されており、他方のゲート電極9(29)は、行毎に共通であるBGL線(以下、単に「BGL」と言う、又BGL−1は第1番目のBGLで、BGL−Mは第M番目のBGLを示す)に接続されている。
ャネル領域4はゲート絶縁膜7、8(27、28)を介してゲート電極9、10(29、30)と容量結合しているので、m行及びn列の半導体記憶装置Hのチャネル領域4の電位は上昇する。各半導体記憶装置Hのうち、m行n列の半導体記憶装置Hのみ両ゲート電極9、10(29、30)の双方に高電位が印加されるのに対し、他の半導体記憶装置Hは一方のゲート電極のみに高電位が印加され、他方のゲート電極には低電位が印加される。
チャネル領域の上下に存在する場合にも適用することが可能である。但し、上述の実施例に示したような構造にすると二つのゲートの位置を容易に揃えられるという利点がある。
2 埋め込み絶縁膜
3 半導体基板
4 チャネル領域
5、6、25 ソース/ドレイン層
7、27 第1のゲート絶縁膜
8、28 第2のゲート絶縁膜
9、29 第1のゲート電極
10、30 第2のゲート電極
20 第1のSiO2膜
21 第2のSiO2膜
22 多結晶シリコン
Claims (11)
- 半導体基板と、
前記半導体基板の主面上に形成された一導電型の半導体層と、
前記半導体基板の主面上に前記半導体層の一端と接して形成され、且つ前記半導体層と逆導電型を有するソース/ドレイン層と、
前記半導体層の一側面に形成された第1の絶縁膜と、
前記半導体層の前記一側面と相対向する他側面に形成された第2の絶縁膜と、
前記半導体層の前記一側面に前記第1の絶縁膜を介して形成された第1のゲート電極と、
前記半導体層の前記他側面に前記第2の絶縁膜を介して形成され、且つ前記第1のゲート電極と相対向する第2のゲート電極と、
を具備し、前記第1のゲート電極と第2のゲート電極を結ぶ方向に流れる電流により、前記半導体層に蓄積される情報を検知することを特徴とする半導体記憶装置。 - 更に、前記ソース/ドレイン層を、前記半導体層の前記一端と相対向する他端に接して前記半導体基板の主面上に設けたことを特徴とする請求項1に記載の半導体記憶装置。
- 半導体基板と、
前記半導体基板の主面上に形成された一導電型の半導体層と、
前記半導体基板の主面上と前記半導体層との間に形成され、且つ前記第1の半導体層と逆導電型を有するソース/ドレイン層と、
前記半導体層の一側面に形成された第1の絶縁膜と、
前記半導体層の前記一側面と相対向する他側面に形成された第2の絶縁膜と、
前記半導体層の前記一側面に前記第1の絶縁膜を介して形成された第1のゲート電極と、
前記半導体層の前記他側面に前記第2の絶縁膜を介して形成され、且つ前記第1のゲート電極と相対向する第2のゲート電極と、
を具備し、前記第1のゲート電極と第2のゲート電極を結ぶ方向に流れる電流により、前記半導体層に蓄積される情報を検知することを特徴とする半導体記憶装置。 - 更に、前記ソース/ドレイン層を、前記半導体層の前記一端と相対向する他端に接して
前記半導体基板の主面上に設けたことを特徴とする請求項3に記載の半導体記憶装置。 - 前記半導体層に蓄積される情報を検知する際、前記半導体層と前記ソース/ドレイン層の間のpn接合を逆方向バイアスすることを特徴とする請求項1乃至請求項4のいずれか1項に記載の半導体記憶装置。
- 前記第1及び第2のゲート電極を結ぶ方向に流れる電流は、前記両ゲート電極間の所定の電位差において極大値を有し、前記電位差は前記半導体層に蓄積された情報によって異なることを特徴とする請求項1乃至請求項5のいずれか1項に記載の半導体記憶装置。
- 前記第1及び第2のゲート絶縁膜の少なくとも一方の前記ゲート絶縁膜は、前記半導体層の多数キャリアに対するエネルギー障壁が、前記半導体層の少数キャリアに対するエネルギー障壁より高いことを特徴とする請求項1乃至請求項6のいずれか1項に記載の半導体記憶装置。
- 前記第1及び第2のゲート電極を結ぶ方向における前記半導体層の幅は、5nm以下であることを特徴とする請求項1乃至請求項7のいずれか1項に記載の半導体記憶装置。
- 前記第1及び第2のゲート絶縁膜の厚さは、2.1nm未満であることを特徴とする請求項1乃至請求項8のいずれか1項に記載の半導体記憶装置。
- 前記半導体層の端部は、前記第1及び第2のゲート電極の側面より外側に位置することを特徴とする請求項1乃至請求項9のいずれか1項に記載の半導体記憶装置。
- 前記第1及び第2のゲート電極は、前記半導体層の導電型と逆導電型を有する半導体であることを特徴とする請求項1乃至請求項10のいずれか1項に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004293172A JP4249684B2 (ja) | 2004-10-06 | 2004-10-06 | 半導体記憶装置 |
US11/244,201 US7449713B2 (en) | 2004-10-06 | 2005-10-06 | Semiconductor memory device |
US12/285,258 US7989867B2 (en) | 2004-10-06 | 2008-10-01 | Semiconductor memory device having a semiconductor layer disposed between first and second gate electrodes |
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JP2004293172A JP4249684B2 (ja) | 2004-10-06 | 2004-10-06 | 半導体記憶装置 |
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JP2006108396A JP2006108396A (ja) | 2006-04-20 |
JP4249684B2 true JP4249684B2 (ja) | 2009-04-02 |
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JP4535896B2 (ja) * | 2005-02-08 | 2010-09-01 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8217435B2 (en) | 2006-12-22 | 2012-07-10 | Intel Corporation | Floating body memory cell having gates favoring different conductivity type regions |
US8026553B2 (en) | 2007-05-10 | 2011-09-27 | Kabushiki Kaisha Toshiba | Semiconductor memory device and manufacturing method thereof |
KR20090116088A (ko) | 2008-05-06 | 2009-11-11 | 삼성전자주식회사 | 정보 유지 능력과 동작 특성이 향상된 커패시터리스 1t반도체 메모리 소자 |
US7969808B2 (en) | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
KR101308048B1 (ko) | 2007-10-10 | 2013-09-12 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR20090075063A (ko) * | 2008-01-03 | 2009-07-08 | 삼성전자주식회사 | 플로팅 바디 트랜지스터를 이용한 동적 메모리 셀을 가지는메모리 셀 어레이를 구비하는 반도체 메모리 장치 및 이장치의 동작 방법 |
KR20100070158A (ko) | 2008-12-17 | 2010-06-25 | 삼성전자주식회사 | 커패시터가 없는 동작 메모리 셀을 구비한 반도체 메모리 장치 및 이 장치의 동작 방법 |
KR101442177B1 (ko) | 2008-12-18 | 2014-09-18 | 삼성전자주식회사 | 커패시터 없는 1-트랜지스터 메모리 셀을 갖는 반도체소자의 제조방법들 |
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US5828079A (en) * | 1992-06-29 | 1998-10-27 | Matsushita Electric Industrial Co., Ltd. | Field-effect type superconducting device including bi-base oxide compound containing copper |
US5604154A (en) * | 1994-10-27 | 1997-02-18 | Nippon Telegraph And Telephone Corporation | Method of manufacturing coulamb blockade element using thermal oxidation |
US6716684B1 (en) * | 2000-11-13 | 2004-04-06 | Advanced Micro Devices, Inc. | Method of making a self-aligned triple gate silicon-on-insulator device |
US6630388B2 (en) * | 2001-03-13 | 2003-10-07 | National Institute Of Advanced Industrial Science And Technology | Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same |
JP3658564B2 (ja) | 2002-01-17 | 2005-06-08 | 株式会社東芝 | 半導体装置 |
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- 2004-10-06 JP JP2004293172A patent/JP4249684B2/ja not_active Expired - Fee Related
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2005
- 2005-10-06 US US11/244,201 patent/US7449713B2/en not_active Expired - Fee Related
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US20090050877A1 (en) | 2009-02-26 |
US7449713B2 (en) | 2008-11-11 |
US7989867B2 (en) | 2011-08-02 |
JP2006108396A (ja) | 2006-04-20 |
US20060081851A1 (en) | 2006-04-20 |
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