JP4203536B2 - 配線基板の製造方法、及び配線基板 - Google Patents
配線基板の製造方法、及び配線基板 Download PDFInfo
- Publication number
- JP4203536B2 JP4203536B2 JP2008126083A JP2008126083A JP4203536B2 JP 4203536 B2 JP4203536 B2 JP 4203536B2 JP 2008126083 A JP2008126083 A JP 2008126083A JP 2008126083 A JP2008126083 A JP 2008126083A JP 4203536 B2 JP4203536 B2 JP 4203536B2
- Authority
- JP
- Japan
- Prior art keywords
- metal foil
- conductor
- wiring board
- wiring
- dielectric sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
5 金属箔密着体
10 積層シート体
11 第一誘電体シート
20 支持基板
21 下地誘電体シート
100 配線積層部
Claims (5)
- 誘電体層と導体層とが交互に積層された配線基板の製造方法であって、
支持基板に、分離可能な金属箔を含む金属箔密着体を介して、前記金属箔密着体上に配置された第一誘電体シートと前記第一誘電体シート上に配置された第一導体層と前記金属箔密着体と前記第一導体層とを接続するように前記第一誘電体シート内に形成された導体とを有する配線積層部を形成する工程と、
前記金属箔密着体に含まれる前記金属箔を分離して、前記配線積層部の前記第一誘電体シートが構成する主表面に少なくとも1つの前記金属箔が付着した状態で、前記配線積層部を前記支持基板から剥離する工程と、
前記配線積層部に付着した前記金属箔を除去し、前記配線積層部の前記主表面を露出させると共に、前記導体の一部をエッチングする金属箔除去工程と、
を備える、配線基板の製造方法。 - 請求項1に記載の配線基板の製造方法であって、
前記主表面は電子部品が搭載される電子部品搭載面であり、
前記第一誘電体シートに形成された前記導体は、前記主表面に電子部品が搭載されたときに前記電子部品に導通する導体である、配線基板の製造方法。 - 請求項1または請求項2に記載の配線基板の製造方法であって、
前記金属箔除去工程は、前記第一誘電体シートの孔内に形成された前記導体の端面が前記孔内に位置することとなるようにエッチングする工程である、配線基板の製造方法。 - 請求項3に記載の配線基板の製造方法であって、
前記金属箔除去工程は、前記導体の端面と前記主表面との距離Dと前記第一誘電体シートの前記孔の最大径Wとの比D/Wが0超過0.5以下となるように、エッチングする工程である、配線基板の製造方法。 - 請求項3または請求項4に記載の配線基板の製造方法であって、さらに、
前記導体の端面に金属端子を接続する工程を備える、配線基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008126083A JP4203536B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003206800 | 2003-08-08 | ||
JP2008126083A JP4203536B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004055503A Division JP4549695B2 (ja) | 2003-08-08 | 2004-02-27 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008227537A JP2008227537A (ja) | 2008-09-25 |
JP4203536B2 true JP4203536B2 (ja) | 2009-01-07 |
Family
ID=39752849
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008125999A Expired - Fee Related JP4203535B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008126083A Expired - Fee Related JP4203536B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008126094A Expired - Fee Related JP4203537B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008126095A Expired - Fee Related JP4203538B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008286947A Pending JP2009076928A (ja) | 2003-08-08 | 2008-11-07 | 配線基板の製造方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008125999A Expired - Fee Related JP4203535B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008126094A Expired - Fee Related JP4203537B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008126095A Expired - Fee Related JP4203538B2 (ja) | 2003-08-08 | 2008-05-13 | 配線基板の製造方法、及び配線基板 |
JP2008286947A Pending JP2009076928A (ja) | 2003-08-08 | 2008-11-07 | 配線基板の製造方法 |
Country Status (1)
Country | Link |
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JP (5) | JP4203535B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5527586B2 (ja) * | 2009-12-17 | 2014-06-18 | 日立化成株式会社 | 多層配線基板 |
TWI400025B (zh) * | 2009-12-29 | 2013-06-21 | Subtron Technology Co Ltd | 線路基板及其製作方法 |
CN103781292B (zh) * | 2012-10-17 | 2017-09-19 | 碁鼎科技秦皇岛有限公司 | 电路板及其制作方法 |
JP6169894B2 (ja) * | 2013-05-28 | 2017-07-26 | 日東電工株式会社 | 配線回路基板 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3811680B2 (ja) * | 2003-01-29 | 2006-08-23 | 富士通株式会社 | 配線基板の製造方法 |
JP4549695B2 (ja) * | 2003-08-08 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
-
2008
- 2008-05-13 JP JP2008125999A patent/JP4203535B2/ja not_active Expired - Fee Related
- 2008-05-13 JP JP2008126083A patent/JP4203536B2/ja not_active Expired - Fee Related
- 2008-05-13 JP JP2008126094A patent/JP4203537B2/ja not_active Expired - Fee Related
- 2008-05-13 JP JP2008126095A patent/JP4203538B2/ja not_active Expired - Fee Related
- 2008-11-07 JP JP2008286947A patent/JP2009076928A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JP4203535B2 (ja) | 2009-01-07 |
JP2008193130A (ja) | 2008-08-21 |
JP2008227537A (ja) | 2008-09-25 |
JP2008244491A (ja) | 2008-10-09 |
JP4203537B2 (ja) | 2009-01-07 |
JP4203538B2 (ja) | 2009-01-07 |
JP2009076928A (ja) | 2009-04-09 |
JP2008227538A (ja) | 2008-09-25 |
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