JP4169882B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP4169882B2
JP4169882B2 JP24248699A JP24248699A JP4169882B2 JP 4169882 B2 JP4169882 B2 JP 4169882B2 JP 24248699 A JP24248699 A JP 24248699A JP 24248699 A JP24248699 A JP 24248699A JP 4169882 B2 JP4169882 B2 JP 4169882B2
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electrode
semiconductor device
conductive foil
diameter portion
protrusions
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JP2001068502A (ja
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徳弘 内山
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NEC Electronics Corp
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NEC Electronics Corp
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Description

【０００１】
【発明の属する技術分野】
本発明はパワーＭＯＳＦＥＴやパワートランジスタなどの大電流を取り扱う半導体装置に関し、特に導通時の電気抵抗（オン抵抗）が小さい半導体ペレットを備えた半導体装置に関する。
【０００２】
【従来の技術】
最近では広い分野で省エネルギーへの対応が要請されており、電力制御装置などの電子回路装置でも具体的にオン抵抗が小さい半導体装置を採用することにより電力効率を高め、省エネルギー化を図っている。
そのため半導体装置本体である半導体ペレットについて耐電圧を高めると同時にオン抵抗を低減しさらには電極間容量を低減するなどの多くの提案がなされ、電力用ＭＯＳＦＥＴでは、数１０ｍΩ程度の低オン抵抗の半導体装置が実用化されている。
一方、オン抵抗が小さな半導体装置は電力用だけでなくスイッチ素子一般に用いられ、小電力分野では小型化も要求されている。
図６及び図７は低オン抵抗の半導体装置の一例を示す。図において、１は半導体ペレットで、内部に半導体素子（図示せず）が形成されている。半導体素子が主電流を制御する電極を有するサイリスタやトランジスタ、ＭＯＳＦＥＴの場合、一方の主面のほぼ全面に主電流が流入するアノードまたはドレインなどの第１の電極２が形成され、他の主面の微小面積領域に制御用のゲート電極（第２の電極）３が形成され、残りの領域に主電流が流出するカソードまたはソースなどの第３の電極４が形成されている。５は半導体ペレット１をマウントしたアイランドで、半導体ペレット１とアイランド５の接続には電気抵抗が小さい半田６が一般的に用いられる。
７は図示例では３本一組のリードで、中間部乃至外端部が平行配置され、中央のリード７ａがアイランド５に電気的、機械的に接続され、他のリード７ｂ、７ｃはリード７ａの両側に配置され、それぞれの内端部がアイランド５の近傍に配置されている。
８は第２の電極３とリード７ｂを電気的に接続する第１のワイヤ、９は第３の電極４とリード７ｃを電気的に接続する第２のワイヤを示す。１０はアイランドの全面と半導体ペレット１を含む主要部分を被覆した樹脂で、各リード７はこの樹脂１０の側壁から導出され、必要に応じて折り曲げ成形される。
この半導体装置の第１電極２は半導体ペレット１内部のオン抵抗より格段に小さい電気抵抗値の半田６、アイランド５を経由してリード７ａに直列接続されている。
また、第２電極３に接続された第１のワイヤ８を通過する電流は主電流に比較して格段に小さく電圧降下を無視できるため細いものを用いることができる。
一方、第３の電極４からリード７ｂへは、第１の電極２に流入した電流とほぼ等しい電流が流出するため、この電流値に応じてワイヤ９の径が決定される。
ワイヤ９は一般的に金、銅、アルミニウムの金属や合金が用いられる。
金や銅は導電性が良好であるが、高価であるため太いものを用いることが困難で径小のワイヤを図６に示すように複数本、図示例では３本並列接続している。
またアルミニウムは安価ではあるが導電性が金や銅に比して劣るため径大のワイヤを複数本並列接続している。
【０００３】
【発明が解決しようとする課題】
ところが、リード７ｃとワイヤ９とを比較すると、ワイヤ９の全断面積はリード７ｃの断面積に比して格段に小さいため、電気抵抗は格段に大きい。
また第１の電極２から流入し半導体ペレット１内を移動した主電流は薄い第３の電極４に到達した後、その表面を移動してワイヤ９に到達するため、第３の電極４自体の抵抗値も無視できない。
そのためリード７ａ、７ｃ間の抵抗値はワイヤ９の径だけでなく、その長さや第３の電極４との接続状態、接続位置によっても影響を受けるため、低オン抵抗の半導体ペレット１の場合、上記影響を無視することができず改善が望まれていた。
また、ワイヤ９を多数本並列接続すれば抵抗値は低減できるが、接続作業に時間を要し、製造コストが上昇するという問題もあった。
このような問題を解決する方法として、ワイヤ９の代わりに導電箔を用いることが知られている。
具体的に、例えば３本並列接続された直径４００μｍのアルミニウムワイヤの場合、厚さ２００μｍ、巾６２８μｍのアルミニウム箔に置換可能である。
アルミニウムの場合、熱圧着、超音波ボンディングにより直接接続でき、金や銀の薄い膜を形成することにより半田付け接続も可能である。
ところが、断面積が等しい一枚のアルミニウム箔は複数本のアルミニウムワイヤに比して表面積が大きく、樹脂１０との接着面積が大きくなるため、半導体装置の動作開始、動作停止時の温度の上昇、下降による熱膨張、収縮によって、第３の電極４とアルミニウム箔の接続界面に熱膨張差によるストレスがかかり、オン、オフ動作を繰り返すと、接続界面にクラックを生じ、最終的に電気的接続が損なわれるという問題があった。
この問題は導電箔と第３電極４の接続面積が大きいほど顕著で、オン抵抗の低減とともに改善が望まれていた。
【０００４】
【課題を解決するための手段】
本発明は上記課題の解決を目的として提案されたもので、一主面に主電流が流入または流出する第１の電極が形成され、他の主面には主電流を制御する小面積の第２の電極及び主電流が流出または流入する大面積の第３の電極がそれぞれ形成された半導体ペレットを、その第１の電極をアイランドに電気的に接続してマウントし、第２、第３の電極をそれぞれリードに電気的に接続し、半導体ペレットを含む主要部分を樹脂にて被覆した半導体装置において、上記第３の電極と導電箔の一端側とを互いに離隔配置した易溶性導電材料を介して接続するとともに、この導電箔の他端をリードに接続したことを特徴とする半導体装置を提供する。
【０００５】
【発明の実施の形態】
本発明による半導体装置は、半導体ペレット上の主電流が流れる大面積の第３の電極とリードとを接続する導電部材として導電箔を用い、この導電箔と第３電極とを離隔配置した易溶性導電材料を介して接続することを特徴とするが、第３の電極又は導電箔に易溶性導電材料からなる異径突起の径大部を接続し、異径突起の径小部を対向する導電箔又は第３の電極に接続する。この場合、異径突起の径大部を第３の電極又は導電箔に超音波接続し、異径突起の径小部を対向する導電箔又は第３の電極に溶融接続する。
【０００６】
【実施例】
以下に本発明の実施例を図１及び図２から説明する。図において、図６及び図７と同一物には同一符号を付し、重複する説明を省略する。本発明による半導体装置は半導体ペレット１上の第３電極４とリード７ｃとを導電箔１１により電気的に接続し、さらにこの導電箔１１と第３の電極４とを互いに離隔配置した易溶性導電材料１２を介して接続した点で、図６に示した半導体装置と大きく異なる。以下にこの半導体装置の製造方法を図３乃至図５から説明する。先ず、図３に示すように予め半導体ペレット１が半田付けされたアイランド５をガイドレール１３上で位置決めする。アイランド５と一体化されたリード７は製造過程では中間部と外端部が連結条により連結され全てのリード７ａ、７ｂ、７ｃが一体化されている。またガイドレール１３にはヒータが埋設されているが図示省略している。このガイドレール１３の位置決めポジションには側上方に超音波振動が付与され、上下動し、一端部にキャピラリ１４が固定されたホーン１５が配置されている。このキャピラリ１４には易溶性導電部材、例えばＰｂ−Ｓｎ系合金、Ａｇ−Ｓｎ−Ｃｕ系合金からなるワイヤ１６が挿通され、このワイヤ１６の下端に放電などによりボール１６ａを形成している。一例としてワイヤ径は４００μｍ、ボール径は８００μｍに設定される。次に図４に示すように、ホーン１５を降下させてボール１６ａをキャピラリ１４の下端で第３の電極４に押し付け、超音波振動を付与して接続するとボール１６ａは押し潰される。このようにして接続を完了しキャピラリ１４とともにワイヤ１６を引き上げると、ワイヤ１６は押し潰されたボールの近傍で図示点線状態に引き切られて径大部１２ａと径小部１２ｂを有する異径突起１２が形成される。このようにして異径突起１２を形成した後、キャピラリ１４位置をずらせて、第３電極４上の異なる位置に異径突起１２を多数形成する。上記突起１２の数は、第３の電極４の露呈全面積に積層する易溶性導電部材の厚さを設定し、この全体積を突起１２一個当たりの体積で割ることにより概略決定できる。各突起１２をほぼ等間隔に配列すればよい。次に図５に示すように、両端部に銅または金、あるいはそれらを順次積層した薄膜１７ａ、１７ｂを形成した導電箔、例えば銅箔１１を加熱手段（図示せず）を備えた吸着ヘッド１８で吸着して、吸着した一端側を異径突起１２上に、他端側をリード７ｃ上に配置し降下させる。吸着ヘッド１８は図示省略するがロードセルにより一つの突起当たり１０〜３０ｇの一定荷重がかかるように設定され、最降下位置で第３の電極４と導電箔１１が所定間隔となるように設定されている。このようにして導電箔１１の位置決めが完了すると導電箔１１の他端側を溶接、熱圧着、超音波接続など図外の手段によりリード７ｃ電気的に接続して固定し、さらに吸着手段１８により加熱しつつ導電箔１１を降下させて異径突起１２の小径部１２ｂに近接させさらに接触させて溶融させ導電箔１１と第３の電極４とを異径突起１２を介して電気的に接続する。ガイドレール１３のヒータ温度は異径突起１２が溶融しない程度の温度に設定することにより径小部１２ｂが溶融する間、径大部１２ａは位置ずれしない。また径小部１２ｂは先端から順次溶融して導電箔１１の薄膜１７ａに拡がるため、その表面が酸化していても溶融した半田素地を薄膜１７ａに接触させることができる。このようにして導電箔１１と第３の電極４の電気的接続が完了すると、吸着手段１８の加熱を停止し吸着を解除して導電箔１１を解放する。この半導体装置は、ワイヤ１６を第３電極４に超音波接続しているため、異径突起１２と第３電極との電気的接続が確実で、しかも突起１２は第３電極４の領域内に分散配置されているため、各突起１２を流れる主電流のばらつきが少なく、小径部１２ｂと導電箔１１の間の電気的接続も確実にできるため、リード７ａ、７ｃ間のオン抵抗即ち、半導体装置のオン抵抗を最小にできる。また、導電箔１１が島状の異径突起１２によって多点接続されているため、熱膨張、収縮を吸収することが出来、導電箔１１と第３の電極４の接続界面にストレスがかかってもこれを緩和することができ、接続界面にクラックを生じにくく、信頼性の高い半導体装置を実現できる。本発明は上記実施例にのみ限定されるものではなく、例えば突起１２は半導体ペレット１の第３電極４に形成するだけでなく、導電箔１１に予め形成してもよい。この場合にはアイランド５側の温度を高め、第３の電極４に接触した突起が溶融するようにすれば良い。また、突起１２は両端の径が異なる異径突起だけでなく、半球体状の突起でもよい。さらには、突起１２は最終的に全体を溶融させて、島状の突起を互いに溶融連結させてもよい。この場合でも、各島状突起の中心位置のずれが少なく、易溶性導電材料の厚みのばらつきを小さくでき、第３の電極４と導電箔１１を平行に保って所定の間隔で接続することが出来る。
【０００７】
【発明の効果】
以上のように本発明によれば、主電流が流れる電極と易溶性導電材料との間を低抵抗で接続でき、易溶性導電材料を流れる電流密度のばらつきが少なく、易溶性導電材料と導電箔との間を低抵抗で接続でき、小径部１２ｂと導電箔１１の電気的接続も確実にできるため、リード７ａ、７ｃ間のオン抵抗即ち、半導体装置のオン抵抗を最小にできる。
【図面の簡単な説明】
【図１】 本発明による半導体装置の実施例を示す一部破断平断面図
【図２】 図１半導体装置の側断面図
【図３】 図１半導体装置の製造方法を示す側断面図
【図４】 第３の電極上に易溶性導電材料を用いた突起を形成する方法を示す要部側断面図
【図５】 図４状態で形成された突起を介して第３の電極と導電箔とを電気的に接続する方法を示す要部拡大側断面図
【図６】 電力用半導体装置の一例を示す平断面図
【図７】 図６半導体装置の側断面図
【符号の説明】
１ 半導体ペレット
２ 第１の電極
３ 第２の電極
４ 第３の電極
５ アイランド
８ リード
１０ 樹脂
１１ 導電箔
１２ 易溶性導電材料（突起）

Claims (8)

  1. 一主面に主電流が流入または流出する第１の電極が形成され、他の主面には主電流を制御する小面積の第２の電極及び主電流が流出または流入する大面積の第３の電極がそれぞれ形成された半導体ペレットを、その第１の電極をアイランドに電気的に接続してマウントし、前記第２、第３の電極をそれぞれリードに電気的に接続し、前記半導体ペレットを含む主要部分を樹脂にて被覆した半導体装置において、
    前記リードとは別体の導電箔を更に有し、
    前記第３の電極と前記導電箔の一端側とを、複数の突起を介して多点接続するとともに、前記導電箔の他端を、対応する前記リードに接続したことを特徴とする半導体装置。
  2. 前記複数の突起はそれぞれ径大部と径小部を有し、前記径大部を第３の電極又は前記導電箔に接続し、これに対する接続対象の前記導電箔又は前記第３の電極を前記径小部に接続したことを特徴とする請求項１に記載の半導体装置。
  3. 前記複数の突起は、ほぼ等間隔に配列されていることを特徴とする請求項１または２に記載の半導体装置。
  4. 前記複数の突起は、Ｓｎを含む合金により形成されていることを特徴とする請求項１乃至３のいずれか一項に記載の半導体装置。
  5. アイランドに半導体ペレットをマウントし、前記半導体ペレットの上面に形成された電極とリードとを前記リードとは別体の導電箔を介して電気的に接続し、前記リードの少なくとも一部と前記半導体ペレットと前記導電箔とを樹脂にて被覆する半導体装置の製造方法において、
    前記電極又は前記導電箔に、複数の突起を形成し、
    前記複数の突起に、接続対象である前記導電箔又は前記電極を接触させ、荷重をかけて加熱することにより、前記電極と前記導電箔とを多点接続することを特徴とする半導体装置の製造方法。
  6. 前記複数の突起は、それぞれ径大部と径小部とを有し、
    キャピラリの中に挿通された、前記複数の突起の形成材料となるワイヤを、前記キャピラリの下端にてボール状に成形し、
    前記ボールを前記電極又は前記導電箔に接触させ、前記キャピラリで前記ボールに超音波振動を付与して押し潰すことにより前記径大部を形成し、
    その後前記キャピラリを引き上げて前記ワイヤを引き切ることにより前記径小部を形成することを特徴とする請求項５に記載の半導体装置の製造方法。
  7. 前記複数の突起の形成材料は、Ｓｎを含む合金であることを特徴とする請求項６に記載の半導体装置の製造方法。
  8. 前記電極と前記導電箔の間隔が所定間隔となるように加熱しつつ荷重をかけることにより、前記複数の突起を互いに溶融連結させたことを特徴とする請求項７に記載の半導体装置の製造方法。
JP24248699A 1999-08-30 1999-08-30 半導体装置およびその製造方法 Expired - Fee Related JP4169882B2 (ja)

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JP4722757B2 (ja) 2006-04-19 2011-07-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4746061B2 (ja) * 2008-02-12 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置
JP5075168B2 (ja) * 2009-07-10 2012-11-14 三菱電機株式会社 電力用半導体装置および電力用半導体装置の製造方法
JP5793295B2 (ja) * 2010-12-16 2015-10-14 新電元工業株式会社 半導体装置
JP2015019115A (ja) * 2014-10-28 2015-01-29 ルネサスエレクトロニクス株式会社 半導体装置
JP2016040839A (ja) * 2015-10-27 2016-03-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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