JP4129212B2 - 半導体素子収納用パッケージおよび半導体装置 - Google Patents
半導体素子収納用パッケージおよび半導体装置 Download PDFInfo
- Publication number
- JP4129212B2 JP4129212B2 JP2003304515A JP2003304515A JP4129212B2 JP 4129212 B2 JP4129212 B2 JP 4129212B2 JP 2003304515 A JP2003304515 A JP 2003304515A JP 2003304515 A JP2003304515 A JP 2003304515A JP 4129212 B2 JP4129212 B2 JP 4129212B2
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- JP
- Japan
- Prior art keywords
- line conductor
- semiconductor element
- side wall
- lead terminal
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
1a:戴置部
2:側壁
3:入出力部
4:線路導体
4a:外側線路導体
4b:突条
5:ロウ材
5a:メニスカス
6:リード端子
7:半導体素子
8:蓋体
A:半導体素子収納用パッケージ
B:半導体装置
Claims (2)
- 上面に形成された凹部の底面に半導体素子を載置する載置部を有するセラミックスから成る基体と、該基体の側壁の内外面に互いに対向するように設けられた2つの段差の底面にわたってその中央部に前記側壁を貫通するメタライズ層から成る線路導体が形成されるとともに前記側壁の外面側の前記線路導体にリード端子がロウ付けされる入出力部とを具備しており、前記側壁の外面側の前記段差の底面の前記線路導体上に、上端で前記リード端子を支持する同じ高さのメタライズ法によって形成された突条が前記線路導体の線路方向に垂直な方向に複数設けられ、かつ前記突条を構成する金属粉末の平均粒径が前記線路導体を構成する金属粒子の平均粒径の1.5乃至3倍であることを特徴とする半導体素子収納用パッケージ。
- 請求項1に記載の半導体素子収納用パッケージと、前記載置部に載置固定されるとともに前記入出力部に電気的に接続された半導体素子と、前記基体の前記側壁の上面に接合された蓋体とを具備したことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003304515A JP4129212B2 (ja) | 2003-08-28 | 2003-08-28 | 半導体素子収納用パッケージおよび半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003304515A JP4129212B2 (ja) | 2003-08-28 | 2003-08-28 | 半導体素子収納用パッケージおよび半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005079145A JP2005079145A (ja) | 2005-03-24 |
JP4129212B2 true JP4129212B2 (ja) | 2008-08-06 |
Family
ID=34408184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003304515A Expired - Fee Related JP4129212B2 (ja) | 2003-08-28 | 2003-08-28 | 半導体素子収納用パッケージおよび半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4129212B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6867263B2 (ja) * | 2017-09-26 | 2021-04-28 | 京セラ株式会社 | 接合構造および半導体パッケージ |
WO2020049723A1 (ja) * | 2018-09-07 | 2020-03-12 | 三菱電機株式会社 | 光モジュール |
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2003
- 2003-08-28 JP JP2003304515A patent/JP4129212B2/ja not_active Expired - Fee Related
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JP2005079145A (ja) | 2005-03-24 |
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