JP4127054B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4127054B2
JP4127054B2 JP2003005804A JP2003005804A JP4127054B2 JP 4127054 B2 JP4127054 B2 JP 4127054B2 JP 2003005804 A JP2003005804 A JP 2003005804A JP 2003005804 A JP2003005804 A JP 2003005804A JP 4127054 B2 JP4127054 B2 JP 4127054B2
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JP
Japan
Prior art keywords
data
address
write
register
bank
Prior art date
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Expired - Fee Related
Application number
JP2003005804A
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English (en)
Japanese (ja)
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JP2004220678A5 (enExample
JP2004220678A (ja
Inventor
賢一 重並
俊一 助川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2003005804A priority Critical patent/JP4127054B2/ja
Priority to US10/749,510 priority patent/US7027347B2/en
Publication of JP2004220678A publication Critical patent/JP2004220678A/ja
Publication of JP2004220678A5 publication Critical patent/JP2004220678A5/ja
Application granted granted Critical
Publication of JP4127054B2 publication Critical patent/JP4127054B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
JP2003005804A 2003-01-14 2003-01-14 半導体記憶装置 Expired - Fee Related JP4127054B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003005804A JP4127054B2 (ja) 2003-01-14 2003-01-14 半導体記憶装置
US10/749,510 US7027347B2 (en) 2003-01-14 2004-01-02 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003005804A JP4127054B2 (ja) 2003-01-14 2003-01-14 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2004220678A JP2004220678A (ja) 2004-08-05
JP2004220678A5 JP2004220678A5 (enExample) 2005-04-07
JP4127054B2 true JP4127054B2 (ja) 2008-07-30

Family

ID=32896373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003005804A Expired - Fee Related JP4127054B2 (ja) 2003-01-14 2003-01-14 半導体記憶装置

Country Status (2)

Country Link
US (1) US7027347B2 (enExample)
JP (1) JP4127054B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585179B1 (ko) * 2005-02-07 2006-06-02 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 데이터 기입및 독출 방법
JP4772546B2 (ja) * 2006-03-17 2011-09-14 富士通セミコンダクター株式会社 半導体メモリ、メモリシステムおよびメモリシステムの動作方法
KR100853469B1 (ko) * 2007-08-29 2008-08-21 주식회사 하이닉스반도체 반도체 메모리장치
JP2009176343A (ja) * 2008-01-22 2009-08-06 Liquid Design Systems:Kk 半導体記憶装置
KR102414690B1 (ko) * 2017-11-30 2022-07-01 에스케이하이닉스 주식회사 반도체 메모리 장치
JP2020140380A (ja) * 2019-02-27 2020-09-03 ローム株式会社 半導体装置及びデバッグシステム
US11545231B2 (en) * 2021-02-09 2023-01-03 Micron Technology, Inc. Reset read disturb mitigation
CN116206649B (zh) * 2022-01-18 2024-03-15 北京超弦存储器研究院 动态存储器及其读写方法、存储装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3112019B2 (ja) 1989-12-08 2000-11-27 株式会社日立製作所 半導体装置
JP3713312B2 (ja) * 1994-09-09 2005-11-09 株式会社ルネサステクノロジ データ処理装置

Also Published As

Publication number Publication date
US20040190363A1 (en) 2004-09-30
US7027347B2 (en) 2006-04-11
JP2004220678A (ja) 2004-08-05

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