JP4125644B2 - 多層回路基板の形成方法および多層回路基板 - Google Patents

多層回路基板の形成方法および多層回路基板 Download PDF

Info

Publication number
JP4125644B2
JP4125644B2 JP2003188290A JP2003188290A JP4125644B2 JP 4125644 B2 JP4125644 B2 JP 4125644B2 JP 2003188290 A JP2003188290 A JP 2003188290A JP 2003188290 A JP2003188290 A JP 2003188290A JP 4125644 B2 JP4125644 B2 JP 4125644B2
Authority
JP
Japan
Prior art keywords
circuit board
forming
conductor
mask
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003188290A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004088093A (ja
JP2004088093A5 (enExample
Inventor
和宏 西川
法人 塚原
博之 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2003188290A priority Critical patent/JP4125644B2/ja
Priority to US10/611,868 priority patent/US6971167B2/en
Priority to KR1020030045204A priority patent/KR20040004173A/ko
Priority to CNB031458092A priority patent/CN100466885C/zh
Publication of JP2004088093A publication Critical patent/JP2004088093A/ja
Publication of JP2004088093A5 publication Critical patent/JP2004088093A5/ja
Application granted granted Critical
Publication of JP4125644B2 publication Critical patent/JP4125644B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0179Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0376Flush conductors, i.e. flush with the surface of the printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0582Coating by resist, i.e. resist used as mask for application of insulating coating or of second resist
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/002Etching of the substrate by chemical or physical means by liquid chemical etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0041Etching of the substrate by chemical or physical means by plasma etching
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2003188290A 2002-07-05 2003-06-30 多層回路基板の形成方法および多層回路基板 Expired - Fee Related JP4125644B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003188290A JP4125644B2 (ja) 2002-07-05 2003-06-30 多層回路基板の形成方法および多層回路基板
US10/611,868 US6971167B2 (en) 2002-07-05 2003-07-03 Multilayered circuit board forming method and multilayered circuit board
KR1020030045204A KR20040004173A (ko) 2002-07-05 2003-07-04 다층 회로기판 형성방법 및 다층 회로기판
CNB031458092A CN100466885C (zh) 2002-07-05 2003-07-07 多层电路板的形成方法及多层电路板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002197033 2002-07-05
JP2003188290A JP4125644B2 (ja) 2002-07-05 2003-06-30 多層回路基板の形成方法および多層回路基板

Publications (3)

Publication Number Publication Date
JP2004088093A JP2004088093A (ja) 2004-03-18
JP2004088093A5 JP2004088093A5 (enExample) 2006-05-11
JP4125644B2 true JP4125644B2 (ja) 2008-07-30

Family

ID=31190281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003188290A Expired - Fee Related JP4125644B2 (ja) 2002-07-05 2003-06-30 多層回路基板の形成方法および多層回路基板

Country Status (4)

Country Link
US (1) US6971167B2 (enExample)
JP (1) JP4125644B2 (enExample)
KR (1) KR20040004173A (enExample)
CN (1) CN100466885C (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989327B2 (en) * 2004-01-31 2006-01-24 Hewlett-Packard Development Company, L.P. Forming a contact in a thin-film device
KR100817639B1 (ko) 2004-03-19 2008-03-27 에스에무케이 가부시키가이샤 스크린 프린팅 금속 마스크 판 및 진동부를 수지-밀봉하는방법
JP4345598B2 (ja) * 2004-07-15 2009-10-14 パナソニック株式会社 回路基板の接続構造体とその製造方法
JP2006128520A (ja) * 2004-10-29 2006-05-18 Tdk Corp 多層基板の製造方法
TWI363585B (en) * 2008-04-02 2012-05-01 Advanced Semiconductor Eng Method for manufacturing a substrate having embedded component therein
JP5903793B2 (ja) 2011-08-03 2016-04-13 日本電産株式会社 スピンドルモータの製造方法、スピンドルモータ、およびディスク駆動装置
JP6927665B2 (ja) * 2015-12-25 2021-09-01 日東電工株式会社 配線回路基板
US11089675B2 (en) * 2018-10-22 2021-08-10 Te Connectivity Corporation Tamper sensor
KR102112327B1 (ko) * 2018-12-04 2020-05-18 주식회사 엠디엠 입체 구조물의 표면에 회로 패턴을 형성하는 방법
CN112165767B (zh) * 2020-10-27 2021-12-07 惠州市特创电子科技股份有限公司 多层线路板以及移动通讯装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3324014A (en) * 1962-12-03 1967-06-06 United Carr Inc Method for making flush metallic patterns
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4354895A (en) * 1981-11-27 1982-10-19 International Business Machines Corporation Method for making laminated multilayer circuit boards
US4789423A (en) * 1982-03-04 1988-12-06 E. I. Du Pont De Nemours And Company Method for manufacturing multi-layer printed circuit boards
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
US4915983A (en) * 1985-06-10 1990-04-10 The Foxboro Company Multilayer circuit board fabrication process
US4927477A (en) * 1985-08-26 1990-05-22 International Business Machines Corporation Method for making a flush surface laminate for a multilayer circuit board
JPH0716094B2 (ja) * 1986-03-31 1995-02-22 日立化成工業株式会社 配線板の製造法
US5114518A (en) * 1986-10-23 1992-05-19 International Business Machines Corporation Method of making multilayer circuit boards having conformal Insulating layers
TW210422B (enExample) * 1991-06-04 1993-08-01 Akzo Nv
US5199163A (en) * 1992-06-01 1993-04-06 International Business Machines Corporation Metal transfer layers for parallel processing
JP3758811B2 (ja) 1997-05-30 2006-03-22 京セラ株式会社 転写シート及びそれを用いた配線基板の製造方法

Also Published As

Publication number Publication date
CN1496216A (zh) 2004-05-12
CN100466885C (zh) 2009-03-04
JP2004088093A (ja) 2004-03-18
US20040020047A1 (en) 2004-02-05
US6971167B2 (en) 2005-12-06
KR20040004173A (ko) 2004-01-13

Similar Documents

Publication Publication Date Title
JP4334996B2 (ja) 多層配線板用基材、両面配線板およびそれらの製造方法
JP2002064271A (ja) 複合配線基板及びその製造方法
JP3500995B2 (ja) 積層型回路モジュールの製造方法
US7936061B2 (en) Semiconductor device and method of manufacturing the same
JP4125644B2 (ja) 多層回路基板の形成方法および多層回路基板
US10893618B2 (en) Method for manufacturing multilayer substrate
JP2014524671A (ja) 回路基板
US7839650B2 (en) Circuit board structure having embedded capacitor and fabrication method thereof
US20110154661A1 (en) Method of fabricating printed circuit board assembly
JP4158714B2 (ja) 電子部品実装済基板の製造方法
US11114238B2 (en) Multilayer substrate, structure of multilayer substrate mounted on circuit board, method for mounting multilayer substrate, and method for manufacturing multilayer substrate
JP5581828B2 (ja) 積層回路基板および基板製造方法
JP2004079773A (ja) 多層プリント配線板及びその製造方法
KR101068466B1 (ko) 적층용 단위 기판의 제조방법과, 단위 기판을 이용한 다층 기판 및 그 제조방법
US7728234B2 (en) Coreless thin substrate with embedded circuits in dielectric layers and method for manufacturing the same
CN102281711A (zh) 叠层电路基板以及基板制造方法
JP2542794B2 (ja) 配線板の製造方法
KR102888239B1 (ko) 도전성 보강 구조를 갖는 회로 기판
JP6779088B2 (ja) 配線基板の製造方法
US20220361329A1 (en) Method for Forming Flipped-Conductor-Patch
JP2002368426A (ja) 積層型セラミック電子部品およびその製造方法ならびに電子装置
JPH04299893A (ja) 多層配線板の製造方法
JPH1079578A (ja) 配線基板の製造方法
JP3867526B2 (ja) 多層基板の製造方法
JP2020064996A (ja) 積層電子部品の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060317

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071018

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071023

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080123

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080321

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080415

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080508

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110516

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120516

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees